blob: e2cc7020fa3ba54c21851708496b4195a0ec33c2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
21*/
22
23/*
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
26*/
27
28/* too many macros - change to inline functions */
29
30#ifndef DRIVER_ATM_HORIZON_H
31#define DRIVER_ATM_HORIZON_H
32
33#include <linux/config.h>
34
35#ifdef CONFIG_ATM_HORIZON_DEBUG
36#define DEBUG_HORIZON
37#endif
38
39#define DEV_LABEL "hrz"
40
41#ifndef PCI_VENDOR_ID_MADGE
42#define PCI_VENDOR_ID_MADGE 0x10B6
43#endif
44#ifndef PCI_DEVICE_ID_MADGE_HORIZON
45#define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
46#endif
47
48// diagnostic output
49
50#define PRINTK(severity,format,args...) \
51 printk(severity DEV_LABEL ": " format "\n" , ## args)
52
53#ifdef DEBUG_HORIZON
54
55#define DBG_ERR 0x0001
56#define DBG_WARN 0x0002
57#define DBG_INFO 0x0004
58#define DBG_VCC 0x0008
59#define DBG_QOS 0x0010
60#define DBG_TX 0x0020
61#define DBG_RX 0x0040
62#define DBG_SKB 0x0080
63#define DBG_IRQ 0x0100
64#define DBG_FLOW 0x0200
65#define DBG_BUS 0x0400
66#define DBG_REGS 0x0800
67#define DBG_DATA 0x1000
68#define DBG_MASK 0x1fff
69
70/* the ## prevents the annoying double expansion of the macro arguments */
71/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
72#define PRINTDB(bits,format,args...) \
73 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
74#define PRINTDM(bits,format,args...) \
75 ( (debug & (bits)) ? printk (format , ## args) : 1 )
76#define PRINTDE(bits,format,args...) \
77 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
78#define PRINTD(bits,format,args...) \
79 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
80
81#else
82
83#define PRINTD(bits,format,args...)
84#define PRINTDB(bits,format,args...)
85#define PRINTDM(bits,format,args...)
86#define PRINTDE(bits,format,args...)
87
88#endif
89
90#define PRINTDD(sec,fmt,args...)
91#define PRINTDDB(sec,fmt,args...)
92#define PRINTDDM(sec,fmt,args...)
93#define PRINTDDE(sec,fmt,args...)
94
95// fixed constants
96
97#define SPARE_BUFFER_POOL_SIZE MAX_VCS
98#define HRZ_MAX_VPI 4
99#define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
100
101/* Horizon specific bits */
102/* Register offsets */
103
104#define HRZ_IO_EXTENT 0x80
105
106#define DATA_PORT_OFF 0x00
107#define TX_CHANNEL_PORT_OFF 0x04
108#define TX_DESCRIPTOR_PORT_OFF 0x08
109#define MEMORY_PORT_OFF 0x0C
110#define MEM_WR_ADDR_REG_OFF 0x14
111#define MEM_RD_ADDR_REG_OFF 0x18
112#define CONTROL_0_REG 0x1C
113#define INT_SOURCE_REG_OFF 0x20
114#define INT_ENABLE_REG_OFF 0x24
115#define MASTER_RX_ADDR_REG_OFF 0x28
116#define MASTER_RX_COUNT_REG_OFF 0x2C
117#define MASTER_TX_ADDR_REG_OFF 0x30
118#define MASTER_TX_COUNT_REG_OFF 0x34
119#define TX_DESCRIPTOR_REG_OFF 0x38
120#define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
121#define TX_CHANNEL_CONFIG_DATA_OFF 0x44
122#define TX_FREE_BUFFER_COUNT_OFF 0x48
123#define RX_FREE_BUFFER_COUNT_OFF 0x4C
124#define TX_CONFIG_OFF 0x50
125#define TX_STATUS_OFF 0x54
126#define RX_CONFIG_OFF 0x58
127#define RX_LINE_CONFIG_OFF 0x5C
128#define RX_QUEUE_RD_PTR_OFF 0x60
129#define RX_QUEUE_WR_PTR_OFF 0x64
130#define MAX_AAL5_CELL_COUNT_OFF 0x68
131#define RX_CHANNEL_PORT_OFF 0x6C
132#define TX_CELL_COUNT_OFF 0x70
133#define RX_CELL_COUNT_OFF 0x74
134#define HEC_ERROR_COUNT_OFF 0x78
135#define UNASSIGNED_CELL_COUNT_OFF 0x7C
136
137/* Register bit definitions */
138
139/* Control 0 register */
140
141#define SEEPROM_DO 0x00000001
142#define SEEPROM_DI 0x00000002
143#define SEEPROM_SK 0x00000004
144#define SEEPROM_CS 0x00000008
145#define DEBUG_BIT_0 0x00000010
146#define DEBUG_BIT_1 0x00000020
147#define DEBUG_BIT_2 0x00000040
148// RESERVED 0x00000080
149#define DEBUG_BIT_0_OE 0x00000100
150#define DEBUG_BIT_1_OE 0x00000200
151#define DEBUG_BIT_2_OE 0x00000400
152// RESERVED 0x00000800
153#define DEBUG_BIT_0_STATE 0x00001000
154#define DEBUG_BIT_1_STATE 0x00002000
155#define DEBUG_BIT_2_STATE 0x00004000
156// RESERVED 0x00008000
157#define GENERAL_BIT_0 0x00010000
158#define GENERAL_BIT_1 0x00020000
159#define GENERAL_BIT_2 0x00040000
160#define GENERAL_BIT_3 0x00080000
161#define RESET_HORIZON 0x00100000
162#define RESET_ATM 0x00200000
163#define RESET_RX 0x00400000
164#define RESET_TX 0x00800000
165#define RESET_HOST 0x01000000
166// RESERVED 0x02000000
167#define TARGET_RETRY_DISABLE 0x04000000
168#define ATM_LAYER_SELECT 0x08000000
169#define ATM_LAYER_STATUS 0x10000000
170// RESERVED 0xE0000000
171
172/* Interrupt source and enable registers */
173
174#define RX_DATA_AV 0x00000001
175#define RX_DISABLED 0x00000002
176#define TIMING_MARKER 0x00000004
177#define FORCED 0x00000008
178#define RX_BUS_MASTER_COMPLETE 0x00000010
179#define TX_BUS_MASTER_COMPLETE 0x00000020
180#define ABR_TX_CELL_COUNT_INT 0x00000040
181#define DEBUG_INT 0x00000080
182// RESERVED 0xFFFFFF00
183
184/* PIO and Bus Mastering */
185
186#define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
187// 8188 is a hard limit for bus mastering
188#define MAX_TRANSFER_COUNT 0x00001ffc // 8188
189#define MASTER_TX_AUTO_APPEND_DESC 0x80000000
190
191/* TX channel config command port */
192
193#define PCR_TIMER_ACCESS 0x0000
194#define SCR_TIMER_ACCESS 0x0001
195#define BUCKET_CAPACITY_ACCESS 0x0002
196#define BUCKET_FULLNESS_ACCESS 0x0003
197#define RATE_TYPE_ACCESS 0x0004
198// UNUSED 0x00F8
199#define TX_CHANNEL_CONFIG_MULT 0x0100
200// UNUSED 0xF800
201#define BUCKET_MAX_SIZE 0x003f
202
203/* TX channel config data port */
204
205#define CLOCK_SELECT_SHIFT 4
206#define CLOCK_DISABLE 0x00ff
207
208#define IDLE_RATE_TYPE 0x0
209#define ABR_RATE_TYPE 0x1
210#define VBR_RATE_TYPE 0x2
211#define CBR_RATE_TYPE 0x3
212
213/* TX config register */
214
215#define DRVR_DRVRBAR_ENABLE 0x0001
216#define TXCLK_MUX_SELECT_RCLK 0x0002
217#define TRANSMIT_TIMING_MARKER 0x0004
218#define LOOPBACK_TIMING_MARKER 0x0008
219#define TX_TEST_MODE_16MHz 0x0000
220#define TX_TEST_MODE_8MHz 0x0010
221#define TX_TEST_MODE_5_33MHz 0x0020
222#define TX_TEST_MODE_4MHz 0x0030
223#define TX_TEST_MODE_3_2MHz 0x0040
224#define TX_TEST_MODE_2_66MHz 0x0050
225#define TX_TEST_MODE_2_29MHz 0x0060
226#define TX_NORMAL_OPERATION 0x0070
227#define ABR_ROUND_ROBIN 0x0080
228
229/* TX status register */
230
231#define IDLE_CHANNELS_MASK 0x00FF
232#define ABR_CELL_COUNT_REACHED_MULT 0x0100
233#define ABR_CELL_COUNT_REACHED_MASK 0xFF
234
235/* RX config register */
236
237#define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
238#define RX_ENABLE 0x0010
239#define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
240#define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
241#define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
242
243/* RX line config register */
244
245#define SIGNAL_LOSS 0x0001
246#define FREQUENCY_DETECT_ERROR 0x0002
247#define LOCK_DETECT_ERROR 0x0004
248#define SELECT_INTERNAL_LOOPBACK 0x0008
249#define LOCK_DETECT_ENABLE 0x0010
250#define FREQUENCY_DETECT_ENABLE 0x0020
251#define USER_FRAQ 0x0040
252#define GXTALOUT_SELECT_DIV4 0x0080
253#define GXTALOUT_SELECT_NO_GATING 0x0100
254#define TIMING_MARKER_RECEIVED 0x0200
255
256/* RX channel port */
257
258#define RX_CHANNEL_MASK 0x03FF
259// UNUSED 0x3C00
260#define FLUSH_CHANNEL 0x4000
261#define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
262
263/* Receive queue entry */
264
265#define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
266#define RX_Q_ENTRY_CHANNEL_SHIFT 16
267#define SIMONS_DODGEY_MARKER 0x08000000
268#define RX_CONGESTION_EXPERIENCED 0x10000000
269#define RX_CRC_10_OK 0x20000000
270#define RX_CRC_32_OK 0x40000000
271#define RX_COMPLETE_FRAME 0x80000000
272
273/* Offsets and constants for use with the buffer memory */
274
275/* Buffer pointers and channel types */
276
277#define BUFFER_PTR_MASK 0x0000FFFF
278#define RX_INT_THRESHOLD_MULT 0x00010000
279#define RX_INT_THRESHOLD_MASK 0x07FF
280#define INT_EVERY_N_CELLS 0x08000000
281#define CONGESTION_EXPERIENCED 0x10000000
282#define FIRST_CELL_OF_AAL5_FRAME 0x20000000
283#define CHANNEL_TYPE_AAL5 0x00000000
284#define CHANNEL_TYPE_RAW_CELLS 0x40000000
285#define CHANNEL_TYPE_AAL3_4 0x80000000
286
287/* Buffer status stuff */
288
289#define BUFF_STATUS_MASK 0x00030000
290#define BUFF_STATUS_EMPTY 0x00000000
291#define BUFF_STATUS_CELL_AV 0x00010000
292#define BUFF_STATUS_LAST_CELL_AV 0x00020000
293
294/* Transmit channel stuff */
295
296/* Receive channel stuff */
297
298#define RX_CHANNEL_DISABLED 0x00000000
299#define RX_CHANNEL_IDLE 0x00000001
300
301/* General things */
302
303#define INITIAL_CRC 0xFFFFFFFF
304
305// A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
306// word addresses and so standard C pointer operations break (as they
307// assume byte addresses); so we pretend that Horizon words (and word
308// pointers) are bytes (and byte pointers) for the purposes of having
309// a memory map that works.
310
311typedef u8 HDW;
312
313typedef struct cell_buf {
314 HDW payload[12];
315 HDW next;
316 HDW cell_count; // AAL5 rx bufs
317 HDW res;
318 union {
319 HDW partial_crc; // AAL5 rx bufs
320 HDW cell_header; // RAW bufs
321 } u;
322} cell_buf;
323
324typedef struct tx_ch_desc {
325 HDW rd_buf_type;
326 HDW wr_buf_type;
327 HDW partial_crc;
328 HDW cell_header;
329} tx_ch_desc;
330
331typedef struct rx_ch_desc {
332 HDW wr_buf_type;
333 HDW rd_buf_type;
334} rx_ch_desc;
335
336typedef struct rx_q_entry {
337 HDW entry;
338} rx_q_entry;
339
340#define TX_CHANS 8
341#define RX_CHANS 1024
342#define RX_QS 1024
343#define MAX_VCS RX_CHANS
344
345/* Horizon buffer memory map */
346
347// TX Channel Descriptors 2
348// TX Initial Buffers 8 // TX_CHANS
349#define BUFN1_SIZE 118 // (126 - TX_CHANS)
350// RX/TX Start/End Buffers 4
351#define BUFN2_SIZE 124
352// RX Queue Entries 64
353#define BUFN3_SIZE 192
354// RX Channel Descriptors 128
355#define BUFN4_SIZE 1408
356// TOTAL cell_buff chunks 2048
357
358// cell_buf bufs[2048];
359// HDW dws[32768];
360
361typedef struct MEMMAP {
362 tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
363 cell_buf inittxbufs[TX_CHANS]; // these are really
364 cell_buf bufn1[BUFN1_SIZE]; // part of this pool
365 cell_buf txfreebufstart;
366 cell_buf txfreebufend;
367 cell_buf rxfreebufstart;
368 cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
369 cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
370 rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
371 cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
372 rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
373 cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
374} MEMMAP;
375
376#define memmap ((MEMMAP *)0)
377
378/* end horizon specific bits */
379
380typedef enum {
381 aal0,
382 aal34,
383 aal5
384} hrz_aal;
385
386typedef enum {
387 tx_busy,
388 rx_busy,
389 ultra
390} hrz_flags;
391
392// a single struct pointed to by atm_vcc->dev_data
393
394typedef struct {
395 unsigned int tx_rate;
396 unsigned int rx_rate;
397 u16 channel;
398 u16 tx_xbr_bits;
399 u16 tx_pcr_bits;
400#if 0
401 u16 tx_scr_bits;
402 u16 tx_bucket_bits;
403#endif
404 hrz_aal aal;
405} hrz_vcc;
406
407struct hrz_dev {
408
409 u32 iobase;
410 u32 * membase;
411
412 struct sk_buff * rx_skb; // skb being RXed
413 unsigned int rx_bytes; // bytes remaining to RX within region
414 void * rx_addr; // addr to send bytes to (for PIO)
415 unsigned int rx_channel; // channel that the skb is going out on
416
417 struct sk_buff * tx_skb; // skb being TXed
418 unsigned int tx_bytes; // bytes remaining to TX within region
419 void * tx_addr; // addr to send bytes from (for PIO)
420 struct iovec * tx_iovec; // remaining regions
421 unsigned int tx_regions; // number of remaining regions
422
423 spinlock_t mem_lock;
424 wait_queue_head_t tx_queue;
425
426 u8 irq;
427 long flags;
428 u8 tx_last;
429 u8 tx_idle;
430
431 rx_q_entry * rx_q_reset;
432 rx_q_entry * rx_q_entry;
433 rx_q_entry * rx_q_wrap;
434
435 struct atm_dev * atm_dev;
436
437 u32 last_vc;
438
439 int noof_spare_buffers;
440 u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
441
442 u16 tx_channel_record[TX_CHANS];
443
444 // this is what we follow when we get incoming data
445 u32 txer[MAX_VCS/32];
446 struct atm_vcc * rxer[MAX_VCS];
447
448 // cell rate allocation
449 spinlock_t rate_lock;
450 unsigned int rx_avail;
451 unsigned int tx_avail;
452
453 // dev stats
454 unsigned long tx_cell_count;
455 unsigned long rx_cell_count;
456 unsigned long hec_error_count;
457 unsigned long unassigned_cell_count;
458
459 struct pci_dev * pci_dev;
460 struct timer_list housekeeping;
461};
462
463typedef struct hrz_dev hrz_dev;
464
465/* macros for use later */
466
467#define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
468
469#define INTERESTING_INTERRUPTS \
470 (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
471
472// 190 cells by default (192 TX buffers - 2 elbow room, see docs)
473#define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
474
475// Have enough RX buffers (unless we allow other buffer splits)
476#define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
477
478/* multi-statement macro protector */
479#define DW(x) do{ x } while(0)
480
481#define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
482#define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
483
484/* Turn the LEDs on and off */
485// The LEDs bits are upside down in that setting the bit in the debug
486// register will turn the appropriate LED off.
487
488#define YELLOW_LED DEBUG_BIT_0
489#define GREEN_LED DEBUG_BIT_1
490#define YELLOW_LED_OE DEBUG_BIT_0_OE
491#define GREEN_LED_OE DEBUG_BIT_1_OE
492
493#define GREEN_LED_OFF(dev) \
494 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
495#define GREEN_LED_ON(dev) \
496 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
497#define YELLOW_LED_OFF(dev) \
498 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
499#define YELLOW_LED_ON(dev) \
500 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
501
502typedef enum {
503 round_up,
504 round_down,
505 round_nearest
506} rounding;
507
508#endif /* DRIVER_ATM_HORIZON_H */