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gerrit-public.fairphone.software / kernel / msm-4.9 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / drivers / char / drm / radeon_drv.h
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Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20050311"
42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 */
86#define DRIVER_MAJOR 1
87#define DRIVER_MINOR 16
88#define DRIVER_PATCHLEVEL 0
89
90#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
91#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
92
93/*
94 * Radeon chip families
95 */
96enum radeon_family {
97 CHIP_R100,
98 CHIP_RS100,
99 CHIP_RV100,
100 CHIP_R200,
101 CHIP_RV200,
102 CHIP_RS200,
103 CHIP_R250,
104 CHIP_RS250,
105 CHIP_RV250,
106 CHIP_RV280,
107 CHIP_R300,
108 CHIP_RS300,
109 CHIP_RV350,
110 CHIP_LAST,
111};
112
113enum radeon_cp_microcode_version {
114 UCODE_R100,
115 UCODE_R200,
116 UCODE_R300,
117};
118
119/*
120 * Chip flags
121 */
122enum radeon_chip_flags {
123 CHIP_FAMILY_MASK = 0x0000ffffUL,
124 CHIP_FLAGS_MASK = 0xffff0000UL,
125 CHIP_IS_MOBILITY = 0x00010000UL,
126 CHIP_IS_IGP = 0x00020000UL,
127 CHIP_SINGLE_CRTC = 0x00040000UL,
128 CHIP_IS_AGP = 0x00080000UL,
129 CHIP_HAS_HIERZ = 0x00100000UL,
130};
131
132typedef struct drm_radeon_freelist {
133 unsigned int age;
134 drm_buf_t *buf;
135 struct drm_radeon_freelist *next;
136 struct drm_radeon_freelist *prev;
137} drm_radeon_freelist_t;
138
139typedef struct drm_radeon_ring_buffer {
140 u32 *start;
141 u32 *end;
142 int size;
143 int size_l2qw;
144
145 u32 tail;
146 u32 tail_mask;
147 int space;
148
149 int high_mark;
150} drm_radeon_ring_buffer_t;
151
152typedef struct drm_radeon_depth_clear_t {
153 u32 rb3d_cntl;
154 u32 rb3d_zstencilcntl;
155 u32 se_cntl;
156} drm_radeon_depth_clear_t;
157
158struct drm_radeon_driver_file_fields {
159 int64_t radeon_fb_delta;
160};
161
162struct mem_block {
163 struct mem_block *next;
164 struct mem_block *prev;
165 int start;
166 int size;
167 DRMFILE filp; /* 0: free, -1: heap, other: real files */
168};
169
170struct radeon_surface {
171 int refcount;
172 u32 lower;
173 u32 upper;
174 u32 flags;
175};
176
177struct radeon_virt_surface {
178 int surface_index;
179 u32 lower;
180 u32 upper;
181 u32 flags;
182 DRMFILE filp;
183};
184
185typedef struct drm_radeon_private {
186 drm_radeon_ring_buffer_t ring;
187 drm_radeon_sarea_t *sarea_priv;
188
189 u32 fb_location;
190
191 int gart_size;
192 u32 gart_vm_start;
193 unsigned long gart_buffers_offset;
194
195 int cp_mode;
196 int cp_running;
197
198 drm_radeon_freelist_t *head;
199 drm_radeon_freelist_t *tail;
200 int last_buf;
201 volatile u32 *scratch;
202 int writeback_works;
203
204 int usec_timeout;
205
206 int microcode_version;
207
208 int is_pci;
209 unsigned long phys_pci_gart;
210 dma_addr_t bus_pci_gart;
211
212 struct {
213 u32 boxes;
214 int freelist_timeouts;
215 int freelist_loops;
216 int requested_bufs;
217 int last_frame_reads;
218 int last_clear_reads;
219 int clears;
220 int texture_uploads;
221 } stats;
222
223 int do_boxes;
224 int page_flipping;
225 int current_page;
226
227 u32 color_fmt;
228 unsigned int front_offset;
229 unsigned int front_pitch;
230 unsigned int back_offset;
231 unsigned int back_pitch;
232
233 u32 depth_fmt;
234 unsigned int depth_offset;
235 unsigned int depth_pitch;
236
237 u32 front_pitch_offset;
238 u32 back_pitch_offset;
239 u32 depth_pitch_offset;
240
241 drm_radeon_depth_clear_t depth_clear;
242
243 unsigned long fb_offset;
244 unsigned long mmio_offset;
245 unsigned long ring_offset;
246 unsigned long ring_rptr_offset;
247 unsigned long buffers_offset;
248 unsigned long gart_textures_offset;
249
250 drm_local_map_t *sarea;
251 drm_local_map_t *mmio;
252 drm_local_map_t *cp_ring;
253 drm_local_map_t *ring_rptr;
254 drm_local_map_t *gart_textures;
255
256 struct mem_block *gart_heap;
257 struct mem_block *fb_heap;
258
259 /* SW interrupt */
260 wait_queue_head_t swi_queue;
261 atomic_t swi_emitted;
262
263 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
264 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
265
266 /* starting from here on, data is preserved accross an open */
267 uint32_t flags; /* see radeon_chip_flags */
268} drm_radeon_private_t;
269
270typedef struct drm_radeon_buf_priv {
271 u32 age;
272} drm_radeon_buf_priv_t;
273
274 /* radeon_cp.c */
275extern int radeon_cp_init( DRM_IOCTL_ARGS );
276extern int radeon_cp_start( DRM_IOCTL_ARGS );
277extern int radeon_cp_stop( DRM_IOCTL_ARGS );
278extern int radeon_cp_reset( DRM_IOCTL_ARGS );
279extern int radeon_cp_idle( DRM_IOCTL_ARGS );
280extern int radeon_cp_resume( DRM_IOCTL_ARGS );
281extern int radeon_engine_reset( DRM_IOCTL_ARGS );
282extern int radeon_fullscreen( DRM_IOCTL_ARGS );
283extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
284
285extern void radeon_freelist_reset( drm_device_t *dev );
286extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
287
288extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
289
290extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
291
292extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
293extern int radeon_driver_postcleanup(struct drm_device *dev);
294
295extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
296extern int radeon_mem_free( DRM_IOCTL_ARGS );
297extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
298extern void radeon_mem_takedown( struct mem_block **heap );
299extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
300
301 /* radeon_irq.c */
302extern int radeon_irq_emit( DRM_IOCTL_ARGS );
303extern int radeon_irq_wait( DRM_IOCTL_ARGS );
304
305extern void radeon_do_release(drm_device_t *dev);
306extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
307extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
308extern void radeon_driver_irq_preinstall( drm_device_t *dev );
309extern void radeon_driver_irq_postinstall( drm_device_t *dev );
310extern void radeon_driver_irq_uninstall( drm_device_t *dev );
311extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
312extern void radeon_driver_pretakedown(drm_device_t *dev);
313extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
314extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
315
316extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
317extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
318extern int radeon_postcleanup( struct drm_device *dev );
319
320/* Flags for stats.boxes
321 */
322#define RADEON_BOX_DMA_IDLE 0x1
323#define RADEON_BOX_RING_FULL 0x2
324#define RADEON_BOX_FLIP 0x4
325#define RADEON_BOX_WAIT_IDLE 0x8
326#define RADEON_BOX_TEXTURE_LOAD 0x10
327
328
329
330/* Register definitions, register access macros and drmAddMap constants
331 * for Radeon kernel driver.
332 */
333
334#define RADEON_AGP_COMMAND 0x0f60
335#define RADEON_AUX_SCISSOR_CNTL 0x26f0
336# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
337# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
338# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
339# define RADEON_SCISSOR_0_ENABLE (1 << 28)
340# define RADEON_SCISSOR_1_ENABLE (1 << 29)
341# define RADEON_SCISSOR_2_ENABLE (1 << 30)
342
343#define RADEON_BUS_CNTL 0x0030
344# define RADEON_BUS_MASTER_DIS (1 << 6)
345
346#define RADEON_CLOCK_CNTL_DATA 0x000c
347# define RADEON_PLL_WR_EN (1 << 7)
348#define RADEON_CLOCK_CNTL_INDEX 0x0008
349#define RADEON_CONFIG_APER_SIZE 0x0108
350#define RADEON_CRTC_OFFSET 0x0224
351#define RADEON_CRTC_OFFSET_CNTL 0x0228
352# define RADEON_CRTC_TILE_EN (1 << 15)
353# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
354#define RADEON_CRTC2_OFFSET 0x0324
355#define RADEON_CRTC2_OFFSET_CNTL 0x0328
356
357#define RADEON_RB3D_COLOROFFSET 0x1c40
358#define RADEON_RB3D_COLORPITCH 0x1c48
359
360#define RADEON_DP_GUI_MASTER_CNTL 0x146c
361# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
362# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
363# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
364# define RADEON_GMC_BRUSH_NONE (15 << 4)
365# define RADEON_GMC_DST_16BPP (4 << 8)
366# define RADEON_GMC_DST_24BPP (5 << 8)
367# define RADEON_GMC_DST_32BPP (6 << 8)
368# define RADEON_GMC_DST_DATATYPE_SHIFT 8
369# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
370# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
371# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
372# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
373# define RADEON_GMC_WR_MSK_DIS (1 << 30)
374# define RADEON_ROP3_S 0x00cc0000
375# define RADEON_ROP3_P 0x00f00000
376#define RADEON_DP_WRITE_MASK 0x16cc
377#define RADEON_DST_PITCH_OFFSET 0x142c
378#define RADEON_DST_PITCH_OFFSET_C 0x1c80
379# define RADEON_DST_TILE_LINEAR (0 << 30)
380# define RADEON_DST_TILE_MACRO (1 << 30)
381# define RADEON_DST_TILE_MICRO (2 << 30)
382# define RADEON_DST_TILE_BOTH (3 << 30)
383
384#define RADEON_SCRATCH_REG0 0x15e0
385#define RADEON_SCRATCH_REG1 0x15e4
386#define RADEON_SCRATCH_REG2 0x15e8
387#define RADEON_SCRATCH_REG3 0x15ec
388#define RADEON_SCRATCH_REG4 0x15f0
389#define RADEON_SCRATCH_REG5 0x15f4
390#define RADEON_SCRATCH_UMSK 0x0770
391#define RADEON_SCRATCH_ADDR 0x0774
392
393#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
394
395#define GET_SCRATCH( x ) (dev_priv->writeback_works \
396 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
397 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
398
399
400#define RADEON_GEN_INT_CNTL 0x0040
401# define RADEON_CRTC_VBLANK_MASK (1 << 0)
402# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
403# define RADEON_SW_INT_ENABLE (1 << 25)
404
405#define RADEON_GEN_INT_STATUS 0x0044
406# define RADEON_CRTC_VBLANK_STAT (1 << 0)
407# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
408# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
409# define RADEON_SW_INT_TEST (1 << 25)
410# define RADEON_SW_INT_TEST_ACK (1 << 25)
411# define RADEON_SW_INT_FIRE (1 << 26)
412
413#define RADEON_HOST_PATH_CNTL 0x0130
414# define RADEON_HDP_SOFT_RESET (1 << 26)
415# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
416# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
417
418#define RADEON_ISYNC_CNTL 0x1724
419# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
420# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
421# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
422# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
423# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
424# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
425
426#define RADEON_RBBM_GUICNTL 0x172c
427# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
428# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
429# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
430# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
431
432#define RADEON_MC_AGP_LOCATION 0x014c
433#define RADEON_MC_FB_LOCATION 0x0148
434#define RADEON_MCLK_CNTL 0x0012
435# define RADEON_FORCEON_MCLKA (1 << 16)
436# define RADEON_FORCEON_MCLKB (1 << 17)
437# define RADEON_FORCEON_YCLKA (1 << 18)
438# define RADEON_FORCEON_YCLKB (1 << 19)
439# define RADEON_FORCEON_MC (1 << 20)
440# define RADEON_FORCEON_AIC (1 << 21)
441
442#define RADEON_PP_BORDER_COLOR_0 0x1d40
443#define RADEON_PP_BORDER_COLOR_1 0x1d44
444#define RADEON_PP_BORDER_COLOR_2 0x1d48
445#define RADEON_PP_CNTL 0x1c38
446# define RADEON_SCISSOR_ENABLE (1 << 1)
447#define RADEON_PP_LUM_MATRIX 0x1d00
448#define RADEON_PP_MISC 0x1c14
449#define RADEON_PP_ROT_MATRIX_0 0x1d58
450#define RADEON_PP_TXFILTER_0 0x1c54
451#define RADEON_PP_TXOFFSET_0 0x1c5c
452#define RADEON_PP_TXFILTER_1 0x1c6c
453#define RADEON_PP_TXFILTER_2 0x1c84
454
455#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
456# define RADEON_RB2D_DC_FLUSH (3 << 0)
457# define RADEON_RB2D_DC_FREE (3 << 2)
458# define RADEON_RB2D_DC_FLUSH_ALL 0xf
459# define RADEON_RB2D_DC_BUSY (1 << 31)
460#define RADEON_RB3D_CNTL 0x1c3c
461# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
462# define RADEON_PLANE_MASK_ENABLE (1 << 1)
463# define RADEON_DITHER_ENABLE (1 << 2)
464# define RADEON_ROUND_ENABLE (1 << 3)
465# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
466# define RADEON_DITHER_INIT (1 << 5)
467# define RADEON_ROP_ENABLE (1 << 6)
468# define RADEON_STENCIL_ENABLE (1 << 7)
469# define RADEON_Z_ENABLE (1 << 8)
470# define RADEON_ZBLOCK16 (1 << 15)
471#define RADEON_RB3D_DEPTHOFFSET 0x1c24
472#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
473#define RADEON_RB3D_DEPTHPITCH 0x1c28
474#define RADEON_RB3D_PLANEMASK 0x1d84
475#define RADEON_RB3D_STENCILREFMASK 0x1d7c
476#define RADEON_RB3D_ZCACHE_MODE 0x3250
477#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
478# define RADEON_RB3D_ZC_FLUSH (1 << 0)
479# define RADEON_RB3D_ZC_FREE (1 << 2)
480# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
481# define RADEON_RB3D_ZC_BUSY (1 << 31)
482#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
483# define RADEON_Z_TEST_MASK (7 << 4)
484# define RADEON_Z_TEST_ALWAYS (7 << 4)
485# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
486# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
487# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
488# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
489# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
490# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
491# define RADEON_FORCE_Z_DIRTY (1 << 29)
492# define RADEON_Z_WRITE_ENABLE (1 << 30)
493# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
494#define RADEON_RBBM_SOFT_RESET 0x00f0
495# define RADEON_SOFT_RESET_CP (1 << 0)
496# define RADEON_SOFT_RESET_HI (1 << 1)
497# define RADEON_SOFT_RESET_SE (1 << 2)
498# define RADEON_SOFT_RESET_RE (1 << 3)
499# define RADEON_SOFT_RESET_PP (1 << 4)
500# define RADEON_SOFT_RESET_E2 (1 << 5)
501# define RADEON_SOFT_RESET_RB (1 << 6)
502# define RADEON_SOFT_RESET_HDP (1 << 7)
503#define RADEON_RBBM_STATUS 0x0e40
504# define RADEON_RBBM_FIFOCNT_MASK 0x007f
505# define RADEON_RBBM_ACTIVE (1 << 31)
506#define RADEON_RE_LINE_PATTERN 0x1cd0
507#define RADEON_RE_MISC 0x26c4
508#define RADEON_RE_TOP_LEFT 0x26c0
509#define RADEON_RE_WIDTH_HEIGHT 0x1c44
510#define RADEON_RE_STIPPLE_ADDR 0x1cc8
511#define RADEON_RE_STIPPLE_DATA 0x1ccc
512
513#define RADEON_SCISSOR_TL_0 0x1cd8
514#define RADEON_SCISSOR_BR_0 0x1cdc
515#define RADEON_SCISSOR_TL_1 0x1ce0
516#define RADEON_SCISSOR_BR_1 0x1ce4
517#define RADEON_SCISSOR_TL_2 0x1ce8
518#define RADEON_SCISSOR_BR_2 0x1cec
519#define RADEON_SE_COORD_FMT 0x1c50
520#define RADEON_SE_CNTL 0x1c4c
521# define RADEON_FFACE_CULL_CW (0 << 0)
522# define RADEON_BFACE_SOLID (3 << 1)
523# define RADEON_FFACE_SOLID (3 << 3)
524# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
525# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
526# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
527# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
528# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
529# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
530# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
531# define RADEON_FOG_SHADE_FLAT (1 << 14)
532# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
533# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
534# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
535# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
536# define RADEON_ROUND_MODE_TRUNC (0 << 28)
537# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
538#define RADEON_SE_CNTL_STATUS 0x2140
539#define RADEON_SE_LINE_WIDTH 0x1db8
540#define RADEON_SE_VPORT_XSCALE 0x1d98
541#define RADEON_SE_ZBIAS_FACTOR 0x1db0
542#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
543#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
544#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
545# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
546# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
547#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
548#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
549# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
550#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
551#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
552#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
553#define RADEON_SURFACE_CNTL 0x0b00
554# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
555# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
556# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
557# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
558# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
559# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
560# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
561# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
562# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
563#define RADEON_SURFACE0_INFO 0x0b0c
564# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
565# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
566# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
567# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
568# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
569# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
570#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
571#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
572# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
573#define RADEON_SURFACE1_INFO 0x0b1c
574#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
575#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
576#define RADEON_SURFACE2_INFO 0x0b2c
577#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
578#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
579#define RADEON_SURFACE3_INFO 0x0b3c
580#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
581#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
582#define RADEON_SURFACE4_INFO 0x0b4c
583#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
584#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
585#define RADEON_SURFACE5_INFO 0x0b5c
586#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
587#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
588#define RADEON_SURFACE6_INFO 0x0b6c
589#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
590#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
591#define RADEON_SURFACE7_INFO 0x0b7c
592#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
593#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
594#define RADEON_SW_SEMAPHORE 0x013c
595
596#define RADEON_WAIT_UNTIL 0x1720
597# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
598# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
599# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
600# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
601
602#define RADEON_RB3D_ZMASKOFFSET 0x3234
603#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
604# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
605# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
606
607
608/* CP registers */
609#define RADEON_CP_ME_RAM_ADDR 0x07d4
610#define RADEON_CP_ME_RAM_RADDR 0x07d8
611#define RADEON_CP_ME_RAM_DATAH 0x07dc
612#define RADEON_CP_ME_RAM_DATAL 0x07e0
613
614#define RADEON_CP_RB_BASE 0x0700
615#define RADEON_CP_RB_CNTL 0x0704
616# define RADEON_BUF_SWAP_32BIT (2 << 16)
617#define RADEON_CP_RB_RPTR_ADDR 0x070c
618#define RADEON_CP_RB_RPTR 0x0710
619#define RADEON_CP_RB_WPTR 0x0714
620
621#define RADEON_CP_RB_WPTR_DELAY 0x0718
622# define RADEON_PRE_WRITE_TIMER_SHIFT 0
623# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
624
625#define RADEON_CP_IB_BASE 0x0738
626
627#define RADEON_CP_CSQ_CNTL 0x0740
628# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
629# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
630# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
631# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
632# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
633# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
634# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
635
636#define RADEON_AIC_CNTL 0x01d0
637# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
638#define RADEON_AIC_STAT 0x01d4
639#define RADEON_AIC_PT_BASE 0x01d8
640#define RADEON_AIC_LO_ADDR 0x01dc
641#define RADEON_AIC_HI_ADDR 0x01e0
642#define RADEON_AIC_TLB_ADDR 0x01e4
643#define RADEON_AIC_TLB_DATA 0x01e8
644
645/* CP command packets */
646#define RADEON_CP_PACKET0 0x00000000
647# define RADEON_ONE_REG_WR (1 << 15)
648#define RADEON_CP_PACKET1 0x40000000
649#define RADEON_CP_PACKET2 0x80000000
650#define RADEON_CP_PACKET3 0xC0000000
651# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
652# define RADEON_WAIT_FOR_IDLE 0x00002600
653# define RADEON_3D_DRAW_VBUF 0x00002800
654# define RADEON_3D_DRAW_IMMD 0x00002900
655# define RADEON_3D_DRAW_INDX 0x00002A00
656# define RADEON_3D_LOAD_VBPNTR 0x00002F00
657# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
658# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
659# define RADEON_3D_CLEAR_ZMASK 0x00003200
660# define RADEON_3D_CLEAR_HIZ 0x00003700
661# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
662# define RADEON_CNTL_PAINT_MULTI 0x00009A00
663# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
664# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
665
666#define RADEON_CP_PACKET_MASK 0xC0000000
667#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
668#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
669#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
670#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
671
672#define RADEON_VTX_Z_PRESENT (1 << 31)
673#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
674
675#define RADEON_PRIM_TYPE_NONE (0 << 0)
676#define RADEON_PRIM_TYPE_POINT (1 << 0)
677#define RADEON_PRIM_TYPE_LINE (2 << 0)
678#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
679#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
680#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
681#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
682#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
683#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
684#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
685#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
686#define RADEON_PRIM_TYPE_MASK 0xf
687#define RADEON_PRIM_WALK_IND (1 << 4)
688#define RADEON_PRIM_WALK_LIST (2 << 4)
689#define RADEON_PRIM_WALK_RING (3 << 4)
690#define RADEON_COLOR_ORDER_BGRA (0 << 6)
691#define RADEON_COLOR_ORDER_RGBA (1 << 6)
692#define RADEON_MAOS_ENABLE (1 << 7)
693#define RADEON_VTX_FMT_R128_MODE (0 << 8)
694#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
695#define RADEON_NUM_VERTICES_SHIFT 16
696
697#define RADEON_COLOR_FORMAT_CI8 2
698#define RADEON_COLOR_FORMAT_ARGB1555 3
699#define RADEON_COLOR_FORMAT_RGB565 4
700#define RADEON_COLOR_FORMAT_ARGB8888 6
701#define RADEON_COLOR_FORMAT_RGB332 7
702#define RADEON_COLOR_FORMAT_RGB8 9
703#define RADEON_COLOR_FORMAT_ARGB4444 15
704
705#define RADEON_TXFORMAT_I8 0
706#define RADEON_TXFORMAT_AI88 1
707#define RADEON_TXFORMAT_RGB332 2
708#define RADEON_TXFORMAT_ARGB1555 3
709#define RADEON_TXFORMAT_RGB565 4
710#define RADEON_TXFORMAT_ARGB4444 5
711#define RADEON_TXFORMAT_ARGB8888 6
712#define RADEON_TXFORMAT_RGBA8888 7
713#define RADEON_TXFORMAT_Y8 8
714#define RADEON_TXFORMAT_VYUY422 10
715#define RADEON_TXFORMAT_YVYU422 11
716#define RADEON_TXFORMAT_DXT1 12
717#define RADEON_TXFORMAT_DXT23 14
718#define RADEON_TXFORMAT_DXT45 15
719
720#define R200_PP_TXCBLEND_0 0x2f00
721#define R200_PP_TXCBLEND_1 0x2f10
722#define R200_PP_TXCBLEND_2 0x2f20
723#define R200_PP_TXCBLEND_3 0x2f30
724#define R200_PP_TXCBLEND_4 0x2f40
725#define R200_PP_TXCBLEND_5 0x2f50
726#define R200_PP_TXCBLEND_6 0x2f60
727#define R200_PP_TXCBLEND_7 0x2f70
728#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
729#define R200_PP_TFACTOR_0 0x2ee0
730#define R200_SE_VTX_FMT_0 0x2088
731#define R200_SE_VAP_CNTL 0x2080
732#define R200_SE_TCL_MATRIX_SEL_0 0x2230
733#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
734#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
735#define R200_PP_TXFILTER_5 0x2ca0
736#define R200_PP_TXFILTER_4 0x2c80
737#define R200_PP_TXFILTER_3 0x2c60
738#define R200_PP_TXFILTER_2 0x2c40
739#define R200_PP_TXFILTER_1 0x2c20
740#define R200_PP_TXFILTER_0 0x2c00
741#define R200_PP_TXOFFSET_5 0x2d78
742#define R200_PP_TXOFFSET_4 0x2d60
743#define R200_PP_TXOFFSET_3 0x2d48
744#define R200_PP_TXOFFSET_2 0x2d30
745#define R200_PP_TXOFFSET_1 0x2d18
746#define R200_PP_TXOFFSET_0 0x2d00
747
748#define R200_PP_CUBIC_FACES_0 0x2c18
749#define R200_PP_CUBIC_FACES_1 0x2c38
750#define R200_PP_CUBIC_FACES_2 0x2c58
751#define R200_PP_CUBIC_FACES_3 0x2c78
752#define R200_PP_CUBIC_FACES_4 0x2c98
753#define R200_PP_CUBIC_FACES_5 0x2cb8
754#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
755#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
756#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
757#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
758#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
759#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
760#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
761#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
762#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
763#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
764#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
765#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
766#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
767#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
768#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
769#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
770#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
771#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
772#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
773#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
774#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
775#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
776#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
777#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
778#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
779#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
780#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
781#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
782#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
783#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
784
785#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
786#define R200_SE_VTE_CNTL 0x20b0
787#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
788#define R200_PP_TAM_DEBUG3 0x2d9c
789#define R200_PP_CNTL_X 0x2cc4
790#define R200_SE_VAP_CNTL_STATUS 0x2140
791#define R200_RE_SCISSOR_TL_0 0x1cd8
792#define R200_RE_SCISSOR_TL_1 0x1ce0
793#define R200_RE_SCISSOR_TL_2 0x1ce8
794#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
795#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
796#define R200_SE_VTX_STATE_CNTL 0x2180
797#define R200_RE_POINTSIZE 0x2648
798#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
799
800#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
801#define RADEON_PP_TEX_SIZE_1 0x1d0c
802#define RADEON_PP_TEX_SIZE_2 0x1d14
803
804#define RADEON_PP_CUBIC_FACES_0 0x1d24
805#define RADEON_PP_CUBIC_FACES_1 0x1d28
806#define RADEON_PP_CUBIC_FACES_2 0x1d2c
807#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
808#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
809#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
810
811#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
812#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
813#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
814#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
815#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
816#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
817#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
818#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
819#define R200_3D_DRAW_IMMD_2 0xC0003500
820#define R200_SE_VTX_FMT_1 0x208c
821#define R200_RE_CNTL 0x1c50
822
823#define R200_RB3D_BLENDCOLOR 0x3218
824
825#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
826
827#define R200_PP_TRI_PERF 0x2cf8
828
829/* Constants */
830#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
831
832#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
833#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
834#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
835#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
836#define RADEON_LAST_DISPATCH 1
837
838#define RADEON_MAX_VB_AGE 0x7fffffff
839#define RADEON_MAX_VB_VERTS (0xffff)
840
841#define RADEON_RING_HIGH_MARK 128
842
843#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
844#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
845#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
846#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
847
848#define RADEON_WRITE_PLL( addr, val ) \
849do { \
850 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
851 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
852 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
853} while (0)
854
855#define CP_PACKET0( reg, n ) \
856 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
857#define CP_PACKET0_TABLE( reg, n ) \
858 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
859#define CP_PACKET1( reg0, reg1 ) \
860 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
861#define CP_PACKET2() \
862 (RADEON_CP_PACKET2)
863#define CP_PACKET3( pkt, n ) \
864 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
865
866
867/* ================================================================
868 * Engine control helper macros
869 */
870
871#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
872 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
873 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
874 RADEON_WAIT_HOST_IDLECLEAN) ); \
875} while (0)
876
877#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
878 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
879 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
880 RADEON_WAIT_HOST_IDLECLEAN) ); \
881} while (0)
882
883#define RADEON_WAIT_UNTIL_IDLE() do { \
884 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
885 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
886 RADEON_WAIT_3D_IDLECLEAN | \
887 RADEON_WAIT_HOST_IDLECLEAN) ); \
888} while (0)
889
890#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
891 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
892 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
893} while (0)
894
895#define RADEON_FLUSH_CACHE() do { \
896 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
897 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
898} while (0)
899
900#define RADEON_PURGE_CACHE() do { \
901 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
902 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
903} while (0)
904
905#define RADEON_FLUSH_ZCACHE() do { \
906 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
907 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
908} while (0)
909
910#define RADEON_PURGE_ZCACHE() do { \
911 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
912 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
913} while (0)
914
915
916/* ================================================================
917 * Misc helper macros
918 */
919
920/* Perfbox functionality only.
921 */
922#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
923do { \
924 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
925 u32 head = GET_RING_HEAD( dev_priv ); \
926 if (head == dev_priv->ring.tail) \
927 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
928 } \
929} while (0)
930
931#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
932do { \
933 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
934 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
935 int __ret = radeon_do_cp_idle( dev_priv ); \
936 if ( __ret ) return __ret; \
937 sarea_priv->last_dispatch = 0; \
938 radeon_freelist_reset( dev ); \
939 } \
940} while (0)
941
942#define RADEON_DISPATCH_AGE( age ) do { \
943 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
944 OUT_RING( age ); \
945} while (0)
946
947#define RADEON_FRAME_AGE( age ) do { \
948 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
949 OUT_RING( age ); \
950} while (0)
951
952#define RADEON_CLEAR_AGE( age ) do { \
953 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
954 OUT_RING( age ); \
955} while (0)
956
957
958/* ================================================================
959 * Ring control
960 */
961
962#define RADEON_VERBOSE 0
963
964#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
965
966#define BEGIN_RING( n ) do { \
967 if ( RADEON_VERBOSE ) { \
968 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
969 n, __FUNCTION__ ); \
970 } \
971 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
972 COMMIT_RING(); \
973 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
974 } \
975 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
976 ring = dev_priv->ring.start; \
977 write = dev_priv->ring.tail; \
978 mask = dev_priv->ring.tail_mask; \
979} while (0)
980
981#define ADVANCE_RING() do { \
982 if ( RADEON_VERBOSE ) { \
983 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
984 write, dev_priv->ring.tail ); \
985 } \
986 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
987 DRM_ERROR( \
988 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
989 ((dev_priv->ring.tail + _nr) & mask), \
990 write, __LINE__); \
991 } else \
992 dev_priv->ring.tail = write; \
993} while (0)
994
995#define COMMIT_RING() do { \
996 /* Flush writes to ring */ \
997 DRM_MEMORYBARRIER(); \
998 GET_RING_HEAD( dev_priv ); \
999 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1000 /* read from PCI bus to ensure correct posting */ \
1001 RADEON_READ( RADEON_CP_RB_RPTR ); \
1002} while (0)
1003
1004#define OUT_RING( x ) do { \
1005 if ( RADEON_VERBOSE ) { \
1006 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1007 (unsigned int)(x), write ); \
1008 } \
1009 ring[write++] = (x); \
1010 write &= mask; \
1011} while (0)
1012
1013#define OUT_RING_REG( reg, val ) do { \
1014 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1015 OUT_RING( val ); \
1016} while (0)
1017
1018
1019#define OUT_RING_TABLE( tab, sz ) do { \
1020 int _size = (sz); \
1021 int *_tab = (int *)(tab); \
1022 \
1023 if (write + _size > mask) { \
1024 int _i = (mask+1) - write; \
1025 _size -= _i; \
1026 while (_i > 0 ) { \
1027 *(int *)(ring + write) = *_tab++; \
1028 write++; \
1029 _i--; \
1030 } \
1031 write = 0; \
1032 _tab += _i; \
1033 } \
1034 \
1035 while (_size > 0) { \
1036 *(ring + write) = *_tab++; \
1037 write++; \
1038 _size--; \
1039 } \
1040 write &= mask; \
1041} while (0)
1042
1043
1044#endif /* __RADEON_DRV_H__ */