Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / drivers / video / nvidia / nv_type.h
blob: e4a5b1da71c433fff3d0c79de9f8cb28b21bd469 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1#ifndef __NV_TYPE_H__
2#define __NV_TYPE_H__
3
4#include <linux/fb.h>
5#include <linux/types.h>
6#include <linux/i2c.h>
7#include <linux/i2c-id.h>
8#include <linux/i2c-algo-bit.h>
9
10#define NV_ARCH_04 0x04
11#define NV_ARCH_10 0x10
12#define NV_ARCH_20 0x20
13#define NV_ARCH_30 0x30
14#define NV_ARCH_40 0x40
15
16#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
17#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
18#define SetBF(mask,value) ((value) << (0?mask))
19#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
20#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
21#define SetBit(n) (1<<(n))
22#define Set8Bits(value) ((value)&0xff)
23
24#define V_DBLSCAN 1
25
26typedef struct {
27 int bitsPerPixel;
28 int depth;
29 int displayWidth;
30 int weight;
31} NVFBLayout;
32
33#define NUM_SEQ_REGS 0x05
34#define NUM_CRT_REGS 0x41
35#define NUM_GRC_REGS 0x09
36#define NUM_ATC_REGS 0x15
37
38struct nvidia_par;
39
40struct nvidia_i2c_chan {
41 struct nvidia_par *par;
42 unsigned long ddc_base;
43 struct i2c_adapter adapter;
44 struct i2c_algo_bit_data algo;
45};
46
47typedef struct _riva_hw_state {
48 u8 attr[NUM_ATC_REGS];
49 u8 crtc[NUM_CRT_REGS];
50 u8 gra[NUM_GRC_REGS];
51 u8 seq[NUM_SEQ_REGS];
52 u8 misc_output;
53 u32 bpp;
54 u32 width;
55 u32 height;
56 u32 interlace;
57 u32 repaint0;
58 u32 repaint1;
59 u32 screen;
60 u32 scale;
61 u32 dither;
62 u32 extra;
63 u32 fifo;
64 u32 pixel;
65 u32 horiz;
66 u32 arbitration0;
67 u32 arbitration1;
68 u32 pll;
69 u32 pllB;
70 u32 vpll;
71 u32 vpll2;
72 u32 vpllB;
73 u32 vpll2B;
74 u32 pllsel;
75 u32 general;
76 u32 crtcOwner;
77 u32 head;
78 u32 head2;
79 u32 config;
80 u32 cursorConfig;
81 u32 cursor0;
82 u32 cursor1;
83 u32 cursor2;
84 u32 timingH;
85 u32 timingV;
86 u32 displayV;
87 u32 crtcSync;
88} RIVA_HW_STATE;
89
90struct riva_regs {
91 RIVA_HW_STATE ext;
92};
93
94struct nvidia_par {
95 RIVA_HW_STATE SavedReg;
96 RIVA_HW_STATE ModeReg;
97 RIVA_HW_STATE *CurrentState;
98 u32 pseudo_palette[16];
99 struct pci_dev *pci_dev;
100 u32 Architecture;
101 u32 CursorStart;
102 int Chipset;
103 int bus;
104 unsigned long FbAddress;
105 u8 __iomem *FbStart;
106 u32 FbMapSize;
107 u32 FbUsableSize;
108 u32 ScratchBufferSize;
109 u32 ScratchBufferStart;
110 int FpScale;
111 u32 MinVClockFreqKHz;
112 u32 MaxVClockFreqKHz;
113 u32 CrystalFreqKHz;
114 u32 RamAmountKBytes;
115 u32 IOBase;
116 NVFBLayout CurrentLayout;
117 int cursor_reset;
118 int lockup;
119 int videoKey;
120 int FlatPanel;
121 int FPDither;
122 int Television;
123 int CRTCnumber;
124 int alphaCursor;
125 int twoHeads;
126 int twoStagePLL;
127 int fpScaler;
128 int fpWidth;
129 int fpHeight;
130 int PanelTweak;
131 int paneltweak;
132 u32 crtcSync_read;
133 u32 fpSyncs;
134 u32 dmaPut;
135 u32 dmaCurrent;
136 u32 dmaFree;
137 u32 dmaMax;
138 u32 __iomem *dmaBase;
139 u32 currentRop;
140 int WaitVSyncPossible;
141 int BlendingPossible;
142 u32 paletteEnabled;
143 u32 forceCRTC;
144 u8 DDCBase;
145#ifdef CONFIG_MTRR
146 struct {
147 int vram;
148 int vram_valid;
149 } mtrr;
150#endif
151 struct nvidia_i2c_chan chan[3];
152
153 volatile u32 __iomem *REGS;
154 volatile u32 __iomem *PCRTC0;
155 volatile u32 __iomem *PCRTC;
156 volatile u32 __iomem *PRAMDAC0;
157 volatile u32 __iomem *PFB;
158 volatile u32 __iomem *PFIFO;
159 volatile u32 __iomem *PGRAPH;
160 volatile u32 __iomem *PEXTDEV;
161 volatile u32 __iomem *PTIMER;
162 volatile u32 __iomem *PMC;
163 volatile u32 __iomem *PRAMIN;
164 volatile u32 __iomem *FIFO;
165 volatile u32 __iomem *CURSOR;
166 volatile u8 __iomem *PCIO0;
167 volatile u8 __iomem *PCIO;
168 volatile u8 __iomem *PVIO;
169 volatile u8 __iomem *PDIO0;
170 volatile u8 __iomem *PDIO;
171 volatile u32 __iomem *PRAMDAC;
172};
173
174#endif /* __NV_TYPE_H__ */