| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * SA-1101.h |
| 3 | * |
| 4 | * Copyright (c) Peter Danielsson 1999 |
| 5 | * |
| 6 | * Definition of constants related to the sa1101 |
| 7 | * support chip for the sa1100 |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | |
| 12 | /* Be sure that virtual mapping is defined right */ |
| 13 | #ifndef __ASM_ARCH_HARDWARE_H |
| 14 | #error You must include hardware.h not SA-1101.h |
| 15 | #endif |
| 16 | |
| 17 | #ifndef SA1101_BASE |
| 18 | #error You must define SA-1101 physical base address |
| 19 | #endif |
| 20 | |
| 21 | #ifndef LANGUAGE |
| 22 | # ifdef __ASSEMBLY__ |
| 23 | # define LANGUAGE Assembly |
| 24 | # else |
| 25 | # define LANGUAGE C |
| 26 | # endif |
| 27 | #endif |
| 28 | |
| 29 | /* |
| 30 | * We have mapped the sa1101 depending on the value of SA1101_BASE. |
| 31 | * It then appears from 0xf4000000. |
| 32 | */ |
| 33 | |
| 34 | #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000) |
| 35 | #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE) |
| 36 | |
| 37 | #ifndef SA1101_p2v |
| 38 | #define SA1101_p2v(PhAdd) (PhAdd) |
| 39 | #endif |
| 40 | |
| 41 | #include <asm/arch/bitfield.h> |
| 42 | |
| 43 | #define C 0 |
| 44 | #define Assembly 1 |
| 45 | |
| 46 | |
| 47 | /* |
| 48 | * Memory map |
| 49 | */ |
| 50 | |
| 51 | #define __SHMEM_CONTROL0 0x00000000 |
| 52 | #define __SYSTEM_CONTROL1 0x00000400 |
| 53 | #define __ARBITER 0x00020000 |
| 54 | #define __SYSTEM_CONTROL2 0x00040000 |
| 55 | #define __SYSTEM_CONTROL3 0x00060000 |
| 56 | #define __PARALLEL_PORT 0x00080000 |
| 57 | #define __VIDMEM_CONTROL 0x00100000 |
| 58 | #define __UPDATE_FIFO 0x00120000 |
| 59 | #define __SHMEM_CONTROL1 0x00140000 |
| 60 | #define __INTERRUPT_CONTROL 0x00160000 |
| 61 | #define __USB_CONTROL 0x00180000 |
| 62 | #define __TRACK_INTERFACE 0x001a0000 |
| 63 | #define __MOUSE_INTERFACE 0x001b0000 |
| 64 | #define __KEYPAD_INTERFACE 0x001c0000 |
| 65 | #define __PCMCIA_INTERFACE 0x001e0000 |
| 66 | #define __VGA_CONTROL 0x00200000 |
| 67 | #define __GPIO_INTERFACE 0x00300000 |
| 68 | |
| 69 | /* |
| 70 | * Macro that calculates real address for registers in the SA-1101 |
| 71 | */ |
| 72 | |
| 73 | #define _SA1101( x ) ((x) + SA1101_BASE) |
| 74 | |
| 75 | /* |
| 76 | * Interface and shared memory controller registers |
| 77 | * |
| 78 | * Registers |
| 79 | * SKCR SA-1101 control register (read/write) |
| 80 | * SMCR Shared Memory Controller Register |
| 81 | * SNPR Snoop Register |
| 82 | */ |
| 83 | |
| 84 | #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ |
| 85 | #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ |
| 86 | #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ |
| 87 | |
| 88 | #if LANGUAGE == C |
| 89 | #define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) |
| 90 | #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) |
| 91 | #define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) |
| 92 | |
| 93 | #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ |
| 94 | #define SKCR_BCLKEn 0x0002 /* Enables BCLK */ |
| 95 | #define SKCR_Sleep 0x0004 /* Sleep Mode */ |
| 96 | #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ |
| 97 | #define SKCR_VCOON 0x0010 /* VCO bias */ |
| 98 | #define SKCR_ScanTestEn 0x0020 /* Enables scan test */ |
| 99 | #define SKCR_ClockTestEn 0x0040 /* Enables clock test */ |
| 100 | |
| 101 | #define SMCR_DCAC Fld(2,0) /* Number of column address bits */ |
| 102 | #define SMCR_DRAC Fld(2,2) /* Number of row address bits */ |
| 103 | #define SMCR_ArbiterBias 0x0008 /* favor video or USB */ |
| 104 | #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ |
| 105 | |
| 106 | #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ |
| 107 | (( (x) - 8 ) << FShft (SMCR_DCAC)) |
| 108 | #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ |
| 109 | (( (x) - 9 ) << FShft (SMCR_DRAC) |
| 110 | |
| 111 | #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ |
| 112 | #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ |
| 113 | #define SNPR_WholeBank (1 << 23) /* Whole bank bit */ |
| 114 | #define SNPR_BankSelect Fld(2,27) /* Bank select */ |
| 115 | #define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ |
| 116 | |
| 117 | #define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ |
| 118 | ( (x) << FShft (SNPR_VFBsize)) |
| 119 | #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ |
| 120 | (( (x) + 1 ) << FShft (SNPR_BankSelect )) |
| 121 | |
| 122 | #endif /* LANGUAGE == C */ |
| 123 | |
| 124 | /* |
| 125 | * Video Memory Controller |
| 126 | * |
| 127 | * Registers |
| 128 | * VMCCR Configuration register |
| 129 | * VMCAR VMC address register |
| 130 | * VMCDR VMC data register |
| 131 | * |
| 132 | */ |
| 133 | |
| 134 | #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ |
| 135 | #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ |
| 136 | #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ |
| 137 | |
| 138 | #if LANGUAGE == C |
| 139 | #define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) |
| 140 | #define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) |
| 141 | #define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) |
| 142 | |
| 143 | #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ |
| 144 | #define VMCCR_Config 0x0001 /* DRAM size */ |
| 145 | #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ |
| 146 | #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ |
| 147 | #define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ |
| 148 | #define VMCCR_RefTest (1<<10) /* refresh test */ |
| 149 | #define VMCCR_RefLow Fld(6,11) /* refresh low counter */ |
| 150 | #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ |
| 151 | #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ |
| 152 | #define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ |
| 153 | |
| 154 | #endif LANGUAGE == C |
| 155 | |
| 156 | |
| 157 | /* Update FIFO |
| 158 | * |
| 159 | * Registers |
| 160 | * UFCR Update FIFO Control Register |
| 161 | * UFSR Update FIFO Status Register |
| 162 | * UFLVLR update FIFO level register |
| 163 | * UFDR update FIFO data register |
| 164 | */ |
| 165 | |
| 166 | #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ |
| 167 | #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ |
| 168 | #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ |
| 169 | #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ |
| 170 | |
| 171 | #if LANGUAGE == C |
| 172 | |
| 173 | #define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) |
| 174 | #define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) |
| 175 | #define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) |
| 176 | #define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) |
| 177 | |
| 178 | |
| 179 | #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ |
| 180 | |
| 181 | #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ |
| 182 | |
| 183 | #endif /* LANGUAGE == C */ |
| 184 | |
| 185 | /* System Controller |
| 186 | * |
| 187 | * Registers |
| 188 | * SKPCR Power Control Register |
| 189 | * SKCDR Clock Divider Register |
| 190 | * DACDR1 DAC1 Data register |
| 191 | * DACDR2 DAC2 Data register |
| 192 | */ |
| 193 | |
| 194 | #define _SKPCR _SA1101(0x00000400) |
| 195 | #define _SKCDR _SA1101(0x00040000) |
| 196 | #define _DACDR1 _SA1101(0x00060000) |
| 197 | #define _DACDR2 _SA1101(0x00060400) |
| 198 | |
| 199 | #if LANGUAGE == C |
| 200 | #define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) |
| 201 | #define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) |
| 202 | #define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) |
| 203 | #define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) |
| 204 | |
| 205 | #define SKPCR_UCLKEn 0x01 /* USB Enable */ |
| 206 | #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ |
| 207 | #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ |
| 208 | #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ |
| 209 | #define SKPCR_PICLKEn 0x10 /* parallel port Enable */ |
| 210 | #define SKPCR_DCLKEn 0x20 /* DACs Enable */ |
| 211 | #define SKPCR_nKPADEn 0x40 /* Multiplexer */ |
| 212 | |
| 213 | #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ |
| 214 | #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ |
| 215 | #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ |
| 216 | #define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ |
| 217 | #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ |
| 218 | #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ |
| 219 | #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ |
| 220 | #define SKDCR_ChargePump (1<<25) /* Charge pump control */ |
| 221 | #define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ |
| 222 | #define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ |
| 223 | #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ |
| 224 | |
| 225 | #define DACDR_DACCount Fld(8,0) /* Count value */ |
| 226 | #define DACDR1_DACCount DACDR_DACCount |
| 227 | #define DACDR2_DACCount DACDR_DACCount |
| 228 | |
| 229 | #endif /* LANGUAGE == C */ |
| 230 | |
| 231 | /* |
| 232 | * Parallel Port Interface |
| 233 | * |
| 234 | * Registers |
| 235 | * IEEE_Config IEEE mode selection and programmable attributes |
| 236 | * IEEE_Control Controls the states of IEEE port control outputs |
| 237 | * IEEE_Data Forward transfer data register |
| 238 | * IEEE_Addr Forward transfer address register |
| 239 | * IEEE_Status Port IO signal status register |
| 240 | * IEEE_IntStatus Port interrupts status register |
| 241 | * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels |
| 242 | * IEEE_InitTime Forward timeout counter initial value |
| 243 | * IEEE_TimerStatus Forward timeout counter current value |
| 244 | * IEEE_FifoReset Reset forward transfer FIFO |
| 245 | * IEEE_ReloadValue Counter reload value |
| 246 | * IEEE_TestControl Control testmode |
| 247 | * IEEE_TestDataIn Test data register |
| 248 | * IEEE_TestDataInEn Enable test data |
| 249 | * IEEE_TestCtrlIn Test control signals |
| 250 | * IEEE_TestCtrlInEn Enable test control signals |
| 251 | * IEEE_TestDataStat Current data bus value |
| 252 | * |
| 253 | */ |
| 254 | |
| 255 | /* |
| 256 | * The control registers are defined as offsets from a base address |
| 257 | */ |
| 258 | |
| 259 | #define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) |
| 260 | |
| 261 | #define _IEEE_Config _IEEE( 0x0000 ) |
| 262 | #define _IEEE_Control _IEEE( 0x0400 ) |
| 263 | #define _IEEE_Data _IEEE( 0x4000 ) |
| 264 | #define _IEEE_Addr _IEEE( 0x0800 ) |
| 265 | #define _IEEE_Status _IEEE( 0x0c00 ) |
| 266 | #define _IEEE_IntStatus _IEEE( 0x1000 ) |
| 267 | #define _IEEE_FifoLevels _IEEE( 0x1400 ) |
| 268 | #define _IEEE_InitTime _IEEE( 0x1800 ) |
| 269 | #define _IEEE_TimerStatus _IEEE( 0x1c00 ) |
| 270 | #define _IEEE_FifoReset _IEEE( 0x2000 ) |
| 271 | #define _IEEE_ReloadValue _IEEE( 0x3c00 ) |
| 272 | #define _IEEE_TestControl _IEEE( 0x2400 ) |
| 273 | #define _IEEE_TestDataIn _IEEE( 0x2800 ) |
| 274 | #define _IEEE_TestDataInEn _IEEE( 0x2c00 ) |
| 275 | #define _IEEE_TestCtrlIn _IEEE( 0x3000 ) |
| 276 | #define _IEEE_TestCtrlInEn _IEEE( 0x3400 ) |
| 277 | #define _IEEE_TestDataStat _IEEE( 0x3800 ) |
| 278 | |
| 279 | |
| 280 | #if LANGUAGE == C |
| 281 | #define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config))) |
| 282 | #define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control))) |
| 283 | #define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data))) |
| 284 | #define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr))) |
| 285 | #define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status))) |
| 286 | #define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus))) |
| 287 | #define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels))) |
| 288 | #define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime))) |
| 289 | #define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus))) |
| 290 | #define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset))) |
| 291 | #define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue))) |
| 292 | #define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl))) |
| 293 | #define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn))) |
| 294 | #define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn))) |
| 295 | #define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn))) |
| 296 | #define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn))) |
| 297 | #define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat))) |
| 298 | |
| 299 | |
| 300 | #define IEEE_Config_M Fld(3,0) /* Mode select */ |
| 301 | #define IEEE_Config_D 0x04 /* FIFO access enable */ |
| 302 | #define IEEE_Config_B 0x08 /* 9-bit word enable */ |
| 303 | #define IEEE_Config_T 0x10 /* Data transfer enable */ |
| 304 | #define IEEE_Config_A 0x20 /* Data transfer direction */ |
| 305 | #define IEEE_Config_E 0x40 /* Timer enable */ |
| 306 | #define IEEE_Control_A 0x08 /* AutoFd output */ |
| 307 | #define IEEE_Control_E 0x04 /* Selectin output */ |
| 308 | #define IEEE_Control_T 0x02 /* Strobe output */ |
| 309 | #define IEEE_Control_I 0x01 /* Port init output */ |
| 310 | #define IEEE_Data_C (1<<31) /* Byte count */ |
| 311 | #define IEEE_Data_Db Fld(9,16) /* Data byte 2 */ |
| 312 | #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */ |
| 313 | #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */ |
| 314 | #define IEEE_Status_A 0x0100 /* nAutoFd port output status */ |
| 315 | #define IEEE_Status_E 0x0080 /* nSelectIn port output status */ |
| 316 | #define IEEE_Status_T 0x0040 /* nStrobe port output status */ |
| 317 | #define IEEE_Status_I 0x0020 /* nInit port output status */ |
| 318 | #define IEEE_Status_B 0x0010 /* Busy port inout status */ |
| 319 | #define IEEE_Status_S 0x0008 /* Select port input status */ |
| 320 | #define IEEE_Status_K 0x0004 /* nAck port input status */ |
| 321 | #define IEEE_Status_F 0x0002 /* nFault port input status */ |
| 322 | #define IEEE_Status_R 0x0001 /* pError port input status */ |
| 323 | |
| 324 | #define IEEE_IntStatus_IntReqDat 0x0100 |
| 325 | #define IEEE_IntStatus_IntReqEmp 0x0080 |
| 326 | #define IEEE_IntStatus_IntReqInt 0x0040 |
| 327 | #define IEEE_IntStatus_IntReqRav 0x0020 |
| 328 | #define IEEE_IntStatus_IntReqTim 0x0010 |
| 329 | #define IEEE_IntStatus_RevAddrComp 0x0008 |
| 330 | #define IEEE_IntStatus_RevDataComp 0x0004 |
| 331 | #define IEEE_IntStatus_FwdAddrComp 0x0002 |
| 332 | #define IEEE_IntStatus_FwdDataComp 0x0001 |
| 333 | #define IEEE_FifoLevels_RevFifoLevel 2 |
| 334 | #define IEEE_FifoLevels_FwdFifoLevel 1 |
| 335 | #define IEEE_InitTime_TimValInit Fld(22,0) |
| 336 | #define IEEE_TimerStatus_TimValStat Fld(22,0) |
| 337 | #define IEEE_ReloadValue_Reload Fld(4,0) |
| 338 | |
| 339 | #define IEEE_TestControl_RegClk 0x04 |
| 340 | #define IEEE_TestControl_ClockSelect Fld(2,1) |
| 341 | #define IEEE_TestControl_TimerTestModeEn 0x01 |
| 342 | #define IEEE_TestCtrlIn_PError 0x10 |
| 343 | #define IEEE_TestCtrlIn_nFault 0x08 |
| 344 | #define IEEE_TestCtrlIn_nAck 0x04 |
| 345 | #define IEEE_TestCtrlIn_PSel 0x02 |
| 346 | #define IEEE_TestCtrlIn_Busy 0x01 |
| 347 | |
| 348 | #endif /* LANGUAGE == C */ |
| 349 | |
| 350 | /* |
| 351 | * VGA Controller |
| 352 | * |
| 353 | * Registers |
| 354 | * VideoControl Video Control Register |
| 355 | * VgaTiming0 VGA Timing Register 0 |
| 356 | * VgaTiming1 VGA Timing Register 1 |
| 357 | * VgaTiming2 VGA Timing Register 2 |
| 358 | * VgaTiming3 VGA Timing Register 3 |
| 359 | * VgaBorder VGA Border Color Register |
| 360 | * VgaDBAR VGADMA Base Address Register |
| 361 | * VgaDCAR VGADMA Channel Current Address Register |
| 362 | * VgaStatus VGA Status Register |
| 363 | * VgaInterruptMask VGA Interrupt Mask Register |
| 364 | * VgaPalette VGA Palette Registers |
| 365 | * DacControl DAC Control Register |
| 366 | * VgaTest VGA Controller Test Register |
| 367 | */ |
| 368 | |
| 369 | #define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL ) |
| 370 | |
| 371 | #define _VideoControl _VGA( 0x0000 ) |
| 372 | #define _VgaTiming0 _VGA( 0x0400 ) |
| 373 | #define _VgaTiming1 _VGA( 0x0800 ) |
| 374 | #define _VgaTiming2 _VGA( 0x0c00 ) |
| 375 | #define _VgaTiming3 _VGA( 0x1000 ) |
| 376 | #define _VgaBorder _VGA( 0x1400 ) |
| 377 | #define _VgaDBAR _VGA( 0x1800 ) |
| 378 | #define _VgaDCAR _VGA( 0x1c00 ) |
| 379 | #define _VgaStatus _VGA( 0x2000 ) |
| 380 | #define _VgaInterruptMask _VGA( 0x2400 ) |
| 381 | #define _VgaPalette _VGA( 0x40000 ) |
| 382 | #define _DacControl _VGA( 0x3000 ) |
| 383 | #define _VgaTest _VGA( 0x2c00 ) |
| 384 | |
| 385 | #if (LANGUAGE == C) |
| 386 | #define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl))) |
| 387 | #define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0))) |
| 388 | #define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1))) |
| 389 | #define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2))) |
| 390 | #define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3))) |
| 391 | #define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder))) |
| 392 | #define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR))) |
| 393 | #define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR))) |
| 394 | #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) |
| 395 | #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) |
| 396 | #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) |
| 397 | #define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)) |
| 398 | #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) |
| 399 | |
| 400 | #define VideoControl_VgaEn 0x00000000 |
| 401 | #define VideoControl_BGR 0x00000001 |
| 402 | #define VideoControl_VCompVal Fld(2,2) |
| 403 | #define VideoControl_VgaReq Fld(4,4) |
| 404 | #define VideoControl_VBurstL Fld(4,8) |
| 405 | #define VideoControl_VMode (1<<12) |
| 406 | #define VideoControl_PalRead (1<<13) |
| 407 | |
| 408 | #define VgaTiming0_PPL Fld(6,2) |
| 409 | #define VgaTiming0_HSW Fld(8,8) |
| 410 | #define VgaTiming0_HFP Fld(8,16) |
| 411 | #define VgaTiming0_HBP Fld(8,24) |
| 412 | |
| 413 | #define VgaTiming1_LPS Fld(10,0) |
| 414 | #define VgaTiming1_VSW Fld(6,10) |
| 415 | #define VgaTiming1_VFP Fld(8,16) |
| 416 | #define VgaTiming1_VBP Fld(8,24) |
| 417 | |
| 418 | #define VgaTiming2_IVS 0x01 |
| 419 | #define VgaTiming2_IHS 0x02 |
| 420 | #define VgaTiming2_CVS 0x04 |
| 421 | #define VgaTiming2_CHS 0x08 |
| 422 | |
| 423 | #define VgaTiming3_HBS Fld(8,0) |
| 424 | #define VgaTiming3_HBE Fld(8,8) |
| 425 | #define VgaTiming3_VBS Fld(8,16) |
| 426 | #define VgaTiming3_VBE Fld(8,24) |
| 427 | |
| 428 | #define VgaBorder_BCOL Fld(24,0) |
| 429 | |
| 430 | #define VgaStatus_VFUF 0x01 |
| 431 | #define VgaStatus_VNext 0x02 |
| 432 | #define VgaStatus_VComp 0x04 |
| 433 | |
| 434 | #define VgaInterruptMask_VFUFMask 0x00 |
| 435 | #define VgaInterruptMask_VNextMask 0x01 |
| 436 | #define VgaInterruptMask_VCompMask 0x02 |
| 437 | |
| 438 | #define VgaPalette_R Fld(8,0) |
| 439 | #define VgaPalette_G Fld(8,8) |
| 440 | #define VgaPalette_B Fld(8,16) |
| 441 | |
| 442 | #define DacControl_DACON 0x0001 |
| 443 | #define DacControl_COMPON 0x0002 |
| 444 | #define DacControl_PEDON 0x0004 |
| 445 | #define DacControl_RTrim Fld(5,4) |
| 446 | #define DacControl_GTrim Fld(5,9) |
| 447 | #define DacControl_BTrim Fld(5,14) |
| 448 | |
| 449 | #define VgaTest_TDAC 0x00 |
| 450 | #define VgaTest_Datatest Fld(4,1) |
| 451 | #define VgaTest_DACTESTDAC 0x10 |
| 452 | #define VgaTest_DACTESTOUT Fld(3,5) |
| 453 | |
| 454 | #endif /* LANGUAGE == C */ |
| 455 | |
| 456 | /* |
| 457 | * USB Host Interface Controller |
| 458 | * |
| 459 | * Registers |
| 460 | * Revision |
| 461 | * Control |
| 462 | * CommandStatus |
| 463 | * InterruptStatus |
| 464 | * InterruptEnable |
| 465 | * HCCA |
| 466 | * PeriodCurrentED |
| 467 | * ControlHeadED |
| 468 | * BulkHeadED |
| 469 | * BulkCurrentED |
| 470 | * DoneHead |
| 471 | * FmInterval |
| 472 | * FmRemaining |
| 473 | * FmNumber |
| 474 | * PeriodicStart |
| 475 | * LSThreshold |
| 476 | * RhDescriptorA |
| 477 | * RhDescriptorB |
| 478 | * RhStatus |
| 479 | * RhPortStatus |
| 480 | * USBStatus |
| 481 | * USBReset |
| 482 | * USTAR |
| 483 | * USWER |
| 484 | * USRFR |
| 485 | * USNFR |
| 486 | * USTCSR |
| 487 | * USSR |
| 488 | * |
| 489 | */ |
| 490 | |
| 491 | #define _USB( x ) _SA1101( ( x ) + __USB_CONTROL ) |
| 492 | |
| 493 | |
| 494 | #define _Revision _USB( 0x0000 ) |
| 495 | #define _Control _USB( 0x0888 ) |
| 496 | #define _CommandStatus _USB( 0x0c00 ) |
| 497 | #define _InterruptStatus _USB( 0x1000 ) |
| 498 | #define _InterruptEnable _USB( 0x1400 ) |
| 499 | #define _HCCA _USB( 0x1800 ) |
| 500 | #define _PeriodCurrentED _USB( 0x1c00 ) |
| 501 | #define _ControlHeadED _USB( 0x2000 ) |
| 502 | #define _BulkHeadED _USB( 0x2800 ) |
| 503 | #define _BulkCurrentED _USB( 0x2c00 ) |
| 504 | #define _DoneHead _USB( 0x3000 ) |
| 505 | #define _FmInterval _USB( 0x3400 ) |
| 506 | #define _FmRemaining _USB( 0x3800 ) |
| 507 | #define _FmNumber _USB( 0x3c00 ) |
| 508 | #define _PeriodicStart _USB( 0x4000 ) |
| 509 | #define _LSThreshold _USB( 0x4400 ) |
| 510 | #define _RhDescriptorA _USB( 0x4800 ) |
| 511 | #define _RhDescriptorB _USB( 0x4c00 ) |
| 512 | #define _RhStatus _USB( 0x5000 ) |
| 513 | #define _RhPortStatus _USB( 0x5400 ) |
| 514 | #define _USBStatus _USB( 0x11800 ) |
| 515 | #define _USBReset _USB( 0x11c00 ) |
| 516 | |
| 517 | #define _USTAR _USB( 0x10400 ) |
| 518 | #define _USWER _USB( 0x10800 ) |
| 519 | #define _USRFR _USB( 0x10c00 ) |
| 520 | #define _USNFR _USB( 0x11000 ) |
| 521 | #define _USTCSR _USB( 0x11400 ) |
| 522 | #define _USSR _USB( 0x11800 ) |
| 523 | |
| 524 | |
| 525 | #if (LANGUAGE == C) |
| 526 | |
| 527 | #define Revision (*((volatile Word *) SA1101_p2v (_Revision))) |
| 528 | #define Control (*((volatile Word *) SA1101_p2v (_Control))) |
| 529 | #define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus))) |
| 530 | #define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus))) |
| 531 | #define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable))) |
| 532 | #define HCCA (*((volatile Word *) SA1101_p2v (_HCCA))) |
| 533 | #define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED))) |
| 534 | #define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED))) |
| 535 | #define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED))) |
| 536 | #define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED))) |
| 537 | #define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead))) |
| 538 | #define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval))) |
| 539 | #define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining))) |
| 540 | #define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber))) |
| 541 | #define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart))) |
| 542 | #define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold))) |
| 543 | #define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA))) |
| 544 | #define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB))) |
| 545 | #define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus))) |
| 546 | #define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus))) |
| 547 | #define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus))) |
| 548 | #define USBReset (*((volatile Word *) SA1101_p2v (_USBReset))) |
| 549 | #define USTAR (*((volatile Word *) SA1101_p2v (_USTAR))) |
| 550 | #define USWER (*((volatile Word *) SA1101_p2v (_USWER))) |
| 551 | #define USRFR (*((volatile Word *) SA1101_p2v (_USRFR))) |
| 552 | #define USNFR (*((volatile Word *) SA1101_p2v (_USNFR))) |
| 553 | #define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR))) |
| 554 | #define USSR (*((volatile Word *) SA1101_p2v (_USSR))) |
| 555 | |
| 556 | |
| 557 | #define USBStatus_IrqHciRmtWkp (1<<7) |
| 558 | #define USBStatus_IrqHciBuffAcc (1<<8) |
| 559 | #define USBStatus_nIrqHciM (1<<9) |
| 560 | #define USBStatus_nHciMFClr (1<<10) |
| 561 | |
| 562 | #define USBReset_ForceIfReset 0x01 |
| 563 | #define USBReset_ForceHcReset 0x02 |
| 564 | #define USBReset_ClkGenReset 0x04 |
| 565 | |
| 566 | #define USTCR_RdBstCntrl Fld(3,0) |
| 567 | #define USTCR_ByteEnable Fld(4,3) |
| 568 | #define USTCR_WriteEn (1<<7) |
| 569 | #define USTCR_FifoCir (1<<8) |
| 570 | #define USTCR_TestXferSel (1<<9) |
| 571 | #define USTCR_FifoCirAtEnd (1<<10) |
| 572 | #define USTCR_nSimScaleDownClk (1<<11) |
| 573 | |
| 574 | #define USSR_nAppMDEmpty 0x01 |
| 575 | #define USSR_nAppMDFirst 0x02 |
| 576 | #define USSR_nAppMDLast 0x04 |
| 577 | #define USSR_nAppMDFull 0x08 |
| 578 | #define USSR_nAppMAFull 0x10 |
| 579 | #define USSR_XferReq 0x20 |
| 580 | #define USSR_XferEnd 0x40 |
| 581 | |
| 582 | #endif /* LANGUAGE == C */ |
| 583 | |
| 584 | |
| 585 | /* |
| 586 | * Interrupt Controller |
| 587 | * |
| 588 | * Registers |
| 589 | * INTTEST0 Test register 0 |
| 590 | * INTTEST1 Test register 1 |
| 591 | * INTENABLE0 Interrupt Enable register 0 |
| 592 | * INTENABLE1 Interrupt Enable register 1 |
| 593 | * INTPOL0 Interrupt Polarity selection 0 |
| 594 | * INTPOL1 Interrupt Polarity selection 1 |
| 595 | * INTTSTSEL Interrupt source selection |
| 596 | * INTSTATCLR0 Interrupt Status 0 |
| 597 | * INTSTATCLR1 Interrupt Status 1 |
| 598 | * INTSET0 Interrupt Set 0 |
| 599 | * INTSET1 Interrupt Set 1 |
| 600 | */ |
| 601 | |
| 602 | #define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL) |
| 603 | |
| 604 | #define _INTTEST0 _INT( 0x1000 ) |
| 605 | #define _INTTEST1 _INT( 0x1400 ) |
| 606 | #define _INTENABLE0 _INT( 0x2000 ) |
| 607 | #define _INTENABLE1 _INT( 0x2400 ) |
| 608 | #define _INTPOL0 _INT( 0x3000 ) |
| 609 | #define _INTPOL1 _INT( 0x3400 ) |
| 610 | #define _INTTSTSEL _INT( 0x5000 ) |
| 611 | #define _INTSTATCLR0 _INT( 0x6000 ) |
| 612 | #define _INTSTATCLR1 _INT( 0x6400 ) |
| 613 | #define _INTSET0 _INT( 0x7000 ) |
| 614 | #define _INTSET1 _INT( 0x7400 ) |
| 615 | |
| 616 | #if ( LANGUAGE == C ) |
| 617 | #define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0))) |
| 618 | #define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1))) |
| 619 | #define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0))) |
| 620 | #define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1))) |
| 621 | #define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0))) |
| 622 | #define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1))) |
| 623 | #define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL))) |
| 624 | #define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0))) |
| 625 | #define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1))) |
| 626 | #define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0))) |
| 627 | #define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1))) |
| 628 | |
| 629 | #endif /* LANGUAGE == C */ |
| 630 | |
| 631 | /* |
| 632 | * PS/2 Trackpad and Mouse Interfaces |
| 633 | * |
| 634 | * Registers (prefix kbd applies to trackpad interface, mse to mouse) |
| 635 | * KBDCR Control Register |
| 636 | * KBDSTAT Status Register |
| 637 | * KBDDATA Transmit/Receive Data register |
| 638 | * KBDCLKDIV Clock Division Register |
| 639 | * KBDPRECNT Clock Precount Register |
| 640 | * KBDTEST1 Test register 1 |
| 641 | * KBDTEST2 Test register 2 |
| 642 | * KBDTEST3 Test register 3 |
| 643 | * KBDTEST4 Test register 4 |
| 644 | * MSECR |
| 645 | * MSESTAT |
| 646 | * MSEDATA |
| 647 | * MSECLKDIV |
| 648 | * MSEPRECNT |
| 649 | * MSETEST1 |
| 650 | * MSETEST2 |
| 651 | * MSETEST3 |
| 652 | * MSETEST4 |
| 653 | * |
| 654 | */ |
| 655 | |
| 656 | #define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE ) |
| 657 | #define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE ) |
| 658 | |
| 659 | #define _KBDCR _KBD( 0x0000 ) |
| 660 | #define _KBDSTAT _KBD( 0x0400 ) |
| 661 | #define _KBDDATA _KBD( 0x0800 ) |
| 662 | #define _KBDCLKDIV _KBD( 0x0c00 ) |
| 663 | #define _KBDPRECNT _KBD( 0x1000 ) |
| 664 | #define _KBDTEST1 _KBD( 0x2000 ) |
| 665 | #define _KBDTEST2 _KBD( 0x2400 ) |
| 666 | #define _KBDTEST3 _KBD( 0x2800 ) |
| 667 | #define _KBDTEST4 _KBD( 0x2c00 ) |
| 668 | #define _MSECR _MSE( 0x0000 ) |
| 669 | #define _MSESTAT _MSE( 0x0400 ) |
| 670 | #define _MSEDATA _MSE( 0x0800 ) |
| 671 | #define _MSECLKDIV _MSE( 0x0c00 ) |
| 672 | #define _MSEPRECNT _MSE( 0x1000 ) |
| 673 | #define _MSETEST1 _MSE( 0x2000 ) |
| 674 | #define _MSETEST2 _MSE( 0x2400 ) |
| 675 | #define _MSETEST3 _MSE( 0x2800 ) |
| 676 | #define _MSETEST4 _MSE( 0x2c00 ) |
| 677 | |
| 678 | #if ( LANGUAGE == C ) |
| 679 | |
| 680 | #define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR))) |
| 681 | #define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT))) |
| 682 | #define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA))) |
| 683 | #define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV))) |
| 684 | #define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT))) |
| 685 | #define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1))) |
| 686 | #define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2))) |
| 687 | #define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3))) |
| 688 | #define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4))) |
| 689 | #define MSECR (*((volatile Word *) SA1101_p2v (_MSECR))) |
| 690 | #define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT))) |
| 691 | #define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA))) |
| 692 | #define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV))) |
| 693 | #define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT))) |
| 694 | #define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1))) |
| 695 | #define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2))) |
| 696 | #define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3))) |
| 697 | #define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4))) |
| 698 | |
| 699 | |
| 700 | #define KBDCR_ENA 0x08 |
| 701 | #define KBDCR_FKD 0x02 |
| 702 | #define KBDCR_FKC 0x01 |
| 703 | |
| 704 | #define KBDSTAT_TXE 0x80 |
| 705 | #define KBDSTAT_TXB 0x40 |
| 706 | #define KBDSTAT_RXF 0x20 |
| 707 | #define KBDSTAT_RXB 0x10 |
| 708 | #define KBDSTAT_ENA 0x08 |
| 709 | #define KBDSTAT_RXP 0x04 |
| 710 | #define KBDSTAT_KBD 0x02 |
| 711 | #define KBDSTAT_KBC 0x01 |
| 712 | |
| 713 | #define KBDCLKDIV_DivVal Fld(4,0) |
| 714 | |
| 715 | #define MSECR_ENA 0x08 |
| 716 | #define MSECR_FKD 0x02 |
| 717 | #define MSECR_FKC 0x01 |
| 718 | |
| 719 | #define MSESTAT_TXE 0x80 |
| 720 | #define MSESTAT_TXB 0x40 |
| 721 | #define MSESTAT_RXF 0x20 |
| 722 | #define MSESTAT_RXB 0x10 |
| 723 | #define MSESTAT_ENA 0x08 |
| 724 | #define MSESTAT_RXP 0x04 |
| 725 | #define MSESTAT_MSD 0x02 |
| 726 | #define MSESTAT_MSC 0x01 |
| 727 | |
| 728 | #define MSECLKDIV_DivVal Fld(4,0) |
| 729 | |
| 730 | #define KBDTEST1_CD 0x80 |
| 731 | #define KBDTEST1_RC1 0x40 |
| 732 | #define KBDTEST1_MC 0x20 |
| 733 | #define KBDTEST1_C Fld(2,3) |
| 734 | #define KBDTEST1_T2 0x40 |
| 735 | #define KBDTEST1_T1 0x20 |
| 736 | #define KBDTEST1_T0 0x10 |
| 737 | #define KBDTEST2_TICBnRES 0x08 |
| 738 | #define KBDTEST2_RKC 0x04 |
| 739 | #define KBDTEST2_RKD 0x02 |
| 740 | #define KBDTEST2_SEL 0x01 |
| 741 | #define KBDTEST3_ms_16 0x80 |
| 742 | #define KBDTEST3_us_64 0x40 |
| 743 | #define KBDTEST3_us_16 0x20 |
| 744 | #define KBDTEST3_DIV8 0x10 |
| 745 | #define KBDTEST3_DIn 0x08 |
| 746 | #define KBDTEST3_CIn 0x04 |
| 747 | #define KBDTEST3_KD 0x02 |
| 748 | #define KBDTEST3_KC 0x01 |
| 749 | #define KBDTEST4_BC12 0x80 |
| 750 | #define KBDTEST4_BC11 0x40 |
| 751 | #define KBDTEST4_TRES 0x20 |
| 752 | #define KBDTEST4_CLKOE 0x10 |
| 753 | #define KBDTEST4_CRES 0x08 |
| 754 | #define KBDTEST4_RXB 0x04 |
| 755 | #define KBDTEST4_TXB 0x02 |
| 756 | #define KBDTEST4_SRX 0x01 |
| 757 | |
| 758 | #define MSETEST1_CD 0x80 |
| 759 | #define MSETEST1_RC1 0x40 |
| 760 | #define MSETEST1_MC 0x20 |
| 761 | #define MSETEST1_C Fld(2,3) |
| 762 | #define MSETEST1_T2 0x40 |
| 763 | #define MSETEST1_T1 0x20 |
| 764 | #define MSETEST1_T0 0x10 |
| 765 | #define MSETEST2_TICBnRES 0x08 |
| 766 | #define MSETEST2_RKC 0x04 |
| 767 | #define MSETEST2_RKD 0x02 |
| 768 | #define MSETEST2_SEL 0x01 |
| 769 | #define MSETEST3_ms_16 0x80 |
| 770 | #define MSETEST3_us_64 0x40 |
| 771 | #define MSETEST3_us_16 0x20 |
| 772 | #define MSETEST3_DIV8 0x10 |
| 773 | #define MSETEST3_DIn 0x08 |
| 774 | #define MSETEST3_CIn 0x04 |
| 775 | #define MSETEST3_KD 0x02 |
| 776 | #define MSETEST3_KC 0x01 |
| 777 | #define MSETEST4_BC12 0x80 |
| 778 | #define MSETEST4_BC11 0x40 |
| 779 | #define MSETEST4_TRES 0x20 |
| 780 | #define MSETEST4_CLKOE 0x10 |
| 781 | #define MSETEST4_CRES 0x08 |
| 782 | #define MSETEST4_RXB 0x04 |
| 783 | #define MSETEST4_TXB 0x02 |
| 784 | #define MSETEST4_SRX 0x01 |
| 785 | |
| 786 | #endif /* LANGUAGE == C */ |
| 787 | |
| 788 | |
| 789 | /* |
| 790 | * General-Purpose I/O Interface |
| 791 | * |
| 792 | * Registers |
| 793 | * PADWR Port A Data Write Register |
| 794 | * PBDWR Port B Data Write Register |
| 795 | * PADRR Port A Data Read Register |
| 796 | * PBDRR Port B Data Read Register |
| 797 | * PADDR Port A Data Direction Register |
| 798 | * PBDDR Port B Data Direction Register |
| 799 | * PASSR Port A Sleep State Register |
| 800 | * PBSSR Port B Sleep State Register |
| 801 | * |
| 802 | */ |
| 803 | |
| 804 | #define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE ) |
| 805 | |
| 806 | #define _PADWR _PIO( 0x0000 ) |
| 807 | #define _PBDWR _PIO( 0x0400 ) |
| 808 | #define _PADRR _PIO( 0x0000 ) |
| 809 | #define _PBDRR _PIO( 0x0400 ) |
| 810 | #define _PADDR _PIO( 0x0800 ) |
| 811 | #define _PBDDR _PIO( 0x0c00 ) |
| 812 | #define _PASSR _PIO( 0x1000 ) |
| 813 | #define _PBSSR _PIO( 0x1400 ) |
| 814 | |
| 815 | |
| 816 | #if ( LANGUAGE == C ) |
| 817 | |
| 818 | |
| 819 | #define PADWR (*((volatile Word *) SA1101_p2v (_PADWR))) |
| 820 | #define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR))) |
| 821 | #define PADRR (*((volatile Word *) SA1101_p2v (_PADRR))) |
| 822 | #define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR))) |
| 823 | #define PADDR (*((volatile Word *) SA1101_p2v (_PADDR))) |
| 824 | #define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR))) |
| 825 | #define PASSR (*((volatile Word *) SA1101_p2v (_PASSR))) |
| 826 | #define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR))) |
| 827 | |
| 828 | #endif |
| 829 | |
| 830 | |
| 831 | |
| 832 | /* |
| 833 | * Keypad Interface |
| 834 | * |
| 835 | * Registers |
| 836 | * PXDWR |
| 837 | * PXDRR |
| 838 | * PYDWR |
| 839 | * PYDRR |
| 840 | * |
| 841 | */ |
| 842 | |
| 843 | #define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) |
| 844 | |
| 845 | #define _PXDWR _KEYPAD( 0x0000 ) |
| 846 | #define _PXDRR _KEYPAD( 0x0000 ) |
| 847 | #define _PYDWR _KEYPAD( 0x0400 ) |
| 848 | #define _PYDRR _KEYPAD( 0x0400 ) |
| 849 | |
| 850 | #if ( LANGUAGE == C ) |
| 851 | |
| 852 | |
| 853 | #define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR))) |
| 854 | #define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR))) |
| 855 | #define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR))) |
| 856 | #define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR))) |
| 857 | |
| 858 | #endif |
| 859 | |
| 860 | |
| 861 | |
| 862 | /* |
| 863 | * PCMCIA Interface |
| 864 | * |
| 865 | * Registers |
| 866 | * PCSR Status Register |
| 867 | * PCCR Control Register |
| 868 | * PCSSR Sleep State Register |
| 869 | * |
| 870 | */ |
| 871 | |
| 872 | #define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE ) |
| 873 | |
| 874 | #define _PCSR _CARD( 0x0000 ) |
| 875 | #define _PCCR _CARD( 0x0400 ) |
| 876 | #define _PCSSR _CARD( 0x0800 ) |
| 877 | |
| 878 | #if ( LANGUAGE == C ) |
| 879 | #define PCSR (*((volatile Word *) SA1101_p2v (_PCSR))) |
| 880 | #define PCCR (*((volatile Word *) SA1101_p2v (_PCCR))) |
| 881 | #define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR))) |
| 882 | |
| 883 | #define PCSR_S0_ready 0x0001 |
| 884 | #define PCSR_S1_ready 0x0002 |
| 885 | #define PCSR_S0_detected 0x0004 |
| 886 | #define PCSR_S1_detected 0x0008 |
| 887 | #define PCSR_S0_VS1 0x0010 |
| 888 | #define PCSR_S0_VS2 0x0020 |
| 889 | #define PCSR_S1_VS1 0x0040 |
| 890 | #define PCSR_S1_VS2 0x0080 |
| 891 | #define PCSR_S0_WP 0x0100 |
| 892 | #define PCSR_S1_WP 0x0200 |
| 893 | #define PCSR_S0_BVD1_nSTSCHG 0x0400 |
| 894 | #define PCSR_S0_BVD2_nSPKR 0x0800 |
| 895 | #define PCSR_S1_BVD1_nSTSCHG 0x1000 |
| 896 | #define PCSR_S1_BVD2_nSPKR 0x2000 |
| 897 | |
| 898 | #define PCCR_S0_VPP0 0x0001 |
| 899 | #define PCCR_S0_VPP1 0x0002 |
| 900 | #define PCCR_S0_VCC0 0x0004 |
| 901 | #define PCCR_S0_VCC1 0x0008 |
| 902 | #define PCCR_S1_VPP0 0x0010 |
| 903 | #define PCCR_S1_VPP1 0x0020 |
| 904 | #define PCCR_S1_VCC0 0x0040 |
| 905 | #define PCCR_S1_VCC1 0x0080 |
| 906 | #define PCCR_S0_reset 0x0100 |
| 907 | #define PCCR_S1_reset 0x0200 |
| 908 | #define PCCR_S0_float 0x0400 |
| 909 | #define PCCR_S1_float 0x0800 |
| 910 | |
| 911 | #define PCSSR_S0_VCC0 0x0001 |
| 912 | #define PCSSR_S0_VCC1 0x0002 |
| 913 | #define PCSSR_S0_VPP0 0x0004 |
| 914 | #define PCSSR_S0_VPP1 0x0008 |
| 915 | #define PCSSR_S0_control 0x0010 |
| 916 | #define PCSSR_S1_VCC0 0x0020 |
| 917 | #define PCSSR_S1_VCC1 0x0040 |
| 918 | #define PCSSR_S1_VPP0 0x0080 |
| 919 | #define PCSSR_S1_VPP1 0x0100 |
| 920 | #define PCSSR_S1_control 0x0200 |
| 921 | |
| 922 | #endif |
| 923 | |
| 924 | #undef C |
| 925 | #undef Assembly |