Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2000-2001 Toshiba Corporation |
| 7 | */ |
| 8 | #ifndef __ASM_TX4927_TX4927_PCI_H |
| 9 | #define __ASM_TX4927_TX4927_PCI_H |
| 10 | |
| 11 | #define TX4927_CCFG_TOE 0x00004000 |
| 12 | |
| 13 | #define TX4927_PCIMEM 0x08000000 |
| 14 | #define TX4927_PCIMEM_SIZE 0x08000000 |
| 15 | #define TX4927_PCIIO 0x16000000 |
| 16 | #define TX4927_PCIIO_SIZE 0x01000000 |
| 17 | |
| 18 | #define TX4927_SDRAMC_REG 0xff1f8000 |
| 19 | #define TX4927_EBUSC_REG 0xff1f9000 |
| 20 | #define TX4927_PCIC_REG 0xff1fd000 |
| 21 | #define TX4927_CCFG_REG 0xff1fe000 |
| 22 | #define TX4927_IRC_REG 0xff1ff600 |
| 23 | #define TX4927_CE3 0x17f00000 /* 1M */ |
| 24 | #define TX4927_PCIRESET_ADDR 0xbc00f006 |
| 25 | #define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) |
| 26 | |
| 27 | #define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n)) |
| 28 | #define tx4927_imstat_ptr(n) \ |
| 29 | ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n)) |
| 30 | |
| 31 | /* bits for ISTAT3/IMASK3/IMSTAT3 */ |
| 32 | #define TX4927_INT3B_PCID 0 |
| 33 | #define TX4927_INT3B_PCIC 1 |
| 34 | #define TX4927_INT3B_PCIB 2 |
| 35 | #define TX4927_INT3B_PCIA 3 |
| 36 | #define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) |
| 37 | #define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) |
| 38 | #define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) |
| 39 | #define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) |
| 40 | |
| 41 | /* bits for PCI_CLK (S6) */ |
| 42 | #define TX4927_PCI_CLK_HOST 0x80 |
| 43 | #define TX4927_PCI_CLK_MASK (0x0f << 3) |
| 44 | #define TX4927_PCI_CLK_33 (0x01 << 3) |
| 45 | #define TX4927_PCI_CLK_25 (0x04 << 3) |
| 46 | #define TX4927_PCI_CLK_66 (0x09 << 3) |
| 47 | #define TX4927_PCI_CLK_50 (0x0c << 3) |
| 48 | #define TX4927_PCI_CLK_ACK 0x04 |
| 49 | #define TX4927_PCI_CLK_ACE 0x02 |
| 50 | #define TX4927_PCI_CLK_ENDIAN 0x01 |
| 51 | #define TX4927_NR_IRQ_LOCAL (8+16) |
| 52 | #define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ |
| 53 | |
| 54 | #define TX4927_IR_PCIC 16 |
| 55 | #define TX4927_IR_PCIERR 22 |
| 56 | #define TX4927_IR_PCIPMA 23 |
| 57 | #define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) |
| 58 | #define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) |
| 59 | #define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) |
| 60 | #define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) |
| 61 | #define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) |
| 62 | #define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) |
| 63 | #define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) |
| 64 | |
| 65 | #ifdef _LANGUAGE_ASSEMBLY |
| 66 | #define _CONST64(c) c |
| 67 | #else |
| 68 | #define _CONST64(c) c##ull |
| 69 | |
| 70 | #include <asm/byteorder.h> |
| 71 | |
| 72 | #define tx4927_pcireset_ptr \ |
| 73 | ((volatile unsigned char *)TX4927_PCIRESET_ADDR) |
| 74 | #define tx4927_pci_clk_ptr \ |
| 75 | ((volatile unsigned char *)TX4927_PCI_CLK_ADDR) |
| 76 | |
| 77 | struct tx4927_sdramc_reg { |
| 78 | volatile unsigned long long cr[4]; |
| 79 | volatile unsigned long long unused0[4]; |
| 80 | volatile unsigned long long tr; |
| 81 | volatile unsigned long long unused1[2]; |
| 82 | volatile unsigned long long cmd; |
| 83 | }; |
| 84 | |
| 85 | struct tx4927_ebusc_reg { |
| 86 | volatile unsigned long long cr[8]; |
| 87 | }; |
| 88 | |
| 89 | struct tx4927_ccfg_reg { |
| 90 | volatile unsigned long long ccfg; |
| 91 | volatile unsigned long long crir; |
| 92 | volatile unsigned long long pcfg; |
| 93 | volatile unsigned long long tear; |
| 94 | volatile unsigned long long clkctr; |
| 95 | volatile unsigned long long unused0; |
| 96 | volatile unsigned long long garbc; |
| 97 | volatile unsigned long long unused1; |
| 98 | volatile unsigned long long unused2; |
| 99 | volatile unsigned long long ramp; |
| 100 | }; |
| 101 | |
| 102 | struct tx4927_irc_reg { |
| 103 | volatile unsigned long cer; |
| 104 | volatile unsigned long cr[2]; |
| 105 | volatile unsigned long unused0; |
| 106 | volatile unsigned long ilr[8]; |
| 107 | volatile unsigned long unused1[4]; |
| 108 | volatile unsigned long imr; |
| 109 | volatile unsigned long unused2[7]; |
| 110 | volatile unsigned long scr; |
| 111 | volatile unsigned long unused3[7]; |
| 112 | volatile unsigned long ssr; |
| 113 | volatile unsigned long unused4[7]; |
| 114 | volatile unsigned long csr; |
| 115 | }; |
| 116 | |
| 117 | struct tx4927_pcic_reg { |
| 118 | volatile unsigned long pciid; |
| 119 | volatile unsigned long pcistatus; |
| 120 | volatile unsigned long pciccrev; |
| 121 | volatile unsigned long pcicfg1; |
| 122 | volatile unsigned long p2gm0plbase; /* +10 */ |
| 123 | volatile unsigned long p2gm0pubase; |
| 124 | volatile unsigned long p2gm1plbase; |
| 125 | volatile unsigned long p2gm1pubase; |
| 126 | volatile unsigned long p2gm2pbase; /* +20 */ |
| 127 | volatile unsigned long p2giopbase; |
| 128 | volatile unsigned long unused0; |
| 129 | volatile unsigned long pcisid; |
| 130 | volatile unsigned long unused1; /* +30 */ |
| 131 | volatile unsigned long pcicapptr; |
| 132 | volatile unsigned long unused2; |
| 133 | volatile unsigned long pcicfg2; |
| 134 | volatile unsigned long g2ptocnt; /* +40 */ |
| 135 | volatile unsigned long unused3[15]; |
| 136 | volatile unsigned long g2pstatus; /* +80 */ |
| 137 | volatile unsigned long g2pmask; |
| 138 | volatile unsigned long pcisstatus; |
| 139 | volatile unsigned long pcimask; |
| 140 | volatile unsigned long p2gcfg; /* +90 */ |
| 141 | volatile unsigned long p2gstatus; |
| 142 | volatile unsigned long p2gmask; |
| 143 | volatile unsigned long p2gccmd; |
| 144 | volatile unsigned long unused4[24]; /* +a0 */ |
| 145 | volatile unsigned long pbareqport; /* +100 */ |
| 146 | volatile unsigned long pbacfg; |
| 147 | volatile unsigned long pbastatus; |
| 148 | volatile unsigned long pbamask; |
| 149 | volatile unsigned long pbabm; /* +110 */ |
| 150 | volatile unsigned long pbacreq; |
| 151 | volatile unsigned long pbacgnt; |
| 152 | volatile unsigned long pbacstate; |
| 153 | volatile unsigned long long g2pmgbase[3]; /* +120 */ |
| 154 | volatile unsigned long long g2piogbase; |
| 155 | volatile unsigned long g2pmmask[3]; /* +140 */ |
| 156 | volatile unsigned long g2piomask; |
| 157 | volatile unsigned long long g2pmpbase[3]; /* +150 */ |
| 158 | volatile unsigned long long g2piopbase; |
| 159 | volatile unsigned long pciccfg; /* +170 */ |
| 160 | volatile unsigned long pcicstatus; |
| 161 | volatile unsigned long pcicmask; |
| 162 | volatile unsigned long unused5; |
| 163 | volatile unsigned long long p2gmgbase[3]; /* +180 */ |
| 164 | volatile unsigned long long p2giogbase; |
| 165 | volatile unsigned long g2pcfgadrs; /* +1a0 */ |
| 166 | volatile unsigned long g2pcfgdata; |
| 167 | volatile unsigned long unused6[8]; |
| 168 | volatile unsigned long g2pintack; |
| 169 | volatile unsigned long g2pspc; |
| 170 | volatile unsigned long unused7[12]; /* +1d0 */ |
| 171 | volatile unsigned long long pdmca; /* +200 */ |
| 172 | volatile unsigned long long pdmga; |
| 173 | volatile unsigned long long pdmpa; |
| 174 | volatile unsigned long long pdmcut; |
| 175 | volatile unsigned long long pdmcnt; /* +220 */ |
| 176 | volatile unsigned long long pdmsts; |
| 177 | volatile unsigned long long unused8[2]; |
| 178 | volatile unsigned long long pdmdb[4]; /* +240 */ |
| 179 | volatile unsigned long long pdmtdh; /* +260 */ |
| 180 | volatile unsigned long long pdmdms; |
| 181 | }; |
| 182 | |
| 183 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 184 | |
| 185 | /* IRCSR : Int. Current Status */ |
| 186 | #define TX4927_IRCSR_IF 0x00010000 |
| 187 | #define TX4927_IRCSR_ILV_MASK 0x00000700 |
| 188 | #define TX4927_IRCSR_IVL_MASK 0x0000001f |
| 189 | |
| 190 | /* |
| 191 | * PCIC |
| 192 | */ |
| 193 | |
| 194 | /* bits for G2PSTATUS/G2PMASK */ |
| 195 | #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 |
| 196 | #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 |
| 197 | #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 |
| 198 | |
| 199 | /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ |
| 200 | #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 |
| 201 | |
| 202 | /* bits for PBACFG */ |
| 203 | #define TX4927_PCIC_PBACFG_RPBA 0x00000004 |
| 204 | #define TX4927_PCIC_PBACFG_PBAEN 0x00000002 |
| 205 | #define TX4927_PCIC_PBACFG_BMCEN 0x00000001 |
| 206 | |
| 207 | /* bits for G2PMnGBASE */ |
| 208 | #define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) |
| 209 | #define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) |
| 210 | |
| 211 | /* bits for G2PIOGBASE */ |
| 212 | #define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) |
| 213 | #define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) |
| 214 | |
| 215 | /* bits for PCICSTATUS/PCICMASK */ |
| 216 | #define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc |
| 217 | |
| 218 | /* bits for PCICCFG */ |
| 219 | #define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 |
| 220 | #define TX4927_PCIC_PCICCFG_HRST 0x00000800 |
| 221 | #define TX4927_PCIC_PCICCFG_SRST 0x00000400 |
| 222 | #define TX4927_PCIC_PCICCFG_IRBER 0x00000200 |
| 223 | #define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 |
| 224 | #define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 |
| 225 | #define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 |
| 226 | #define TX4927_PCIC_PCICCFG_IISE 0x00000020 |
| 227 | #define TX4927_PCIC_PCICCFG_ATR 0x00000010 |
| 228 | #define TX4927_PCIC_PCICCFG_ICAE 0x00000008 |
| 229 | |
| 230 | /* bits for P2GMnGBASE */ |
| 231 | #define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) |
| 232 | #define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) |
| 233 | #define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) |
| 234 | |
| 235 | /* bits for P2GIOGBASE */ |
| 236 | #define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) |
| 237 | #define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) |
| 238 | #define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) |
| 239 | |
| 240 | #define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) |
| 241 | #define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) |
| 242 | |
| 243 | /* |
| 244 | * CCFG |
| 245 | */ |
| 246 | /* CCFG : Chip Configuration */ |
| 247 | #define TX4927_CCFG_PCI66 0x00800000 |
| 248 | #define TX4927_CCFG_PCIMIDE 0x00400000 |
| 249 | #define TX4927_CCFG_PCIXARB 0x00002000 |
| 250 | #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 |
| 251 | #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 |
| 252 | #define TX4927_CCFG_PCIDIVMODE_3 0x00000800 |
| 253 | #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 |
| 254 | #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 |
| 255 | |
| 256 | /* PCFG : Pin Configuration */ |
| 257 | #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 |
| 258 | #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) |
| 259 | |
| 260 | /* CLKCTR : Clock Control */ |
| 261 | #define TX4927_CLKCTR_PCICKD 0x00400000 |
| 262 | #define TX4927_CLKCTR_PCIRST 0x00000040 |
| 263 | |
| 264 | |
| 265 | #ifndef _LANGUAGE_ASSEMBLY |
| 266 | |
| 267 | #define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) |
| 268 | #define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) |
| 269 | #define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) |
| 270 | #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) |
| 271 | #define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG) |
| 272 | |
| 273 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 274 | |
| 275 | #endif /* __ASM_TX4927_TX4927_PCI_H */ |