Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 Power domains framework |
| 3 | * |
Benoit Cousson | 7932870 | 2010-05-20 12:31:11 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 6 | * |
| 7 | * Abhijit Pagare (abhijitpagare@ti.com) |
| 8 | * Benoit Cousson (b-cousson@ti.com) |
Benoit Cousson | 7932870 | 2010-05-20 12:31:11 -0600 | [diff] [blame] | 9 | * Paul Walmsley (paul@pwsan.com) |
Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 10 | * |
| 11 | * This file is automatically generated from the OMAP hardware databases. |
| 12 | * We respectfully ask that any modifications to this file be coordinated |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 14 | * authors above to ensure that the autogeneration scripts are kept |
| 15 | * up-to-date with the file contents. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. |
| 20 | */ |
| 21 | |
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H |
| 24 | |
| 25 | #include <plat/powerdomain.h> |
| 26 | |
| 27 | #include "prcm-common.h" |
| 28 | #include "cm.h" |
| 29 | #include "cm-regbits-44xx.h" |
| 30 | #include "prm.h" |
| 31 | #include "prm-regbits-44xx.h" |
| 32 | |
| 33 | #if defined(CONFIG_ARCH_OMAP4) |
| 34 | |
| 35 | /* core_44xx_pwrdm: CORE power domain */ |
| 36 | static struct powerdomain core_44xx_pwrdm = { |
| 37 | .name = "core_pwrdm", |
| 38 | .prcm_offs = OMAP4430_PRM_CORE_MOD, |
| 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 40 | .pwrsts = PWRSTS_RET_ON, |
| 41 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 42 | .banks = 5, |
| 43 | .pwrsts_mem_ret = { |
| 44 | [0] = PWRDM_POWER_OFF, /* core_nret_bank */ |
| 45 | [1] = PWRSTS_OFF_RET, /* core_ocmram */ |
| 46 | [2] = PWRDM_POWER_RET, /* core_other_bank */ |
| 47 | [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ |
| 48 | [4] = PWRSTS_OFF_RET, /* ducati_unicache */ |
| 49 | }, |
| 50 | .pwrsts_mem_on = { |
| 51 | [0] = PWRDM_POWER_ON, /* core_nret_bank */ |
| 52 | [1] = PWRSTS_OFF_RET, /* core_ocmram */ |
| 53 | [2] = PWRDM_POWER_ON, /* core_other_bank */ |
| 54 | [3] = PWRDM_POWER_ON, /* ducati_l2ram */ |
| 55 | [4] = PWRDM_POWER_ON, /* ducati_unicache */ |
| 56 | }, |
| 57 | }; |
| 58 | |
| 59 | /* gfx_44xx_pwrdm: 3D accelerator power domain */ |
| 60 | static struct powerdomain gfx_44xx_pwrdm = { |
| 61 | .name = "gfx_pwrdm", |
| 62 | .prcm_offs = OMAP4430_PRM_GFX_MOD, |
| 63 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 64 | .pwrsts = PWRSTS_OFF_ON, |
| 65 | .banks = 1, |
| 66 | .pwrsts_mem_ret = { |
| 67 | [0] = PWRDM_POWER_OFF, /* gfx_mem */ |
| 68 | }, |
| 69 | .pwrsts_mem_on = { |
| 70 | [0] = PWRDM_POWER_ON, /* gfx_mem */ |
| 71 | }, |
| 72 | }; |
| 73 | |
| 74 | /* abe_44xx_pwrdm: Audio back end power domain */ |
| 75 | static struct powerdomain abe_44xx_pwrdm = { |
| 76 | .name = "abe_pwrdm", |
| 77 | .prcm_offs = OMAP4430_PRM_ABE_MOD, |
| 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 79 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 80 | .pwrsts_logic_ret = PWRDM_POWER_OFF, |
| 81 | .banks = 2, |
| 82 | .pwrsts_mem_ret = { |
| 83 | [0] = PWRDM_POWER_RET, /* aessmem */ |
| 84 | [1] = PWRDM_POWER_OFF, /* periphmem */ |
| 85 | }, |
| 86 | .pwrsts_mem_on = { |
| 87 | [0] = PWRDM_POWER_ON, /* aessmem */ |
| 88 | [1] = PWRDM_POWER_ON, /* periphmem */ |
| 89 | }, |
| 90 | }; |
| 91 | |
| 92 | /* dss_44xx_pwrdm: Display subsystem power domain */ |
| 93 | static struct powerdomain dss_44xx_pwrdm = { |
| 94 | .name = "dss_pwrdm", |
| 95 | .prcm_offs = OMAP4430_PRM_DSS_MOD, |
| 96 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 97 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 98 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 99 | .banks = 1, |
| 100 | .pwrsts_mem_ret = { |
| 101 | [0] = PWRDM_POWER_OFF, /* dss_mem */ |
| 102 | }, |
| 103 | .pwrsts_mem_on = { |
| 104 | [0] = PWRDM_POWER_ON, /* dss_mem */ |
| 105 | }, |
| 106 | }; |
| 107 | |
| 108 | /* tesla_44xx_pwrdm: Tesla processor power domain */ |
| 109 | static struct powerdomain tesla_44xx_pwrdm = { |
| 110 | .name = "tesla_pwrdm", |
| 111 | .prcm_offs = OMAP4430_PRM_TESLA_MOD, |
| 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 113 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 114 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 115 | .banks = 3, |
| 116 | .pwrsts_mem_ret = { |
| 117 | [0] = PWRDM_POWER_RET, /* tesla_edma */ |
| 118 | [1] = PWRSTS_OFF_RET, /* tesla_l1 */ |
| 119 | [2] = PWRSTS_OFF_RET, /* tesla_l2 */ |
| 120 | }, |
| 121 | .pwrsts_mem_on = { |
| 122 | [0] = PWRDM_POWER_ON, /* tesla_edma */ |
| 123 | [1] = PWRDM_POWER_ON, /* tesla_l1 */ |
| 124 | [2] = PWRDM_POWER_ON, /* tesla_l2 */ |
| 125 | }, |
| 126 | }; |
| 127 | |
| 128 | /* wkup_44xx_pwrdm: Wake-up power domain */ |
| 129 | static struct powerdomain wkup_44xx_pwrdm = { |
| 130 | .name = "wkup_pwrdm", |
| 131 | .prcm_offs = OMAP4430_PRM_WKUP_MOD, |
| 132 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 133 | .pwrsts = PWRDM_POWER_ON, |
| 134 | .banks = 1, |
| 135 | .pwrsts_mem_ret = { |
| 136 | [0] = PWRDM_POWER_OFF, /* wkup_bank */ |
| 137 | }, |
| 138 | .pwrsts_mem_on = { |
| 139 | [0] = PWRDM_POWER_ON, /* wkup_bank */ |
| 140 | }, |
| 141 | }; |
| 142 | |
| 143 | /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ |
| 144 | static struct powerdomain cpu0_44xx_pwrdm = { |
| 145 | .name = "cpu0_pwrdm", |
Benoit Cousson | 7932870 | 2010-05-20 12:31:11 -0600 | [diff] [blame] | 146 | .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, |
Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 147 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 148 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 149 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 150 | .banks = 1, |
| 151 | .pwrsts_mem_ret = { |
| 152 | [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ |
| 153 | }, |
| 154 | .pwrsts_mem_on = { |
| 155 | [0] = PWRDM_POWER_ON, /* cpu0_l1 */ |
| 156 | }, |
| 157 | }; |
| 158 | |
| 159 | /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ |
| 160 | static struct powerdomain cpu1_44xx_pwrdm = { |
| 161 | .name = "cpu1_pwrdm", |
Benoit Cousson | 7932870 | 2010-05-20 12:31:11 -0600 | [diff] [blame] | 162 | .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, |
Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 163 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 164 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 165 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 166 | .banks = 1, |
| 167 | .pwrsts_mem_ret = { |
| 168 | [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ |
| 169 | }, |
| 170 | .pwrsts_mem_on = { |
| 171 | [0] = PWRDM_POWER_ON, /* cpu1_l1 */ |
| 172 | }, |
| 173 | }; |
| 174 | |
| 175 | /* emu_44xx_pwrdm: Emulation power domain */ |
| 176 | static struct powerdomain emu_44xx_pwrdm = { |
| 177 | .name = "emu_pwrdm", |
| 178 | .prcm_offs = OMAP4430_PRM_EMU_MOD, |
| 179 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 180 | .pwrsts = PWRSTS_OFF_ON, |
| 181 | .banks = 1, |
| 182 | .pwrsts_mem_ret = { |
| 183 | [0] = PWRDM_POWER_OFF, /* emu_bank */ |
| 184 | }, |
| 185 | .pwrsts_mem_on = { |
| 186 | [0] = PWRDM_POWER_ON, /* emu_bank */ |
| 187 | }, |
| 188 | }; |
| 189 | |
| 190 | /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ |
| 191 | static struct powerdomain mpu_44xx_pwrdm = { |
| 192 | .name = "mpu_pwrdm", |
| 193 | .prcm_offs = OMAP4430_PRM_MPU_MOD, |
| 194 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 195 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 196 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 197 | .banks = 3, |
| 198 | .pwrsts_mem_ret = { |
| 199 | [0] = PWRSTS_OFF_RET, /* mpu_l1 */ |
| 200 | [1] = PWRSTS_OFF_RET, /* mpu_l2 */ |
| 201 | [2] = PWRDM_POWER_RET, /* mpu_ram */ |
| 202 | }, |
| 203 | .pwrsts_mem_on = { |
| 204 | [0] = PWRDM_POWER_ON, /* mpu_l1 */ |
| 205 | [1] = PWRDM_POWER_ON, /* mpu_l2 */ |
| 206 | [2] = PWRDM_POWER_ON, /* mpu_ram */ |
| 207 | }, |
| 208 | }; |
| 209 | |
| 210 | /* ivahd_44xx_pwrdm: IVA-HD power domain */ |
| 211 | static struct powerdomain ivahd_44xx_pwrdm = { |
| 212 | .name = "ivahd_pwrdm", |
| 213 | .prcm_offs = OMAP4430_PRM_IVAHD_MOD, |
| 214 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 215 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 216 | .pwrsts_logic_ret = PWRDM_POWER_OFF, |
| 217 | .banks = 4, |
| 218 | .pwrsts_mem_ret = { |
| 219 | [0] = PWRDM_POWER_OFF, /* hwa_mem */ |
| 220 | [1] = PWRSTS_OFF_RET, /* sl2_mem */ |
| 221 | [2] = PWRSTS_OFF_RET, /* tcm1_mem */ |
| 222 | [3] = PWRSTS_OFF_RET, /* tcm2_mem */ |
| 223 | }, |
| 224 | .pwrsts_mem_on = { |
| 225 | [0] = PWRDM_POWER_ON, /* hwa_mem */ |
| 226 | [1] = PWRDM_POWER_ON, /* sl2_mem */ |
| 227 | [2] = PWRDM_POWER_ON, /* tcm1_mem */ |
| 228 | [3] = PWRDM_POWER_ON, /* tcm2_mem */ |
| 229 | }, |
| 230 | }; |
| 231 | |
| 232 | /* cam_44xx_pwrdm: Camera subsystem power domain */ |
| 233 | static struct powerdomain cam_44xx_pwrdm = { |
| 234 | .name = "cam_pwrdm", |
| 235 | .prcm_offs = OMAP4430_PRM_CAM_MOD, |
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 237 | .pwrsts = PWRSTS_OFF_ON, |
| 238 | .banks = 1, |
| 239 | .pwrsts_mem_ret = { |
| 240 | [0] = PWRDM_POWER_OFF, /* cam_mem */ |
| 241 | }, |
| 242 | .pwrsts_mem_on = { |
| 243 | [0] = PWRDM_POWER_ON, /* cam_mem */ |
| 244 | }, |
| 245 | }; |
| 246 | |
| 247 | /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ |
| 248 | static struct powerdomain l3init_44xx_pwrdm = { |
| 249 | .name = "l3init_pwrdm", |
| 250 | .prcm_offs = OMAP4430_PRM_L3INIT_MOD, |
| 251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 252 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 253 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 254 | .banks = 1, |
| 255 | .pwrsts_mem_ret = { |
| 256 | [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ |
| 257 | }, |
| 258 | .pwrsts_mem_on = { |
| 259 | [0] = PWRDM_POWER_ON, /* l3init_bank1 */ |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | /* l4per_44xx_pwrdm: Target peripherals power domain */ |
| 264 | static struct powerdomain l4per_44xx_pwrdm = { |
| 265 | .name = "l4per_pwrdm", |
| 266 | .prcm_offs = OMAP4430_PRM_L4PER_MOD, |
| 267 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 268 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 269 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 270 | .banks = 2, |
| 271 | .pwrsts_mem_ret = { |
| 272 | [0] = PWRDM_POWER_OFF, /* nonretained_bank */ |
| 273 | [1] = PWRDM_POWER_RET, /* retained_bank */ |
| 274 | }, |
| 275 | .pwrsts_mem_on = { |
| 276 | [0] = PWRDM_POWER_ON, /* nonretained_bank */ |
| 277 | [1] = PWRDM_POWER_ON, /* retained_bank */ |
| 278 | }, |
| 279 | }; |
| 280 | |
| 281 | /* |
| 282 | * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage |
| 283 | * domain |
| 284 | */ |
| 285 | static struct powerdomain always_on_core_44xx_pwrdm = { |
| 286 | .name = "always_on_core_pwrdm", |
| 287 | .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, |
| 288 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 289 | .pwrsts = PWRDM_POWER_ON, |
| 290 | }; |
| 291 | |
| 292 | /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ |
| 293 | static struct powerdomain cefuse_44xx_pwrdm = { |
| 294 | .name = "cefuse_pwrdm", |
| 295 | .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, |
| 296 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 297 | .pwrsts = PWRSTS_OFF_ON, |
| 298 | }; |
| 299 | |
| 300 | /* |
| 301 | * The following power domains are not under SW control |
| 302 | * |
| 303 | * always_on_iva |
| 304 | * always_on_mpu |
| 305 | * stdefuse |
| 306 | */ |
| 307 | |
| 308 | #endif |
| 309 | |
| 310 | #endif |