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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/acornfb.h
3 *
4 * Copyright (C) 1998,1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Frame buffer code for Acorn platforms
11 */
12#if defined(HAS_VIDC20)
13#include <asm/hardware/iomd.h>
14#define VIDC_PALETTE_SIZE 256
15#define VIDC_NAME "VIDC20"
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#endif
17
18#define EXTEND8(x) ((x)|(x)<<8)
19#define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
20
21struct vidc20_palette {
22 u_int red:8;
23 u_int green:8;
24 u_int blue:8;
25 u_int ext:4;
26 u_int unused:4;
27};
28
29struct vidc_palette {
30 u_int red:4;
31 u_int green:4;
32 u_int blue:4;
33 u_int trans:1;
34 u_int sbz1:13;
35 u_int reg:4;
36 u_int sbz2:2;
37};
38
39union palette {
40 struct vidc20_palette vidc20;
41 struct vidc_palette vidc;
42 u_int p;
43};
44
45struct acornfb_par {
46 struct device *dev;
47 unsigned long screen_end;
48 unsigned int dram_size;
49 unsigned int vram_half_sam;
50 unsigned int palette_size;
51 signed int montype;
52 unsigned int using_vram : 1;
53 unsigned int dpms : 1;
54
55 union palette palette[VIDC_PALETTE_SIZE];
56
57 u32 pseudo_palette[16];
58};
59
60struct vidc_timing {
61 u_int h_cycle;
62 u_int h_sync_width;
63 u_int h_border_start;
64 u_int h_display_start;
65 u_int h_display_end;
66 u_int h_border_end;
67 u_int h_interlace;
68
69 u_int v_cycle;
70 u_int v_sync_width;
71 u_int v_border_start;
72 u_int v_display_start;
73 u_int v_display_end;
74 u_int v_border_end;
75
76 u_int control;
77
78 /* VIDC20 only */
79 u_int pll_ctl;
80};
81
82struct modey_params {
83 u_int y_res;
84 u_int u_margin;
85 u_int b_margin;
86 u_int vsync_len;
87 u_int vf;
88};
89
90struct modex_params {
91 u_int x_res;
92 u_int l_margin;
93 u_int r_margin;
94 u_int hsync_len;
95 u_int clock;
96 u_int hf;
97 const struct modey_params *modey;
98};
99
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100#ifdef HAS_VIDC20
101/*
102 * VIDC20 registers
103 */
104#define VIDC20_CTRL 0xe0000000
105#define VIDC20_CTRL_PIX_VCLK (0 << 0)
106#define VIDC20_CTRL_PIX_HCLK (1 << 0)
107#define VIDC20_CTRL_PIX_RCLK (2 << 0)
108#define VIDC20_CTRL_PIX_CK (0 << 2)
109#define VIDC20_CTRL_PIX_CK2 (1 << 2)
110#define VIDC20_CTRL_PIX_CK3 (2 << 2)
111#define VIDC20_CTRL_PIX_CK4 (3 << 2)
112#define VIDC20_CTRL_PIX_CK5 (4 << 2)
113#define VIDC20_CTRL_PIX_CK6 (5 << 2)
114#define VIDC20_CTRL_PIX_CK7 (6 << 2)
115#define VIDC20_CTRL_PIX_CK8 (7 << 2)
116#define VIDC20_CTRL_1BPP (0 << 5)
117#define VIDC20_CTRL_2BPP (1 << 5)
118#define VIDC20_CTRL_4BPP (2 << 5)
119#define VIDC20_CTRL_8BPP (3 << 5)
120#define VIDC20_CTRL_16BPP (4 << 5)
121#define VIDC20_CTRL_32BPP (6 << 5)
122#define VIDC20_CTRL_FIFO_NS (0 << 8)
123#define VIDC20_CTRL_FIFO_4 (1 << 8)
124#define VIDC20_CTRL_FIFO_8 (2 << 8)
125#define VIDC20_CTRL_FIFO_12 (3 << 8)
126#define VIDC20_CTRL_FIFO_16 (4 << 8)
127#define VIDC20_CTRL_FIFO_20 (5 << 8)
128#define VIDC20_CTRL_FIFO_24 (6 << 8)
129#define VIDC20_CTRL_FIFO_28 (7 << 8)
130#define VIDC20_CTRL_INT (1 << 12)
131#define VIDC20_CTRL_DUP (1 << 13)
132#define VIDC20_CTRL_PDOWN (1 << 14)
133
134#define VIDC20_ECTL 0xc0000000
135#define VIDC20_ECTL_REG(x) ((x) & 0xf3)
136#define VIDC20_ECTL_ECK (1 << 2)
137#define VIDC20_ECTL_REDPED (1 << 8)
138#define VIDC20_ECTL_GREENPED (1 << 9)
139#define VIDC20_ECTL_BLUEPED (1 << 10)
140#define VIDC20_ECTL_DAC (1 << 12)
141#define VIDC20_ECTL_LCDGS (1 << 13)
142#define VIDC20_ECTL_HRM (1 << 14)
143
144#define VIDC20_ECTL_HS_MASK (3 << 16)
145#define VIDC20_ECTL_HS_HSYNC (0 << 16)
146#define VIDC20_ECTL_HS_NHSYNC (1 << 16)
147#define VIDC20_ECTL_HS_CSYNC (2 << 16)
148#define VIDC20_ECTL_HS_NCSYNC (3 << 16)
149
150#define VIDC20_ECTL_VS_MASK (3 << 18)
151#define VIDC20_ECTL_VS_VSYNC (0 << 18)
152#define VIDC20_ECTL_VS_NVSYNC (1 << 18)
153#define VIDC20_ECTL_VS_CSYNC (2 << 18)
154#define VIDC20_ECTL_VS_NCSYNC (3 << 18)
155
156#define VIDC20_DCTL 0xf0000000
157/* 0-9 = number of words in scanline */
158#define VIDC20_DCTL_SNA (1 << 12)
159#define VIDC20_DCTL_HDIS (1 << 13)
160#define VIDC20_DCTL_BUS_NS (0 << 16)
161#define VIDC20_DCTL_BUS_D31_0 (1 << 16)
162#define VIDC20_DCTL_BUS_D63_32 (2 << 16)
163#define VIDC20_DCTL_BUS_D63_0 (3 << 16)
164#define VIDC20_DCTL_VRAM_DIS (0 << 18)
165#define VIDC20_DCTL_VRAM_PXCLK (1 << 18)
166#define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
167#define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
168
169#endif