Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/dcb.h> |
| 27 | #include <subdev/bios/dp.h> |
| 28 | #include <subdev/bios/init.h> |
| 29 | #include <subdev/i2c.h> |
| 30 | |
| 31 | #include <engine/disp.h> |
| 32 | |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 33 | #include <core/class.h> |
| 34 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 35 | #include "dport.h" |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 36 | #include "outpdp.h" |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 37 | |
| 38 | /****************************************************************************** |
| 39 | * link training |
| 40 | *****************************************************************************/ |
| 41 | struct dp_state { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 42 | struct nvkm_output_dp *outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 43 | int link_nr; |
| 44 | u32 link_bw; |
| 45 | u8 stat[6]; |
| 46 | u8 conf[4]; |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 47 | bool pc2; |
| 48 | u8 pc2stat; |
| 49 | u8 pc2conf[2]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | static int |
| 53 | dp_set_link_config(struct dp_state *dp) |
| 54 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 55 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 56 | struct nvkm_output_dp *outp = dp->outp; |
| 57 | struct nouveau_disp *disp = nouveau_disp(outp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 58 | struct nouveau_bios *bios = nouveau_bios(disp); |
| 59 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 60 | .subdev = nv_subdev(disp), |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 61 | .bios = bios, |
| 62 | .offset = 0x0000, |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 63 | .outp = &outp->base.info, |
| 64 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 65 | .execute = 1, |
| 66 | }; |
| 67 | u32 lnkcmp; |
| 68 | u8 sink[2]; |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 69 | int ret; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 70 | |
| 71 | DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); |
| 72 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 73 | /* set desired link configuration on the source */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 74 | if ((lnkcmp = dp->outp->info.lnkcmp)) { |
| 75 | if (outp->version < 0x30) { |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 76 | while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) |
| 77 | lnkcmp += 4; |
| 78 | init.offset = nv_ro16(bios, lnkcmp + 2); |
| 79 | } else { |
| 80 | while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) |
| 81 | lnkcmp += 3; |
| 82 | init.offset = nv_ro16(bios, lnkcmp + 1); |
| 83 | } |
| 84 | |
| 85 | nvbios_exec(&init); |
| 86 | } |
| 87 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 88 | ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, |
| 89 | outp->dpcd[DPCD_RC02] & |
| 90 | DPCD_RC02_ENHANCED_FRAME_CAP); |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 91 | if (ret) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 92 | if (ret < 0) |
| 93 | ERR("lnk_ctl failed with %d\n", ret); |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 94 | return ret; |
| 95 | } |
| 96 | |
Ben Skeggs | 1ecee1c | 2014-05-26 11:57:57 +1000 | [diff] [blame^] | 97 | impl->lnk_pwr(outp, dp->link_nr); |
| 98 | |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 99 | /* set desired link configuration on the sink */ |
| 100 | sink[0] = dp->link_bw / 27000; |
| 101 | sink[1] = dp->link_nr; |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 102 | if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 103 | sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; |
| 104 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 105 | return nv_wraux(outp->base.edid, DPCD_LC00, sink, 2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | static void |
| 109 | dp_set_training_pattern(struct dp_state *dp, u8 pattern) |
| 110 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 111 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 112 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 113 | u8 sink_tp; |
| 114 | |
| 115 | DBG("training pattern %d\n", pattern); |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 116 | impl->pattern(outp, pattern); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 117 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 118 | nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 119 | sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; |
| 120 | sink_tp |= pattern; |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 121 | nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static int |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 125 | dp_link_train_commit(struct dp_state *dp, bool pc) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 126 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 127 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 128 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 129 | int ret, i; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 130 | |
| 131 | for (i = 0; i < dp->link_nr; i++) { |
| 132 | u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; |
| 133 | u8 lpre = (lane & 0x0c) >> 2; |
| 134 | u8 lvsw = (lane & 0x03) >> 0; |
| 135 | |
| 136 | dp->conf[i] = (lpre << 3) | lvsw; |
| 137 | if (lvsw == 3) |
| 138 | dp->conf[i] |= DPCD_LC03_MAX_SWING_REACHED; |
| 139 | if (lpre == 3) |
| 140 | dp->conf[i] |= DPCD_LC03_MAX_PRE_EMPHASIS_REACHED; |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 141 | dp->pc2conf[i >> 1] |= 4 << ((i & 1) * 4); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 142 | |
| 143 | DBG("config lane %d %02x\n", i, dp->conf[i]); |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 144 | impl->drv_ctl(outp, i, lvsw, lpre, 0); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 145 | } |
| 146 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 147 | ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 148 | if (ret) |
| 149 | return ret; |
| 150 | |
| 151 | if (pc) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 152 | ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 153 | if (ret) |
| 154 | return ret; |
| 155 | } |
| 156 | |
| 157 | return 0; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static int |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 161 | dp_link_train_update(struct dp_state *dp, bool pc, u32 delay) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 162 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 163 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 164 | int ret; |
| 165 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 166 | if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) |
| 167 | mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); |
Ben Skeggs | fb7c2a7 | 2014-05-15 21:50:07 +1000 | [diff] [blame] | 168 | else |
| 169 | udelay(delay); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 170 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 171 | ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 172 | if (ret) |
| 173 | return ret; |
| 174 | |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 175 | if (pc) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 176 | ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 177 | if (ret) |
| 178 | dp->pc2stat = 0x00; |
| 179 | DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat); |
| 180 | } else { |
| 181 | DBG("status %6ph\n", dp->stat); |
| 182 | } |
| 183 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | static int |
| 188 | dp_link_train_cr(struct dp_state *dp) |
| 189 | { |
| 190 | bool cr_done = false, abort = false; |
| 191 | int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 192 | int tries = 0, i; |
| 193 | |
| 194 | dp_set_training_pattern(dp, 1); |
| 195 | |
| 196 | do { |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 197 | if (dp_link_train_commit(dp, false) || |
| 198 | dp_link_train_update(dp, false, 100)) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 199 | break; |
| 200 | |
| 201 | cr_done = true; |
| 202 | for (i = 0; i < dp->link_nr; i++) { |
| 203 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 204 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { |
| 205 | cr_done = false; |
| 206 | if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED) |
| 207 | abort = true; |
| 208 | break; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { |
| 213 | voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 214 | tries = 0; |
| 215 | } |
| 216 | } while (!cr_done && !abort && ++tries < 5); |
| 217 | |
| 218 | return cr_done ? 0 : -1; |
| 219 | } |
| 220 | |
| 221 | static int |
| 222 | dp_link_train_eq(struct dp_state *dp) |
| 223 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 224 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | c5bd028 | 2013-04-11 10:12:48 +1000 | [diff] [blame] | 225 | bool eq_done = false, cr_done = true; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 226 | int tries = 0, i; |
| 227 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 228 | if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) |
Ben Skeggs | 6e8e268 | 2014-05-15 22:00:06 +1000 | [diff] [blame] | 229 | dp_set_training_pattern(dp, 3); |
| 230 | else |
| 231 | dp_set_training_pattern(dp, 2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 232 | |
| 233 | do { |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 234 | if (dp_link_train_update(dp, dp->pc2, 400)) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 235 | break; |
| 236 | |
| 237 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); |
| 238 | for (i = 0; i < dp->link_nr && eq_done; i++) { |
| 239 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 240 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) |
| 241 | cr_done = false; |
| 242 | if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || |
| 243 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) |
| 244 | eq_done = false; |
| 245 | } |
| 246 | |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 247 | if (dp_link_train_commit(dp, dp->pc2)) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 248 | break; |
| 249 | } while (!eq_done && cr_done && ++tries <= 5); |
| 250 | |
| 251 | return eq_done ? 0 : -1; |
| 252 | } |
| 253 | |
| 254 | static void |
| 255 | dp_link_train_init(struct dp_state *dp, bool spread) |
| 256 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 257 | struct nvkm_output_dp *outp = dp->outp; |
| 258 | struct nouveau_disp *disp = nouveau_disp(outp); |
| 259 | struct nouveau_bios *bios = nouveau_bios(disp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 260 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 261 | .subdev = nv_subdev(disp), |
| 262 | .bios = bios, |
| 263 | .outp = &outp->base.info, |
| 264 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 265 | .execute = 1, |
| 266 | }; |
| 267 | |
| 268 | /* set desired spread */ |
| 269 | if (spread) |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 270 | init.offset = outp->info.script[2]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 271 | else |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 272 | init.offset = outp->info.script[3]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 273 | nvbios_exec(&init); |
| 274 | |
| 275 | /* pre-train script */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 276 | init.offset = outp->info.script[0]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 277 | nvbios_exec(&init); |
| 278 | } |
| 279 | |
| 280 | static void |
| 281 | dp_link_train_fini(struct dp_state *dp) |
| 282 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 283 | struct nvkm_output_dp *outp = dp->outp; |
| 284 | struct nouveau_disp *disp = nouveau_disp(outp); |
| 285 | struct nouveau_bios *bios = nouveau_bios(disp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 286 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 287 | .subdev = nv_subdev(disp), |
| 288 | .bios = bios, |
| 289 | .outp = &outp->base.info, |
| 290 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 291 | .execute = 1, |
| 292 | }; |
| 293 | |
| 294 | /* post-train script */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 295 | init.offset = outp->info.script[1], |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 296 | nvbios_exec(&init); |
| 297 | } |
| 298 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 299 | static const struct dp_rates { |
| 300 | u32 rate; |
| 301 | u8 bw; |
| 302 | u8 nr; |
| 303 | } nouveau_dp_rates[] = { |
| 304 | { 2160000, 0x14, 4 }, |
| 305 | { 1080000, 0x0a, 4 }, |
| 306 | { 1080000, 0x14, 2 }, |
| 307 | { 648000, 0x06, 4 }, |
| 308 | { 540000, 0x0a, 2 }, |
| 309 | { 540000, 0x14, 1 }, |
| 310 | { 324000, 0x06, 2 }, |
| 311 | { 270000, 0x0a, 1 }, |
| 312 | { 162000, 0x06, 1 }, |
| 313 | {} |
| 314 | }; |
| 315 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 316 | int |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 317 | nouveau_dp_train(struct nvkm_output_dp *outp, u32 datarate) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 318 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 319 | struct nouveau_disp *disp = nouveau_disp(outp); |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 320 | const struct dp_rates *cfg = nouveau_dp_rates; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 321 | struct dp_state _dp = { |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 322 | .outp = outp, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 323 | }, *dp = &_dp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 324 | int ret; |
| 325 | |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 326 | /* bring capabilities within encoder limits */ |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 327 | if (nv_mclass(disp) < NVD0_DISP_CLASS) |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 328 | outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; |
| 329 | if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { |
| 330 | outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; |
| 331 | outp->dpcd[2] |= outp->base.info.dpconf.link_nr; |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 332 | } |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 333 | if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) |
| 334 | outp->dpcd[1] = outp->base.info.dpconf.link_bw; |
| 335 | dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED; |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 336 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 337 | /* restrict link config to the lowest required rate, if requested */ |
| 338 | if (datarate) { |
| 339 | datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */ |
| 340 | while (cfg[1].rate >= datarate) |
| 341 | cfg++; |
| 342 | } |
| 343 | cfg--; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 344 | |
| 345 | /* enable down-spreading and execute pre-train script from vbios */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 346 | dp_link_train_init(dp, outp->dpcd[3] & 0x01); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 347 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 348 | while (ret = -EIO, (++cfg)->rate) { |
| 349 | /* select next configuration supported by encoder and sink */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 350 | while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) || |
| 351 | cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE])) |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 352 | cfg++; |
| 353 | dp->link_bw = cfg->bw * 27000; |
| 354 | dp->link_nr = cfg->nr; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 355 | |
| 356 | /* program selected link configuration */ |
| 357 | ret = dp_set_link_config(dp); |
| 358 | if (ret == 0) { |
| 359 | /* attempt to train the link at this configuration */ |
| 360 | memset(dp->stat, 0x00, sizeof(dp->stat)); |
| 361 | if (!dp_link_train_cr(dp) && |
| 362 | !dp_link_train_eq(dp)) |
| 363 | break; |
| 364 | } else |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 365 | if (ret) { |
| 366 | /* dp_set_link_config() handled training, or |
| 367 | * we failed to communicate with the sink. |
| 368 | */ |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 369 | break; |
| 370 | } |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | /* finish link training */ |
| 374 | dp_set_training_pattern(dp, 0); |
Ben Skeggs | 687d8f6 | 2013-11-01 09:36:42 +1000 | [diff] [blame] | 375 | if (ret < 0) |
| 376 | ERR("link training failed\n"); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 377 | |
| 378 | /* execute post-train script from vbios */ |
| 379 | dp_link_train_fini(dp); |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 380 | return (ret < 0) ? false : true; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 381 | } |