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Laurent Pinchart87244fe2014-07-09 00:42:19 +02001/*
2 * Renesas R-Car Gen2 DMA Controller Driver
3 *
4 * Copyright (C) 2014 Renesas Electronics Inc.
5 *
6 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 */
12
Laurent Pinchartccadee92014-07-16 23:15:48 +020013#include <linux/dma-mapping.h>
Laurent Pinchart87244fe2014-07-09 00:42:19 +020014#include <linux/dmaengine.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/of.h>
20#include <linux/of_dma.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
27#include "../dmaengine.h"
28
29/*
30 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
31 * @node: entry in the parent's chunks list
32 * @src_addr: device source address
33 * @dst_addr: device destination address
34 * @size: transfer size in bytes
35 */
36struct rcar_dmac_xfer_chunk {
37 struct list_head node;
38
39 dma_addr_t src_addr;
40 dma_addr_t dst_addr;
41 u32 size;
42};
43
44/*
Laurent Pinchartccadee92014-07-16 23:15:48 +020045 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
46 * @sar: value of the SAR register (source address)
47 * @dar: value of the DAR register (destination address)
48 * @tcr: value of the TCR register (transfer count)
49 */
50struct rcar_dmac_hw_desc {
51 u32 sar;
52 u32 dar;
53 u32 tcr;
54 u32 reserved;
55} __attribute__((__packed__));
56
57/*
Laurent Pinchart87244fe2014-07-09 00:42:19 +020058 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
59 * @async_tx: base DMA asynchronous transaction descriptor
60 * @direction: direction of the DMA transfer
61 * @xfer_shift: log2 of the transfer size
62 * @chcr: value of the channel configuration register for this transfer
63 * @node: entry in the channel's descriptors lists
64 * @chunks: list of transfer chunks for this transfer
65 * @running: the transfer chunk being currently processed
Laurent Pinchartccadee92014-07-16 23:15:48 +020066 * @nchunks: number of transfer chunks for this transfer
Laurent Pinchart1ed13152014-07-19 00:05:14 +020067 * @hwdescs.use: whether the transfer descriptor uses hardware descriptors
Laurent Pinchartccadee92014-07-16 23:15:48 +020068 * @hwdescs.mem: hardware descriptors memory for the transfer
69 * @hwdescs.dma: device address of the hardware descriptors memory
70 * @hwdescs.size: size of the hardware descriptors in bytes
Laurent Pinchart87244fe2014-07-09 00:42:19 +020071 * @size: transfer size in bytes
72 * @cyclic: when set indicates that the DMA transfer is cyclic
73 */
74struct rcar_dmac_desc {
75 struct dma_async_tx_descriptor async_tx;
76 enum dma_transfer_direction direction;
77 unsigned int xfer_shift;
78 u32 chcr;
79
80 struct list_head node;
81 struct list_head chunks;
82 struct rcar_dmac_xfer_chunk *running;
Laurent Pinchartccadee92014-07-16 23:15:48 +020083 unsigned int nchunks;
84
85 struct {
Laurent Pinchart1ed13152014-07-19 00:05:14 +020086 bool use;
Laurent Pinchartccadee92014-07-16 23:15:48 +020087 struct rcar_dmac_hw_desc *mem;
88 dma_addr_t dma;
89 size_t size;
90 } hwdescs;
Laurent Pinchart87244fe2014-07-09 00:42:19 +020091
92 unsigned int size;
93 bool cyclic;
94};
95
96#define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx)
97
98/*
99 * struct rcar_dmac_desc_page - One page worth of descriptors
100 * @node: entry in the channel's pages list
101 * @descs: array of DMA descriptors
102 * @chunks: array of transfer chunk descriptors
103 */
104struct rcar_dmac_desc_page {
105 struct list_head node;
106
107 union {
108 struct rcar_dmac_desc descs[0];
109 struct rcar_dmac_xfer_chunk chunks[0];
110 };
111};
112
113#define RCAR_DMAC_DESCS_PER_PAGE \
114 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \
115 sizeof(struct rcar_dmac_desc))
116#define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \
117 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \
118 sizeof(struct rcar_dmac_xfer_chunk))
119
120/*
121 * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel
122 * @chan: base DMA channel object
123 * @iomem: channel I/O memory base
124 * @index: index of this channel in the controller
125 * @src_xfer_size: size (in bytes) of hardware transfers on the source side
126 * @dst_xfer_size: size (in bytes) of hardware transfers on the destination side
127 * @src_slave_addr: slave source memory address
128 * @dst_slave_addr: slave destination memory address
129 * @mid_rid: hardware MID/RID for the DMA client using this channel
130 * @lock: protects the channel CHCR register and the desc members
131 * @desc.free: list of free descriptors
132 * @desc.pending: list of pending descriptors (submitted with tx_submit)
133 * @desc.active: list of active descriptors (activated with issue_pending)
134 * @desc.done: list of completed descriptors
135 * @desc.wait: list of descriptors waiting for an ack
136 * @desc.running: the descriptor being processed (a member of the active list)
137 * @desc.chunks_free: list of free transfer chunk descriptors
138 * @desc.pages: list of pages used by allocated descriptors
139 */
140struct rcar_dmac_chan {
141 struct dma_chan chan;
142 void __iomem *iomem;
143 unsigned int index;
144
145 unsigned int src_xfer_size;
146 unsigned int dst_xfer_size;
147 dma_addr_t src_slave_addr;
148 dma_addr_t dst_slave_addr;
149 int mid_rid;
150
151 spinlock_t lock;
152
153 struct {
154 struct list_head free;
155 struct list_head pending;
156 struct list_head active;
157 struct list_head done;
158 struct list_head wait;
159 struct rcar_dmac_desc *running;
160
161 struct list_head chunks_free;
162
163 struct list_head pages;
164 } desc;
165};
166
167#define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan)
168
169/*
170 * struct rcar_dmac - R-Car Gen2 DMA Controller
171 * @engine: base DMA engine object
172 * @dev: the hardware device
173 * @iomem: remapped I/O memory base
174 * @n_channels: number of available channels
175 * @channels: array of DMAC channels
176 * @modules: bitmask of client modules in use
177 */
178struct rcar_dmac {
179 struct dma_device engine;
180 struct device *dev;
181 void __iomem *iomem;
182
183 unsigned int n_channels;
184 struct rcar_dmac_chan *channels;
185
186 unsigned long modules[256 / BITS_PER_LONG];
187};
188
189#define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
190
191/* -----------------------------------------------------------------------------
192 * Registers
193 */
194
195#define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i))
196
197#define RCAR_DMAISTA 0x0020
198#define RCAR_DMASEC 0x0030
199#define RCAR_DMAOR 0x0060
200#define RCAR_DMAOR_PRI_FIXED (0 << 8)
201#define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8)
202#define RCAR_DMAOR_AE (1 << 2)
203#define RCAR_DMAOR_DME (1 << 0)
204#define RCAR_DMACHCLR 0x0080
205#define RCAR_DMADPSEC 0x00a0
206
207#define RCAR_DMASAR 0x0000
208#define RCAR_DMADAR 0x0004
209#define RCAR_DMATCR 0x0008
210#define RCAR_DMATCR_MASK 0x00ffffff
211#define RCAR_DMATSR 0x0028
212#define RCAR_DMACHCR 0x000c
213#define RCAR_DMACHCR_CAE (1 << 31)
214#define RCAR_DMACHCR_CAIE (1 << 30)
215#define RCAR_DMACHCR_DPM_DISABLED (0 << 28)
216#define RCAR_DMACHCR_DPM_ENABLED (1 << 28)
217#define RCAR_DMACHCR_DPM_REPEAT (2 << 28)
218#define RCAR_DMACHCR_DPM_INFINITE (3 << 28)
219#define RCAR_DMACHCR_RPT_SAR (1 << 27)
220#define RCAR_DMACHCR_RPT_DAR (1 << 26)
221#define RCAR_DMACHCR_RPT_TCR (1 << 25)
222#define RCAR_DMACHCR_DPB (1 << 22)
223#define RCAR_DMACHCR_DSE (1 << 19)
224#define RCAR_DMACHCR_DSIE (1 << 18)
225#define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3))
226#define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3))
227#define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3))
228#define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3))
229#define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3))
230#define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3))
231#define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3))
232#define RCAR_DMACHCR_DM_FIXED (0 << 14)
233#define RCAR_DMACHCR_DM_INC (1 << 14)
234#define RCAR_DMACHCR_DM_DEC (2 << 14)
235#define RCAR_DMACHCR_SM_FIXED (0 << 12)
236#define RCAR_DMACHCR_SM_INC (1 << 12)
237#define RCAR_DMACHCR_SM_DEC (2 << 12)
238#define RCAR_DMACHCR_RS_AUTO (4 << 8)
239#define RCAR_DMACHCR_RS_DMARS (8 << 8)
240#define RCAR_DMACHCR_IE (1 << 2)
241#define RCAR_DMACHCR_TE (1 << 1)
242#define RCAR_DMACHCR_DE (1 << 0)
243#define RCAR_DMATCRB 0x0018
244#define RCAR_DMATSRB 0x0038
245#define RCAR_DMACHCRB 0x001c
246#define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
Laurent Pinchartccadee92014-07-16 23:15:48 +0200247#define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
248#define RCAR_DMACHCRB_DPTR_SHIFT 16
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200249#define RCAR_DMACHCRB_DRST (1 << 15)
250#define RCAR_DMACHCRB_DTS (1 << 8)
251#define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
252#define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4)
253#define RCAR_DMACHCRB_PRI(n) ((n) << 0)
254#define RCAR_DMARS 0x0040
255#define RCAR_DMABUFCR 0x0048
256#define RCAR_DMABUFCR_MBU(n) ((n) << 16)
257#define RCAR_DMABUFCR_ULB(n) ((n) << 0)
258#define RCAR_DMADPBASE 0x0050
259#define RCAR_DMADPBASE_MASK 0xfffffff0
260#define RCAR_DMADPBASE_SEL (1 << 0)
261#define RCAR_DMADPCR 0x0054
262#define RCAR_DMADPCR_DIPT(n) ((n) << 24)
263#define RCAR_DMAFIXSAR 0x0010
264#define RCAR_DMAFIXDAR 0x0014
265#define RCAR_DMAFIXDPBASE 0x0060
266
267/* Hardcode the MEMCPY transfer size to 4 bytes. */
268#define RCAR_DMAC_MEMCPY_XFER_SIZE 4
269
270/* -----------------------------------------------------------------------------
271 * Device access
272 */
273
274static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data)
275{
276 if (reg == RCAR_DMAOR)
277 writew(data, dmac->iomem + reg);
278 else
279 writel(data, dmac->iomem + reg);
280}
281
282static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg)
283{
284 if (reg == RCAR_DMAOR)
285 return readw(dmac->iomem + reg);
286 else
287 return readl(dmac->iomem + reg);
288}
289
290static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg)
291{
292 if (reg == RCAR_DMARS)
293 return readw(chan->iomem + reg);
294 else
295 return readl(chan->iomem + reg);
296}
297
298static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
299{
300 if (reg == RCAR_DMARS)
301 writew(data, chan->iomem + reg);
302 else
303 writel(data, chan->iomem + reg);
304}
305
306/* -----------------------------------------------------------------------------
307 * Initialization and configuration
308 */
309
310static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
311{
312 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
313
314 return (chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE)) == RCAR_DMACHCR_DE;
315}
316
317static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
318{
319 struct rcar_dmac_desc *desc = chan->desc.running;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200320 u32 chcr = desc->chcr;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200321
322 WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
323
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200324 if (chan->mid_rid >= 0)
325 rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
326
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200327 if (desc->hwdescs.use) {
Laurent Pinchartccadee92014-07-16 23:15:48 +0200328 dev_dbg(chan->chan.device->dev,
329 "chan%u: queue desc %p: %u@%pad\n",
330 chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200331
Laurent Pinchartccadee92014-07-16 23:15:48 +0200332#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
333 rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
334 desc->hwdescs.dma >> 32);
335#endif
336 rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
337 (desc->hwdescs.dma & 0xfffffff0) |
338 RCAR_DMADPBASE_SEL);
339 rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
340 RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
341 RCAR_DMACHCRB_DRST);
342
343 /*
344 * Program the descriptor stage interrupt to occur after the end
345 * of the first stage.
346 */
347 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
348
349 chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
350 | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
351
352 /*
353 * If the descriptor isn't cyclic enable normal descriptor mode
354 * and the transfer completion interrupt.
355 */
356 if (!desc->cyclic)
357 chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
358 /*
359 * If the descriptor is cyclic and has a callback enable the
360 * descriptor stage interrupt in infinite repeat mode.
361 */
362 else if (desc->async_tx.callback)
363 chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
364 /*
365 * Otherwise just select infinite repeat mode without any
366 * interrupt.
367 */
368 else
369 chcr |= RCAR_DMACHCR_DPM_INFINITE;
370 } else {
371 struct rcar_dmac_xfer_chunk *chunk = desc->running;
372
373 dev_dbg(chan->chan.device->dev,
374 "chan%u: queue chunk %p: %u@%pad -> %pad\n",
375 chan->index, chunk, chunk->size, &chunk->src_addr,
376 &chunk->dst_addr);
377
378#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
379 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
380 chunk->src_addr >> 32);
381 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
382 chunk->dst_addr >> 32);
383#endif
384 rcar_dmac_chan_write(chan, RCAR_DMASAR,
385 chunk->src_addr & 0xffffffff);
386 rcar_dmac_chan_write(chan, RCAR_DMADAR,
387 chunk->dst_addr & 0xffffffff);
388 rcar_dmac_chan_write(chan, RCAR_DMATCR,
389 chunk->size >> desc->xfer_shift);
390
391 chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
392 }
393
394 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200395}
396
397static int rcar_dmac_init(struct rcar_dmac *dmac)
398{
399 u16 dmaor;
400
401 /* Clear all channels and enable the DMAC globally. */
402 rcar_dmac_write(dmac, RCAR_DMACHCLR, 0x7fff);
403 rcar_dmac_write(dmac, RCAR_DMAOR,
404 RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
405
406 dmaor = rcar_dmac_read(dmac, RCAR_DMAOR);
407 if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) {
408 dev_warn(dmac->dev, "DMAOR initialization failed.\n");
409 return -EIO;
410 }
411
412 return 0;
413}
414
415/* -----------------------------------------------------------------------------
416 * Descriptors submission
417 */
418
419static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
420{
421 struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan);
422 struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx);
423 unsigned long flags;
424 dma_cookie_t cookie;
425
426 spin_lock_irqsave(&chan->lock, flags);
427
428 cookie = dma_cookie_assign(tx);
429
430 dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n",
431 chan->index, tx->cookie, desc);
432
433 list_add_tail(&desc->node, &chan->desc.pending);
434 desc->running = list_first_entry(&desc->chunks,
435 struct rcar_dmac_xfer_chunk, node);
436
437 spin_unlock_irqrestore(&chan->lock, flags);
438
439 return cookie;
440}
441
442/* -----------------------------------------------------------------------------
443 * Descriptors allocation and free
444 */
445
446/*
447 * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors
448 * @chan: the DMA channel
449 * @gfp: allocation flags
450 */
451static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
452{
453 struct rcar_dmac_desc_page *page;
454 LIST_HEAD(list);
455 unsigned int i;
456
457 page = (void *)get_zeroed_page(gfp);
458 if (!page)
459 return -ENOMEM;
460
461 for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) {
462 struct rcar_dmac_desc *desc = &page->descs[i];
463
464 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
465 desc->async_tx.tx_submit = rcar_dmac_tx_submit;
466 INIT_LIST_HEAD(&desc->chunks);
467
468 list_add_tail(&desc->node, &list);
469 }
470
471 spin_lock_irq(&chan->lock);
472 list_splice_tail(&list, &chan->desc.free);
473 list_add_tail(&page->node, &chan->desc.pages);
474 spin_unlock_irq(&chan->lock);
475
476 return 0;
477}
478
479/*
480 * rcar_dmac_desc_put - Release a DMA transfer descriptor
481 * @chan: the DMA channel
482 * @desc: the descriptor
483 *
484 * Put the descriptor and its transfer chunk descriptors back in the channel's
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200485 * free descriptors lists. The descriptor's chunks list will be reinitialized to
486 * an empty list as a result.
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200487 *
Laurent Pinchartccadee92014-07-16 23:15:48 +0200488 * The descriptor must have been removed from the channel's lists before calling
489 * this function.
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200490 *
Laurent Pinchartccadee92014-07-16 23:15:48 +0200491 * Locking: Must be called in non-atomic context.
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200492 */
493static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
494 struct rcar_dmac_desc *desc)
495{
Laurent Pinchartccadee92014-07-16 23:15:48 +0200496 spin_lock_irq(&chan->lock);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200497 list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
498 list_add_tail(&desc->node, &chan->desc.free);
Laurent Pinchartccadee92014-07-16 23:15:48 +0200499 spin_unlock_irq(&chan->lock);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200500}
501
502static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
503{
504 struct rcar_dmac_desc *desc, *_desc;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200505 LIST_HEAD(list);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200506
Laurent Pinchartccadee92014-07-16 23:15:48 +0200507 /*
508 * We have to temporarily move all descriptors from the wait list to a
509 * local list as iterating over the wait list, even with
510 * list_for_each_entry_safe, isn't safe if we release the channel lock
511 * around the rcar_dmac_desc_put() call.
512 */
513 spin_lock_irq(&chan->lock);
514 list_splice_init(&chan->desc.wait, &list);
515 spin_unlock_irq(&chan->lock);
516
517 list_for_each_entry_safe(desc, _desc, &list, node) {
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200518 if (async_tx_test_ack(&desc->async_tx)) {
519 list_del(&desc->node);
520 rcar_dmac_desc_put(chan, desc);
521 }
522 }
Laurent Pinchartccadee92014-07-16 23:15:48 +0200523
524 if (list_empty(&list))
525 return;
526
527 /* Put the remaining descriptors back in the wait list. */
528 spin_lock_irq(&chan->lock);
529 list_splice(&list, &chan->desc.wait);
530 spin_unlock_irq(&chan->lock);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200531}
532
533/*
534 * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
535 * @chan: the DMA channel
536 *
537 * Locking: This function must be called in a non-atomic context.
538 *
539 * Return: A pointer to the allocated descriptor or NULL if no descriptor can
540 * be allocated.
541 */
542static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
543{
544 struct rcar_dmac_desc *desc;
545 int ret;
546
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200547 /* Recycle acked descriptors before attempting allocation. */
548 rcar_dmac_desc_recycle_acked(chan);
549
Laurent Pinchartccadee92014-07-16 23:15:48 +0200550 spin_lock_irq(&chan->lock);
551
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200552 do {
553 if (list_empty(&chan->desc.free)) {
554 /*
555 * No free descriptors, allocate a page worth of them
556 * and try again, as someone else could race us to get
557 * the newly allocated descriptors. If the allocation
558 * fails return an error.
559 */
560 spin_unlock_irq(&chan->lock);
561 ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT);
562 if (ret < 0)
563 return NULL;
564 spin_lock_irq(&chan->lock);
565 continue;
566 }
567
568 desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc,
569 node);
570 list_del(&desc->node);
571 } while (!desc);
572
573 spin_unlock_irq(&chan->lock);
574
575 return desc;
576}
577
578/*
579 * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
580 * @chan: the DMA channel
581 * @gfp: allocation flags
582 */
583static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
584{
585 struct rcar_dmac_desc_page *page;
586 LIST_HEAD(list);
587 unsigned int i;
588
589 page = (void *)get_zeroed_page(gfp);
590 if (!page)
591 return -ENOMEM;
592
593 for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) {
594 struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i];
595
596 list_add_tail(&chunk->node, &list);
597 }
598
599 spin_lock_irq(&chan->lock);
600 list_splice_tail(&list, &chan->desc.chunks_free);
601 list_add_tail(&page->node, &chan->desc.pages);
602 spin_unlock_irq(&chan->lock);
603
604 return 0;
605}
606
607/*
608 * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
609 * @chan: the DMA channel
610 *
611 * Locking: This function must be called in a non-atomic context.
612 *
613 * Return: A pointer to the allocated transfer chunk descriptor or NULL if no
614 * descriptor can be allocated.
615 */
616static struct rcar_dmac_xfer_chunk *
617rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
618{
619 struct rcar_dmac_xfer_chunk *chunk;
620 int ret;
621
622 spin_lock_irq(&chan->lock);
623
624 do {
625 if (list_empty(&chan->desc.chunks_free)) {
626 /*
627 * No free descriptors, allocate a page worth of them
628 * and try again, as someone else could race us to get
629 * the newly allocated descriptors. If the allocation
630 * fails return an error.
631 */
632 spin_unlock_irq(&chan->lock);
633 ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT);
634 if (ret < 0)
635 return NULL;
636 spin_lock_irq(&chan->lock);
637 continue;
638 }
639
640 chunk = list_first_entry(&chan->desc.chunks_free,
641 struct rcar_dmac_xfer_chunk, node);
642 list_del(&chunk->node);
643 } while (!chunk);
644
645 spin_unlock_irq(&chan->lock);
646
647 return chunk;
648}
649
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200650static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan,
651 struct rcar_dmac_desc *desc, size_t size)
652{
653 /*
654 * dma_alloc_coherent() allocates memory in page size increments. To
655 * avoid reallocating the hardware descriptors when the allocated size
656 * wouldn't change align the requested size to a multiple of the page
657 * size.
658 */
659 size = PAGE_ALIGN(size);
660
661 if (desc->hwdescs.size == size)
662 return;
663
664 if (desc->hwdescs.mem) {
665 dma_free_coherent(NULL, desc->hwdescs.size, desc->hwdescs.mem,
666 desc->hwdescs.dma);
667 desc->hwdescs.mem = NULL;
668 desc->hwdescs.size = 0;
669 }
670
671 if (!size)
672 return;
673
674 desc->hwdescs.mem = dma_alloc_coherent(NULL, size, &desc->hwdescs.dma,
675 GFP_NOWAIT);
676 if (!desc->hwdescs.mem)
677 return;
678
679 desc->hwdescs.size = size;
680}
681
682static void rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
683 struct rcar_dmac_desc *desc)
Laurent Pinchartccadee92014-07-16 23:15:48 +0200684{
685 struct rcar_dmac_xfer_chunk *chunk;
686 struct rcar_dmac_hw_desc *hwdesc;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200687
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200688 rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc));
689
690 hwdesc = desc->hwdescs.mem;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200691 if (!hwdesc)
692 return;
693
Laurent Pinchartccadee92014-07-16 23:15:48 +0200694 list_for_each_entry(chunk, &desc->chunks, node) {
695 hwdesc->sar = chunk->src_addr;
696 hwdesc->dar = chunk->dst_addr;
697 hwdesc->tcr = chunk->size >> desc->xfer_shift;
698 hwdesc++;
699 }
700}
701
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200702/* -----------------------------------------------------------------------------
703 * Stop and reset
704 */
705
706static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
707{
708 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
709
Laurent Pinchartccadee92014-07-16 23:15:48 +0200710 chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
711 RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200712 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
713}
714
715static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
716{
717 struct rcar_dmac_desc *desc, *_desc;
718 unsigned long flags;
719 LIST_HEAD(descs);
720
721 spin_lock_irqsave(&chan->lock, flags);
722
723 /* Move all non-free descriptors to the local lists. */
724 list_splice_init(&chan->desc.pending, &descs);
725 list_splice_init(&chan->desc.active, &descs);
726 list_splice_init(&chan->desc.done, &descs);
727 list_splice_init(&chan->desc.wait, &descs);
728
729 chan->desc.running = NULL;
730
731 spin_unlock_irqrestore(&chan->lock, flags);
732
733 list_for_each_entry_safe(desc, _desc, &descs, node) {
734 list_del(&desc->node);
735 rcar_dmac_desc_put(chan, desc);
736 }
737}
738
739static void rcar_dmac_stop(struct rcar_dmac *dmac)
740{
741 rcar_dmac_write(dmac, RCAR_DMAOR, 0);
742}
743
744static void rcar_dmac_abort(struct rcar_dmac *dmac)
745{
746 unsigned int i;
747
748 /* Stop all channels. */
749 for (i = 0; i < dmac->n_channels; ++i) {
750 struct rcar_dmac_chan *chan = &dmac->channels[i];
751
752 /* Stop and reinitialize the channel. */
753 spin_lock(&chan->lock);
754 rcar_dmac_chan_halt(chan);
755 spin_unlock(&chan->lock);
756
757 rcar_dmac_chan_reinit(chan);
758 }
759}
760
761/* -----------------------------------------------------------------------------
762 * Descriptors preparation
763 */
764
765static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan,
766 struct rcar_dmac_desc *desc)
767{
768 static const u32 chcr_ts[] = {
769 RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B,
770 RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B,
771 RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B,
772 RCAR_DMACHCR_TS_64B,
773 };
774
775 unsigned int xfer_size;
776 u32 chcr;
777
778 switch (desc->direction) {
779 case DMA_DEV_TO_MEM:
780 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
781 | RCAR_DMACHCR_RS_DMARS;
782 xfer_size = chan->src_xfer_size;
783 break;
784
785 case DMA_MEM_TO_DEV:
786 chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
787 | RCAR_DMACHCR_RS_DMARS;
788 xfer_size = chan->dst_xfer_size;
789 break;
790
791 case DMA_MEM_TO_MEM:
792 default:
793 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
794 | RCAR_DMACHCR_RS_AUTO;
795 xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE;
796 break;
797 }
798
799 desc->xfer_shift = ilog2(xfer_size);
800 desc->chcr = chcr | chcr_ts[desc->xfer_shift];
801}
802
803/*
804 * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
805 *
806 * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
807 * converted to scatter-gather to guarantee consistent locking and a correct
808 * list manipulation. For slave DMA direction carries the usual meaning, and,
809 * logically, the SG list is RAM and the addr variable contains slave address,
810 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
811 * and the SG list contains only one element and points at the source buffer.
812 */
813static struct dma_async_tx_descriptor *
814rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
815 unsigned int sg_len, dma_addr_t dev_addr,
816 enum dma_transfer_direction dir, unsigned long dma_flags,
817 bool cyclic)
818{
819 struct rcar_dmac_xfer_chunk *chunk;
820 struct rcar_dmac_desc *desc;
821 struct scatterlist *sg;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200822 unsigned int nchunks = 0;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200823 unsigned int max_chunk_size;
824 unsigned int full_size = 0;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200825 bool highmem = false;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200826 unsigned int i;
827
828 desc = rcar_dmac_desc_get(chan);
829 if (!desc)
830 return NULL;
831
832 desc->async_tx.flags = dma_flags;
833 desc->async_tx.cookie = -EBUSY;
834
835 desc->cyclic = cyclic;
836 desc->direction = dir;
837
838 rcar_dmac_chan_configure_desc(chan, desc);
839
840 max_chunk_size = (RCAR_DMATCR_MASK + 1) << desc->xfer_shift;
841
842 /*
843 * Allocate and fill the transfer chunk descriptors. We own the only
844 * reference to the DMA descriptor, there's no need for locking.
845 */
846 for_each_sg(sgl, sg, sg_len, i) {
847 dma_addr_t mem_addr = sg_dma_address(sg);
848 unsigned int len = sg_dma_len(sg);
849
850 full_size += len;
851
852 while (len) {
853 unsigned int size = min(len, max_chunk_size);
854
855#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
856 /*
857 * Prevent individual transfers from crossing 4GB
858 * boundaries.
859 */
860 if (dev_addr >> 32 != (dev_addr + size - 1) >> 32)
861 size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
862 if (mem_addr >> 32 != (mem_addr + size - 1) >> 32)
863 size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
Laurent Pinchartccadee92014-07-16 23:15:48 +0200864
865 /*
866 * Check if either of the source or destination address
867 * can't be expressed in 32 bits. If so we can't use
868 * hardware descriptor lists.
869 */
870 if (dev_addr >> 32 || mem_addr >> 32)
871 highmem = true;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200872#endif
873
874 chunk = rcar_dmac_xfer_chunk_get(chan);
875 if (!chunk) {
876 rcar_dmac_desc_put(chan, desc);
877 return NULL;
878 }
879
880 if (dir == DMA_DEV_TO_MEM) {
881 chunk->src_addr = dev_addr;
882 chunk->dst_addr = mem_addr;
883 } else {
884 chunk->src_addr = mem_addr;
885 chunk->dst_addr = dev_addr;
886 }
887
888 chunk->size = size;
889
890 dev_dbg(chan->chan.device->dev,
891 "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n",
892 chan->index, chunk, desc, i, sg, size, len,
893 &chunk->src_addr, &chunk->dst_addr);
894
895 mem_addr += size;
896 if (dir == DMA_MEM_TO_MEM)
897 dev_addr += size;
898
899 len -= size;
900
901 list_add_tail(&chunk->node, &desc->chunks);
Laurent Pinchartccadee92014-07-16 23:15:48 +0200902 nchunks++;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200903 }
904 }
905
Laurent Pinchartccadee92014-07-16 23:15:48 +0200906 desc->nchunks = nchunks;
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200907 desc->size = full_size;
908
Laurent Pinchartccadee92014-07-16 23:15:48 +0200909 /*
910 * Use hardware descriptor lists if possible when more than one chunk
911 * needs to be transferred (otherwise they don't make much sense).
912 *
913 * The highmem check currently covers the whole transfer. As an
914 * optimization we could use descriptor lists for consecutive lowmem
915 * chunks and direct manual mode for highmem chunks. Whether the
916 * performance improvement would be significant enough compared to the
917 * additional complexity remains to be investigated.
918 */
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200919 desc->hwdescs.use = !highmem && nchunks > 1;
920 if (desc->hwdescs.use)
921 rcar_dmac_fill_hwdesc(chan, desc);
Laurent Pinchartccadee92014-07-16 23:15:48 +0200922
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200923 return &desc->async_tx;
924}
925
926/* -----------------------------------------------------------------------------
927 * DMA engine operations
928 */
929
930static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan)
931{
932 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
933 int ret;
934
935 INIT_LIST_HEAD(&rchan->desc.free);
936 INIT_LIST_HEAD(&rchan->desc.pending);
937 INIT_LIST_HEAD(&rchan->desc.active);
938 INIT_LIST_HEAD(&rchan->desc.done);
939 INIT_LIST_HEAD(&rchan->desc.wait);
940 INIT_LIST_HEAD(&rchan->desc.chunks_free);
941 INIT_LIST_HEAD(&rchan->desc.pages);
942
943 /* Preallocate descriptors. */
944 ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL);
945 if (ret < 0)
946 return -ENOMEM;
947
948 ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL);
949 if (ret < 0)
950 return -ENOMEM;
951
952 return pm_runtime_get_sync(chan->device->dev);
953}
954
955static void rcar_dmac_free_chan_resources(struct dma_chan *chan)
956{
957 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
958 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
959 struct rcar_dmac_desc_page *page, *_page;
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200960 struct rcar_dmac_desc *desc;
961 LIST_HEAD(list);
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200962
963 /* Protect against ISR */
964 spin_lock_irq(&rchan->lock);
965 rcar_dmac_chan_halt(rchan);
966 spin_unlock_irq(&rchan->lock);
967
968 /* Now no new interrupts will occur */
969
970 if (rchan->mid_rid >= 0) {
971 /* The caller is holding dma_list_mutex */
972 clear_bit(rchan->mid_rid, dmac->modules);
973 rchan->mid_rid = -EINVAL;
974 }
975
Laurent Pinchart1ed13152014-07-19 00:05:14 +0200976 list_splice(&rchan->desc.free, &list);
977 list_splice(&rchan->desc.pending, &list);
978 list_splice(&rchan->desc.active, &list);
979 list_splice(&rchan->desc.done, &list);
980 list_splice(&rchan->desc.wait, &list);
981
982 list_for_each_entry(desc, &list, node)
983 rcar_dmac_realloc_hwdesc(rchan, desc, 0);
984
Laurent Pinchart87244fe2014-07-09 00:42:19 +0200985 list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) {
986 list_del(&page->node);
987 free_page((unsigned long)page);
988 }
989
990 pm_runtime_put(chan->device->dev);
991}
992
993static struct dma_async_tx_descriptor *
994rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
995 dma_addr_t dma_src, size_t len, unsigned long flags)
996{
997 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
998 struct scatterlist sgl;
999
1000 if (!len)
1001 return NULL;
1002
1003 sg_init_table(&sgl, 1);
1004 sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len,
1005 offset_in_page(dma_src));
1006 sg_dma_address(&sgl) = dma_src;
1007 sg_dma_len(&sgl) = len;
1008
1009 return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest,
1010 DMA_MEM_TO_MEM, flags, false);
1011}
1012
1013static struct dma_async_tx_descriptor *
1014rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1015 unsigned int sg_len, enum dma_transfer_direction dir,
1016 unsigned long flags, void *context)
1017{
1018 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1019 dma_addr_t dev_addr;
1020
1021 /* Someone calling slave DMA on a generic channel? */
1022 if (rchan->mid_rid < 0 || !sg_len) {
1023 dev_warn(chan->device->dev,
1024 "%s: bad parameter: len=%d, id=%d\n",
1025 __func__, sg_len, rchan->mid_rid);
1026 return NULL;
1027 }
1028
1029 dev_addr = dir == DMA_DEV_TO_MEM
1030 ? rchan->src_slave_addr : rchan->dst_slave_addr;
1031 return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr,
1032 dir, flags, false);
1033}
1034
1035#define RCAR_DMAC_MAX_SG_LEN 32
1036
1037static struct dma_async_tx_descriptor *
1038rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
1039 size_t buf_len, size_t period_len,
1040 enum dma_transfer_direction dir, unsigned long flags)
1041{
1042 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1043 struct dma_async_tx_descriptor *desc;
1044 struct scatterlist *sgl;
1045 dma_addr_t dev_addr;
1046 unsigned int sg_len;
1047 unsigned int i;
1048
1049 /* Someone calling slave DMA on a generic channel? */
1050 if (rchan->mid_rid < 0 || buf_len < period_len) {
1051 dev_warn(chan->device->dev,
1052 "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n",
1053 __func__, buf_len, period_len, rchan->mid_rid);
1054 return NULL;
1055 }
1056
1057 sg_len = buf_len / period_len;
1058 if (sg_len > RCAR_DMAC_MAX_SG_LEN) {
1059 dev_err(chan->device->dev,
1060 "chan%u: sg length %d exceds limit %d",
1061 rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN);
1062 return NULL;
1063 }
1064
1065 /*
1066 * Allocate the sg list dynamically as it would consume too much stack
1067 * space.
1068 */
1069 sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
1070 if (!sgl)
1071 return NULL;
1072
1073 sg_init_table(sgl, sg_len);
1074
1075 for (i = 0; i < sg_len; ++i) {
1076 dma_addr_t src = buf_addr + (period_len * i);
1077
1078 sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len,
1079 offset_in_page(src));
1080 sg_dma_address(&sgl[i]) = src;
1081 sg_dma_len(&sgl[i]) = period_len;
1082 }
1083
1084 dev_addr = dir == DMA_DEV_TO_MEM
1085 ? rchan->src_slave_addr : rchan->dst_slave_addr;
1086 desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr,
1087 dir, flags, true);
1088
1089 kfree(sgl);
1090 return desc;
1091}
1092
1093static int rcar_dmac_device_config(struct dma_chan *chan,
1094 struct dma_slave_config *cfg)
1095{
1096 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1097
1098 /*
1099 * We could lock this, but you shouldn't be configuring the
1100 * channel, while using it...
1101 */
1102 rchan->src_slave_addr = cfg->src_addr;
1103 rchan->dst_slave_addr = cfg->dst_addr;
1104 rchan->src_xfer_size = cfg->src_addr_width;
1105 rchan->dst_xfer_size = cfg->dst_addr_width;
1106
1107 return 0;
1108}
1109
1110static int rcar_dmac_chan_terminate_all(struct dma_chan *chan)
1111{
1112 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1113 unsigned long flags;
1114
1115 spin_lock_irqsave(&rchan->lock, flags);
1116 rcar_dmac_chan_halt(rchan);
1117 spin_unlock_irqrestore(&rchan->lock, flags);
1118
1119 /*
1120 * FIXME: No new interrupt can occur now, but the IRQ thread might still
1121 * be running.
1122 */
1123
1124 rcar_dmac_chan_reinit(rchan);
1125
1126 return 0;
1127}
1128
1129static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
1130 dma_cookie_t cookie)
1131{
1132 struct rcar_dmac_desc *desc = chan->desc.running;
Laurent Pinchartccadee92014-07-16 23:15:48 +02001133 struct rcar_dmac_xfer_chunk *running = NULL;
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001134 struct rcar_dmac_xfer_chunk *chunk;
1135 unsigned int residue = 0;
Laurent Pinchartccadee92014-07-16 23:15:48 +02001136 unsigned int dptr = 0;
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001137
1138 if (!desc)
1139 return 0;
1140
1141 /*
1142 * If the cookie doesn't correspond to the currently running transfer
1143 * then the descriptor hasn't been processed yet, and the residue is
1144 * equal to the full descriptor size.
1145 */
1146 if (cookie != desc->async_tx.cookie)
1147 return desc->size;
1148
Laurent Pinchartccadee92014-07-16 23:15:48 +02001149 /*
1150 * In descriptor mode the descriptor running pointer is not maintained
1151 * by the interrupt handler, find the running descriptor from the
1152 * descriptor pointer field in the CHCRB register. In non-descriptor
1153 * mode just use the running descriptor pointer.
1154 */
Laurent Pinchart1ed13152014-07-19 00:05:14 +02001155 if (desc->hwdescs.use) {
Laurent Pinchartccadee92014-07-16 23:15:48 +02001156 dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1157 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1158 WARN_ON(dptr >= desc->nchunks);
1159 } else {
1160 running = desc->running;
1161 }
1162
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001163 /* Compute the size of all chunks still to be transferred. */
1164 list_for_each_entry_reverse(chunk, &desc->chunks, node) {
Laurent Pinchartccadee92014-07-16 23:15:48 +02001165 if (chunk == running || ++dptr == desc->nchunks)
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001166 break;
1167
1168 residue += chunk->size;
1169 }
1170
1171 /* Add the residue for the current chunk. */
1172 residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift;
1173
1174 return residue;
1175}
1176
1177static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan,
1178 dma_cookie_t cookie,
1179 struct dma_tx_state *txstate)
1180{
1181 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1182 enum dma_status status;
1183 unsigned long flags;
1184 unsigned int residue;
1185
1186 status = dma_cookie_status(chan, cookie, txstate);
1187 if (status == DMA_COMPLETE || !txstate)
1188 return status;
1189
1190 spin_lock_irqsave(&rchan->lock, flags);
1191 residue = rcar_dmac_chan_get_residue(rchan, cookie);
1192 spin_unlock_irqrestore(&rchan->lock, flags);
1193
1194 dma_set_residue(txstate, residue);
1195
1196 return status;
1197}
1198
1199static void rcar_dmac_issue_pending(struct dma_chan *chan)
1200{
1201 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1202 unsigned long flags;
1203
1204 spin_lock_irqsave(&rchan->lock, flags);
1205
1206 if (list_empty(&rchan->desc.pending))
1207 goto done;
1208
1209 /* Append the pending list to the active list. */
1210 list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active);
1211
1212 /*
1213 * If no transfer is running pick the first descriptor from the active
1214 * list and start the transfer.
1215 */
1216 if (!rchan->desc.running) {
1217 struct rcar_dmac_desc *desc;
1218
1219 desc = list_first_entry(&rchan->desc.active,
1220 struct rcar_dmac_desc, node);
1221 rchan->desc.running = desc;
1222
1223 rcar_dmac_chan_start_xfer(rchan);
1224 }
1225
1226done:
1227 spin_unlock_irqrestore(&rchan->lock, flags);
1228}
1229
1230/* -----------------------------------------------------------------------------
1231 * IRQ handling
1232 */
1233
Laurent Pinchartccadee92014-07-16 23:15:48 +02001234static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan)
1235{
1236 struct rcar_dmac_desc *desc = chan->desc.running;
1237 unsigned int stage;
1238
1239 if (WARN_ON(!desc || !desc->cyclic)) {
1240 /*
1241 * This should never happen, there should always be a running
1242 * cyclic descriptor when a descriptor stage end interrupt is
1243 * triggered. Warn and return.
1244 */
1245 return IRQ_NONE;
1246 }
1247
1248 /* Program the interrupt pointer to the next stage. */
1249 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1250 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1251 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
1252
1253 return IRQ_WAKE_THREAD;
1254}
1255
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001256static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan)
1257{
1258 struct rcar_dmac_desc *desc = chan->desc.running;
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001259 irqreturn_t ret = IRQ_WAKE_THREAD;
1260
1261 if (WARN_ON_ONCE(!desc)) {
1262 /*
Laurent Pinchartccadee92014-07-16 23:15:48 +02001263 * This should never happen, there should always be a running
1264 * descriptor when a transfer end interrupt is triggered. Warn
1265 * and return.
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001266 */
1267 return IRQ_NONE;
1268 }
1269
1270 /*
Laurent Pinchartccadee92014-07-16 23:15:48 +02001271 * The transfer end interrupt isn't generated for each chunk when using
1272 * descriptor mode. Only update the running chunk pointer in
1273 * non-descriptor mode.
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001274 */
Laurent Pinchart1ed13152014-07-19 00:05:14 +02001275 if (!desc->hwdescs.use) {
Laurent Pinchartccadee92014-07-16 23:15:48 +02001276 /*
1277 * If we haven't completed the last transfer chunk simply move
1278 * to the next one. Only wake the IRQ thread if the transfer is
1279 * cyclic.
1280 */
1281 if (!list_is_last(&desc->running->node, &desc->chunks)) {
1282 desc->running = list_next_entry(desc->running, node);
1283 if (!desc->cyclic)
1284 ret = IRQ_HANDLED;
1285 goto done;
1286 }
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001287
Laurent Pinchartccadee92014-07-16 23:15:48 +02001288 /*
1289 * We've completed the last transfer chunk. If the transfer is
1290 * cyclic, move back to the first one.
1291 */
1292 if (desc->cyclic) {
1293 desc->running =
1294 list_first_entry(&desc->chunks,
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001295 struct rcar_dmac_xfer_chunk,
1296 node);
Laurent Pinchartccadee92014-07-16 23:15:48 +02001297 goto done;
1298 }
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001299 }
1300
1301 /* The descriptor is complete, move it to the done list. */
1302 list_move_tail(&desc->node, &chan->desc.done);
1303
1304 /* Queue the next descriptor, if any. */
1305 if (!list_empty(&chan->desc.active))
1306 chan->desc.running = list_first_entry(&chan->desc.active,
1307 struct rcar_dmac_desc,
1308 node);
1309 else
1310 chan->desc.running = NULL;
1311
1312done:
1313 if (chan->desc.running)
1314 rcar_dmac_chan_start_xfer(chan);
1315
1316 return ret;
1317}
1318
1319static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
1320{
Laurent Pinchartccadee92014-07-16 23:15:48 +02001321 u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001322 struct rcar_dmac_chan *chan = dev;
1323 irqreturn_t ret = IRQ_NONE;
1324 u32 chcr;
1325
1326 spin_lock(&chan->lock);
1327
1328 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
Laurent Pinchartccadee92014-07-16 23:15:48 +02001329 if (chcr & RCAR_DMACHCR_TE)
1330 mask |= RCAR_DMACHCR_DE;
1331 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
1332
1333 if (chcr & RCAR_DMACHCR_DSE)
1334 ret |= rcar_dmac_isr_desc_stage_end(chan);
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001335
1336 if (chcr & RCAR_DMACHCR_TE)
1337 ret |= rcar_dmac_isr_transfer_end(chan);
1338
1339 spin_unlock(&chan->lock);
1340
1341 return ret;
1342}
1343
1344static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
1345{
1346 struct rcar_dmac_chan *chan = dev;
1347 struct rcar_dmac_desc *desc;
1348
1349 spin_lock_irq(&chan->lock);
1350
1351 /* For cyclic transfers notify the user after every chunk. */
1352 if (chan->desc.running && chan->desc.running->cyclic) {
1353 dma_async_tx_callback callback;
1354 void *callback_param;
1355
1356 desc = chan->desc.running;
1357 callback = desc->async_tx.callback;
1358 callback_param = desc->async_tx.callback_param;
1359
1360 if (callback) {
1361 spin_unlock_irq(&chan->lock);
1362 callback(callback_param);
1363 spin_lock_irq(&chan->lock);
1364 }
1365 }
1366
1367 /*
1368 * Call the callback function for all descriptors on the done list and
1369 * move them to the ack wait list.
1370 */
1371 while (!list_empty(&chan->desc.done)) {
1372 desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc,
1373 node);
1374 dma_cookie_complete(&desc->async_tx);
1375 list_del(&desc->node);
1376
1377 if (desc->async_tx.callback) {
1378 spin_unlock_irq(&chan->lock);
1379 /*
1380 * We own the only reference to this descriptor, we can
1381 * safely dereference it without holding the channel
1382 * lock.
1383 */
1384 desc->async_tx.callback(desc->async_tx.callback_param);
1385 spin_lock_irq(&chan->lock);
1386 }
1387
1388 list_add_tail(&desc->node, &chan->desc.wait);
1389 }
1390
Laurent Pinchartccadee92014-07-16 23:15:48 +02001391 spin_unlock_irq(&chan->lock);
1392
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001393 /* Recycle all acked descriptors. */
1394 rcar_dmac_desc_recycle_acked(chan);
1395
Laurent Pinchart87244fe2014-07-09 00:42:19 +02001396 return IRQ_HANDLED;
1397}
1398
1399static irqreturn_t rcar_dmac_isr_error(int irq, void *data)
1400{
1401 struct rcar_dmac *dmac = data;
1402
1403 if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE))
1404 return IRQ_NONE;
1405
1406 /*
1407 * An unrecoverable error occurred on an unknown channel. Halt the DMAC,
1408 * abort transfers on all channels, and reinitialize the DMAC.
1409 */
1410 rcar_dmac_stop(dmac);
1411 rcar_dmac_abort(dmac);
1412 rcar_dmac_init(dmac);
1413
1414 return IRQ_HANDLED;
1415}
1416
1417/* -----------------------------------------------------------------------------
1418 * OF xlate and channel filter
1419 */
1420
1421static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg)
1422{
1423 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1424 struct of_phandle_args *dma_spec = arg;
1425
1426 /*
1427 * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate
1428 * function knows from which device it wants to allocate a channel from,
1429 * and would be perfectly capable of selecting the channel it wants.
1430 * Forcing it to call dma_request_channel() and iterate through all
1431 * channels from all controllers is just pointless.
1432 */
1433 if (chan->device->device_config != rcar_dmac_device_config ||
1434 dma_spec->np != chan->device->dev->of_node)
1435 return false;
1436
1437 return !test_and_set_bit(dma_spec->args[0], dmac->modules);
1438}
1439
1440static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec,
1441 struct of_dma *ofdma)
1442{
1443 struct rcar_dmac_chan *rchan;
1444 struct dma_chan *chan;
1445 dma_cap_mask_t mask;
1446
1447 if (dma_spec->args_count != 1)
1448 return NULL;
1449
1450 /* Only slave DMA channels can be allocated via DT */
1451 dma_cap_zero(mask);
1452 dma_cap_set(DMA_SLAVE, mask);
1453
1454 chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec);
1455 if (!chan)
1456 return NULL;
1457
1458 rchan = to_rcar_dmac_chan(chan);
1459 rchan->mid_rid = dma_spec->args[0];
1460
1461 return chan;
1462}
1463
1464/* -----------------------------------------------------------------------------
1465 * Power management
1466 */
1467
1468#ifdef CONFIG_PM_SLEEP
1469static int rcar_dmac_sleep_suspend(struct device *dev)
1470{
1471 /*
1472 * TODO: Wait for the current transfer to complete and stop the device.
1473 */
1474 return 0;
1475}
1476
1477static int rcar_dmac_sleep_resume(struct device *dev)
1478{
1479 /* TODO: Resume transfers, if any. */
1480 return 0;
1481}
1482#endif
1483
1484#ifdef CONFIG_PM
1485static int rcar_dmac_runtime_suspend(struct device *dev)
1486{
1487 return 0;
1488}
1489
1490static int rcar_dmac_runtime_resume(struct device *dev)
1491{
1492 struct rcar_dmac *dmac = dev_get_drvdata(dev);
1493
1494 return rcar_dmac_init(dmac);
1495}
1496#endif
1497
1498static const struct dev_pm_ops rcar_dmac_pm = {
1499 SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume)
1500 SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
1501 NULL)
1502};
1503
1504/* -----------------------------------------------------------------------------
1505 * Probe and remove
1506 */
1507
1508static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
1509 struct rcar_dmac_chan *rchan,
1510 unsigned int index)
1511{
1512 struct platform_device *pdev = to_platform_device(dmac->dev);
1513 struct dma_chan *chan = &rchan->chan;
1514 char pdev_irqname[5];
1515 char *irqname;
1516 int irq;
1517 int ret;
1518
1519 rchan->index = index;
1520 rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index);
1521 rchan->mid_rid = -EINVAL;
1522
1523 spin_lock_init(&rchan->lock);
1524
1525 /* Request the channel interrupt. */
1526 sprintf(pdev_irqname, "ch%u", index);
1527 irq = platform_get_irq_byname(pdev, pdev_irqname);
1528 if (irq < 0) {
1529 dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1530 return -ENODEV;
1531 }
1532
1533 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
1534 dev_name(dmac->dev), index);
1535 if (!irqname)
1536 return -ENOMEM;
1537
1538 ret = devm_request_threaded_irq(dmac->dev, irq, rcar_dmac_isr_channel,
1539 rcar_dmac_isr_channel_thread, 0,
1540 irqname, rchan);
1541 if (ret) {
1542 dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", irq, ret);
1543 return ret;
1544 }
1545
1546 /*
1547 * Initialize the DMA engine channel and add it to the DMA engine
1548 * channels list.
1549 */
1550 chan->device = &dmac->engine;
1551 dma_cookie_init(chan);
1552
1553 list_add_tail(&chan->device_node, &dmac->engine.channels);
1554
1555 return 0;
1556}
1557
1558static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
1559{
1560 struct device_node *np = dev->of_node;
1561 int ret;
1562
1563 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
1564 if (ret < 0) {
1565 dev_err(dev, "unable to read dma-channels property\n");
1566 return ret;
1567 }
1568
1569 if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
1570 dev_err(dev, "invalid number of channels %u\n",
1571 dmac->n_channels);
1572 return -EINVAL;
1573 }
1574
1575 return 0;
1576}
1577
1578static int rcar_dmac_probe(struct platform_device *pdev)
1579{
1580 const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE |
1581 DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
1582 DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
1583 DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
1584 struct dma_device *engine;
1585 struct rcar_dmac *dmac;
1586 struct resource *mem;
1587 unsigned int i;
1588 char *irqname;
1589 int irq;
1590 int ret;
1591
1592 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
1593 if (!dmac)
1594 return -ENOMEM;
1595
1596 dmac->dev = &pdev->dev;
1597 platform_set_drvdata(pdev, dmac);
1598
1599 ret = rcar_dmac_parse_of(&pdev->dev, dmac);
1600 if (ret < 0)
1601 return ret;
1602
1603 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
1604 sizeof(*dmac->channels), GFP_KERNEL);
1605 if (!dmac->channels)
1606 return -ENOMEM;
1607
1608 /* Request resources. */
1609 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1610 dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
1611 if (IS_ERR(dmac->iomem))
1612 return PTR_ERR(dmac->iomem);
1613
1614 irq = platform_get_irq_byname(pdev, "error");
1615 if (irq < 0) {
1616 dev_err(&pdev->dev, "no error IRQ specified\n");
1617 return -ENODEV;
1618 }
1619
1620 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error",
1621 dev_name(dmac->dev));
1622 if (!irqname)
1623 return -ENOMEM;
1624
1625 ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0,
1626 irqname, dmac);
1627 if (ret) {
1628 dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
1629 irq, ret);
1630 return ret;
1631 }
1632
1633 /* Enable runtime PM and initialize the device. */
1634 pm_runtime_enable(&pdev->dev);
1635 ret = pm_runtime_get_sync(&pdev->dev);
1636 if (ret < 0) {
1637 dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
1638 return ret;
1639 }
1640
1641 ret = rcar_dmac_init(dmac);
1642 pm_runtime_put(&pdev->dev);
1643
1644 if (ret) {
1645 dev_err(&pdev->dev, "failed to reset device\n");
1646 goto error;
1647 }
1648
1649 /* Initialize the channels. */
1650 INIT_LIST_HEAD(&dmac->engine.channels);
1651
1652 for (i = 0; i < dmac->n_channels; ++i) {
1653 ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], i);
1654 if (ret < 0)
1655 goto error;
1656 }
1657
1658 /* Register the DMAC as a DMA provider for DT. */
1659 ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate,
1660 NULL);
1661 if (ret < 0)
1662 goto error;
1663
1664 /*
1665 * Register the DMA engine device.
1666 *
1667 * Default transfer size of 32 bytes requires 32-byte alignment.
1668 */
1669 engine = &dmac->engine;
1670 dma_cap_set(DMA_MEMCPY, engine->cap_mask);
1671 dma_cap_set(DMA_SLAVE, engine->cap_mask);
1672
1673 engine->dev = &pdev->dev;
1674 engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE);
1675
1676 engine->src_addr_widths = widths;
1677 engine->dst_addr_widths = widths;
1678 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1679 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1680
1681 engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources;
1682 engine->device_free_chan_resources = rcar_dmac_free_chan_resources;
1683 engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy;
1684 engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg;
1685 engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic;
1686 engine->device_config = rcar_dmac_device_config;
1687 engine->device_terminate_all = rcar_dmac_chan_terminate_all;
1688 engine->device_tx_status = rcar_dmac_tx_status;
1689 engine->device_issue_pending = rcar_dmac_issue_pending;
1690
1691 ret = dma_async_device_register(engine);
1692 if (ret < 0)
1693 goto error;
1694
1695 return 0;
1696
1697error:
1698 of_dma_controller_free(pdev->dev.of_node);
1699 pm_runtime_disable(&pdev->dev);
1700 return ret;
1701}
1702
1703static int rcar_dmac_remove(struct platform_device *pdev)
1704{
1705 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1706
1707 of_dma_controller_free(pdev->dev.of_node);
1708 dma_async_device_unregister(&dmac->engine);
1709
1710 pm_runtime_disable(&pdev->dev);
1711
1712 return 0;
1713}
1714
1715static void rcar_dmac_shutdown(struct platform_device *pdev)
1716{
1717 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1718
1719 rcar_dmac_stop(dmac);
1720}
1721
1722static const struct of_device_id rcar_dmac_of_ids[] = {
1723 { .compatible = "renesas,rcar-dmac", },
1724 { /* Sentinel */ }
1725};
1726MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids);
1727
1728static struct platform_driver rcar_dmac_driver = {
1729 .driver = {
1730 .pm = &rcar_dmac_pm,
1731 .name = "rcar-dmac",
1732 .of_match_table = rcar_dmac_of_ids,
1733 },
1734 .probe = rcar_dmac_probe,
1735 .remove = rcar_dmac_remove,
1736 .shutdown = rcar_dmac_shutdown,
1737};
1738
1739module_platform_driver(rcar_dmac_driver);
1740
1741MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver");
1742MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1743MODULE_LICENSE("GPL v2");