Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2010-2016, 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include "mdss_hdmi_util.h" |
| 19 | |
| 20 | #define RESOLUTION_NAME_STR_LEN 30 |
| 21 | #define HDMI_SEC_TO_MS 1000 |
| 22 | #define HDMI_MS_TO_US 1000 |
| 23 | #define HDMI_SEC_TO_US (HDMI_SEC_TO_MS * HDMI_MS_TO_US) |
| 24 | #define HDMI_KHZ_TO_HZ 1000 |
| 25 | #define HDMI_BUSY_WAIT_DELAY_US 100 |
| 26 | |
| 27 | #define HDMI_SCDC_UNKNOWN_REGISTER "Unknown register" |
| 28 | |
| 29 | static char res_buf[RESOLUTION_NAME_STR_LEN]; |
| 30 | |
| 31 | enum trigger_mode { |
| 32 | TRIGGER_WRITE, |
| 33 | TRIGGER_READ |
| 34 | }; |
| 35 | |
| 36 | int hdmi_utils_get_timeout_in_hysnc(struct msm_hdmi_mode_timing_info *timing, |
| 37 | u32 timeout_ms) |
| 38 | { |
| 39 | u32 fps, v_total; |
| 40 | u32 time_taken_by_one_line_us, lines_needed_for_given_time; |
| 41 | |
| 42 | if (!timing || !timeout_ms) { |
| 43 | pr_err("invalid input\n"); |
| 44 | return -EINVAL; |
| 45 | } |
| 46 | |
| 47 | fps = timing->refresh_rate / HDMI_KHZ_TO_HZ; |
| 48 | v_total = hdmi_tx_get_v_total(timing); |
| 49 | |
| 50 | /* |
| 51 | * pixel clock = h_total * v_total * fps |
| 52 | * 1 sec = pixel clock number of pixels are transmitted. |
| 53 | * time taken by one line (h_total) = 1 / (v_total * fps). |
| 54 | */ |
| 55 | time_taken_by_one_line_us = HDMI_SEC_TO_US / (v_total * fps); |
| 56 | lines_needed_for_given_time = (timeout_ms * HDMI_MS_TO_US) / |
| 57 | time_taken_by_one_line_us; |
| 58 | |
| 59 | return lines_needed_for_given_time; |
| 60 | } |
| 61 | |
| 62 | static int hdmi_ddc_clear_irq(struct hdmi_tx_ddc_ctrl *ddc_ctrl, |
| 63 | char *what) |
| 64 | { |
| 65 | u32 ddc_int_ctrl, ddc_status, in_use, timeout; |
| 66 | u32 sw_done_mask = BIT(2); |
| 67 | u32 sw_done_ack = BIT(1); |
| 68 | u32 in_use_by_sw = BIT(0); |
| 69 | u32 in_use_by_hw = BIT(1); |
| 70 | |
| 71 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 72 | pr_err("invalid input\n"); |
| 73 | return -EINVAL; |
| 74 | } |
| 75 | |
| 76 | /* clear and enable interrutps */ |
| 77 | ddc_int_ctrl = sw_done_mask | sw_done_ack; |
| 78 | |
| 79 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, ddc_int_ctrl); |
| 80 | |
| 81 | /* wait until DDC HW is free */ |
| 82 | timeout = 100; |
| 83 | do { |
| 84 | ddc_status = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_HW_STATUS); |
| 85 | in_use = ddc_status & (in_use_by_sw | in_use_by_hw); |
| 86 | if (in_use) { |
| 87 | pr_debug("ddc is in use by %s, timeout(%d)\n", |
| 88 | ddc_status & in_use_by_sw ? "sw" : "hw", |
| 89 | timeout); |
| 90 | udelay(100); |
| 91 | } |
| 92 | } while (in_use && --timeout); |
| 93 | |
| 94 | if (!timeout) { |
| 95 | pr_err("%s: timedout\n", what); |
| 96 | return -ETIMEDOUT; |
| 97 | } |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | static void hdmi_scrambler_ddc_reset(struct hdmi_tx_ddc_ctrl *ctrl) |
| 103 | { |
| 104 | u32 reg_val; |
| 105 | |
| 106 | if (!ctrl) { |
| 107 | pr_err("Invalid parameters\n"); |
| 108 | return; |
| 109 | } |
| 110 | |
| 111 | /* clear ack and disable interrupts */ |
| 112 | reg_val = BIT(14) | BIT(9) | BIT(5) | BIT(1); |
| 113 | DSS_REG_W(ctrl->io, HDMI_DDC_INT_CTRL2, reg_val); |
| 114 | |
| 115 | /* Reset DDC timers */ |
| 116 | reg_val = BIT(0) | DSS_REG_R(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_CTRL); |
| 117 | DSS_REG_W(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_CTRL, reg_val); |
| 118 | |
| 119 | reg_val = DSS_REG_R(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_CTRL); |
| 120 | reg_val &= ~BIT(0); |
| 121 | DSS_REG_W(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_CTRL, reg_val); |
| 122 | } |
| 123 | |
| 124 | void hdmi_scrambler_ddc_disable(struct hdmi_tx_ddc_ctrl *ctrl) |
| 125 | { |
| 126 | u32 reg_val; |
| 127 | |
| 128 | if (!ctrl) { |
| 129 | pr_err("Invalid parameters\n"); |
| 130 | return; |
| 131 | } |
| 132 | |
| 133 | hdmi_scrambler_ddc_reset(ctrl); |
| 134 | |
| 135 | /* Disable HW DDC access to RxStatus register */ |
| 136 | reg_val = DSS_REG_R(ctrl->io, HDMI_HW_DDC_CTRL); |
| 137 | reg_val &= ~(BIT(8) | BIT(9)); |
| 138 | |
| 139 | DSS_REG_W(ctrl->io, HDMI_HW_DDC_CTRL, reg_val); |
| 140 | } |
| 141 | |
| 142 | static int hdmi_scrambler_ddc_check_status(struct hdmi_tx_ddc_ctrl *ctrl) |
| 143 | { |
| 144 | int rc = 0; |
| 145 | u32 reg_val; |
| 146 | |
| 147 | if (!ctrl) { |
| 148 | pr_err("invalid ddc ctrl\n"); |
| 149 | return -EINVAL; |
| 150 | } |
| 151 | |
| 152 | /* check for errors and clear status */ |
| 153 | reg_val = DSS_REG_R(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_STATUS); |
| 154 | |
| 155 | if (reg_val & BIT(4)) { |
| 156 | pr_err("ddc aborted\n"); |
| 157 | reg_val |= BIT(5); |
| 158 | rc = -ECONNABORTED; |
| 159 | } |
| 160 | |
| 161 | if (reg_val & BIT(8)) { |
| 162 | pr_err("timed out\n"); |
| 163 | reg_val |= BIT(9); |
| 164 | rc = -ETIMEDOUT; |
| 165 | } |
| 166 | |
| 167 | if (reg_val & BIT(12)) { |
| 168 | pr_err("NACK0\n"); |
| 169 | reg_val |= BIT(13); |
| 170 | rc = -EIO; |
| 171 | } |
| 172 | |
| 173 | if (reg_val & BIT(14)) { |
| 174 | pr_err("NACK1\n"); |
| 175 | reg_val |= BIT(15); |
| 176 | rc = -EIO; |
| 177 | } |
| 178 | |
| 179 | DSS_REG_W(ctrl->io, HDMI_SCRAMBLER_STATUS_DDC_STATUS, reg_val); |
| 180 | |
| 181 | return rc; |
| 182 | } |
| 183 | |
| 184 | static int hdmi_scrambler_status_timer_setup(struct hdmi_tx_ddc_ctrl *ctrl, |
| 185 | u32 timeout_hsync) |
| 186 | { |
| 187 | u32 reg_val; |
| 188 | int rc; |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 189 | struct mdss_io_data *io = NULL; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 190 | |
| 191 | if (!ctrl || !ctrl->io) { |
| 192 | pr_err("invalid input\n"); |
| 193 | return -EINVAL; |
| 194 | } |
| 195 | |
| 196 | io = ctrl->io; |
| 197 | |
| 198 | hdmi_ddc_clear_irq(ctrl, "scrambler"); |
| 199 | |
| 200 | DSS_REG_W(io, HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL, timeout_hsync); |
| 201 | DSS_REG_W(io, HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL2, timeout_hsync); |
| 202 | |
| 203 | reg_val = DSS_REG_R(io, HDMI_DDC_INT_CTRL5); |
| 204 | reg_val |= BIT(10); |
| 205 | DSS_REG_W(io, HDMI_DDC_INT_CTRL5, reg_val); |
| 206 | |
| 207 | reg_val = DSS_REG_R(io, HDMI_DDC_INT_CTRL2); |
| 208 | /* Trigger interrupt if scrambler status is 0 or DDC failure */ |
| 209 | reg_val |= BIT(10); |
| 210 | reg_val &= ~(BIT(15) | BIT(16)); |
| 211 | reg_val |= BIT(16); |
| 212 | DSS_REG_W(io, HDMI_DDC_INT_CTRL2, reg_val); |
| 213 | |
| 214 | /* Enable DDC access */ |
| 215 | reg_val = DSS_REG_R(io, HDMI_HW_DDC_CTRL); |
| 216 | |
| 217 | reg_val &= ~(BIT(8) | BIT(9)); |
| 218 | reg_val |= BIT(8); |
| 219 | DSS_REG_W(io, HDMI_HW_DDC_CTRL, reg_val); |
| 220 | |
| 221 | /* WAIT for 200ms as per HDMI 2.0 standard for sink to respond */ |
| 222 | msleep(200); |
| 223 | |
| 224 | /* clear the scrambler status */ |
| 225 | rc = hdmi_scrambler_ddc_check_status(ctrl); |
| 226 | if (rc) |
| 227 | pr_err("scrambling ddc error %d\n", rc); |
| 228 | |
| 229 | hdmi_scrambler_ddc_disable(ctrl); |
| 230 | |
| 231 | return rc; |
| 232 | } |
| 233 | |
| 234 | static inline char *hdmi_scdc_reg2string(u32 type) |
| 235 | { |
| 236 | switch (type) { |
| 237 | case HDMI_TX_SCDC_SCRAMBLING_STATUS: |
| 238 | return "HDMI_TX_SCDC_SCRAMBLING_STATUS"; |
| 239 | case HDMI_TX_SCDC_SCRAMBLING_ENABLE: |
| 240 | return "HDMI_TX_SCDC_SCRAMBLING_ENABLE"; |
| 241 | case HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE: |
| 242 | return "HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE"; |
| 243 | case HDMI_TX_SCDC_CLOCK_DET_STATUS: |
| 244 | return "HDMI_TX_SCDC_CLOCK_DET_STATUS"; |
| 245 | case HDMI_TX_SCDC_CH0_LOCK_STATUS: |
| 246 | return "HDMI_TX_SCDC_CH0_LOCK_STATUS"; |
| 247 | case HDMI_TX_SCDC_CH1_LOCK_STATUS: |
| 248 | return "HDMI_TX_SCDC_CH1_LOCK_STATUS"; |
| 249 | case HDMI_TX_SCDC_CH2_LOCK_STATUS: |
| 250 | return "HDMI_TX_SCDC_CH2_LOCK_STATUS"; |
| 251 | case HDMI_TX_SCDC_CH0_ERROR_COUNT: |
| 252 | return "HDMI_TX_SCDC_CH0_ERROR_COUNT"; |
| 253 | case HDMI_TX_SCDC_CH1_ERROR_COUNT: |
| 254 | return "HDMI_TX_SCDC_CH1_ERROR_COUNT"; |
| 255 | case HDMI_TX_SCDC_CH2_ERROR_COUNT: |
| 256 | return "HDMI_TX_SCDC_CH2_ERROR_COUNT"; |
| 257 | case HDMI_TX_SCDC_READ_ENABLE: |
| 258 | return"HDMI_TX_SCDC_READ_ENABLE"; |
| 259 | default: |
| 260 | return HDMI_SCDC_UNKNOWN_REGISTER; |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | static struct msm_hdmi_mode_timing_info hdmi_resv_timings[ |
| 265 | RESERVE_VFRMT_END - HDMI_VFRMT_RESERVE1 + 1]; |
| 266 | |
| 267 | static int hdmi_get_resv_timing_info( |
| 268 | struct msm_hdmi_mode_timing_info *mode, int id) |
| 269 | { |
| 270 | int i; |
| 271 | |
| 272 | for (i = 0; i < ARRAY_SIZE(hdmi_resv_timings); i++) { |
| 273 | struct msm_hdmi_mode_timing_info *info = &hdmi_resv_timings[i]; |
| 274 | |
| 275 | if (info->video_format == id) { |
| 276 | *mode = *info; |
| 277 | return 0; |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | return -EINVAL; |
| 282 | } |
| 283 | |
| 284 | int hdmi_set_resv_timing_info(struct msm_hdmi_mode_timing_info *mode) |
| 285 | { |
| 286 | int i; |
| 287 | |
| 288 | for (i = 0; i < ARRAY_SIZE(hdmi_resv_timings); i++) { |
| 289 | struct msm_hdmi_mode_timing_info *info = &hdmi_resv_timings[i]; |
| 290 | |
| 291 | if (info->video_format == 0) { |
| 292 | *info = *mode; |
| 293 | info->video_format = HDMI_VFRMT_RESERVE1 + i; |
| 294 | return info->video_format; |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | return -ENOMEM; |
| 299 | } |
| 300 | |
| 301 | bool hdmi_is_valid_resv_timing(int mode) |
| 302 | { |
| 303 | struct msm_hdmi_mode_timing_info *info; |
| 304 | |
| 305 | if (mode < HDMI_VFRMT_RESERVE1 || mode > RESERVE_VFRMT_END) { |
| 306 | pr_err("invalid mode %d\n", mode); |
| 307 | return false; |
| 308 | } |
| 309 | |
| 310 | info = &hdmi_resv_timings[mode - HDMI_VFRMT_RESERVE1]; |
| 311 | |
| 312 | return info->video_format >= HDMI_VFRMT_RESERVE1 && |
| 313 | info->video_format <= RESERVE_VFRMT_END; |
| 314 | } |
| 315 | |
| 316 | void hdmi_reset_resv_timing_info(void) |
| 317 | { |
| 318 | int i; |
| 319 | |
| 320 | for (i = 0; i < ARRAY_SIZE(hdmi_resv_timings); i++) { |
| 321 | struct msm_hdmi_mode_timing_info *info = &hdmi_resv_timings[i]; |
| 322 | |
| 323 | info->video_format = 0; |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | int msm_hdmi_get_timing_info( |
| 328 | struct msm_hdmi_mode_timing_info *mode, int id) |
| 329 | { |
| 330 | int ret = 0; |
| 331 | |
| 332 | switch (id) { |
| 333 | case HDMI_VFRMT_640x480p60_4_3: |
| 334 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_640x480p60_4_3); |
| 335 | break; |
| 336 | case HDMI_VFRMT_720x480p60_4_3: |
| 337 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_720x480p60_4_3); |
| 338 | break; |
| 339 | case HDMI_VFRMT_720x480p60_16_9: |
| 340 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_720x480p60_16_9); |
| 341 | break; |
| 342 | case HDMI_VFRMT_1280x720p60_16_9: |
| 343 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x720p60_16_9); |
| 344 | break; |
| 345 | case HDMI_VFRMT_1920x1080i60_16_9: |
| 346 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080i60_16_9); |
| 347 | break; |
| 348 | case HDMI_VFRMT_1440x480i60_4_3: |
| 349 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1440x480i60_4_3); |
| 350 | break; |
| 351 | case HDMI_VFRMT_1440x480i60_16_9: |
| 352 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1440x480i60_16_9); |
| 353 | break; |
| 354 | case HDMI_VFRMT_1920x1080p60_16_9: |
| 355 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p60_16_9); |
| 356 | break; |
| 357 | case HDMI_VFRMT_720x576p50_4_3: |
| 358 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_720x576p50_4_3); |
| 359 | break; |
| 360 | case HDMI_VFRMT_720x576p50_16_9: |
| 361 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_720x576p50_16_9); |
| 362 | break; |
| 363 | case HDMI_VFRMT_1280x720p50_16_9: |
| 364 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x720p50_16_9); |
| 365 | break; |
| 366 | case HDMI_VFRMT_1440x576i50_4_3: |
| 367 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1440x576i50_4_3); |
| 368 | break; |
| 369 | case HDMI_VFRMT_1440x576i50_16_9: |
| 370 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1440x576i50_16_9); |
| 371 | break; |
| 372 | case HDMI_VFRMT_1920x1080p50_16_9: |
| 373 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p50_16_9); |
| 374 | break; |
| 375 | case HDMI_VFRMT_1920x1080p24_16_9: |
| 376 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p24_16_9); |
| 377 | break; |
| 378 | case HDMI_VFRMT_1920x1080p25_16_9: |
| 379 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p25_16_9); |
| 380 | break; |
| 381 | case HDMI_VFRMT_1920x1080p30_16_9: |
| 382 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p30_16_9); |
| 383 | break; |
| 384 | case HDMI_EVFRMT_3840x2160p30_16_9: |
| 385 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p30_16_9); |
| 386 | break; |
| 387 | case HDMI_EVFRMT_3840x2160p25_16_9: |
| 388 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p25_16_9); |
| 389 | break; |
| 390 | case HDMI_EVFRMT_3840x2160p24_16_9: |
| 391 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p24_16_9); |
| 392 | break; |
| 393 | case HDMI_EVFRMT_4096x2160p24_16_9: |
| 394 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_4096x2160p24_16_9); |
| 395 | break; |
| 396 | case HDMI_VFRMT_1024x768p60_4_3: |
| 397 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1024x768p60_4_3); |
| 398 | break; |
| 399 | case HDMI_VFRMT_1280x1024p60_5_4: |
| 400 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x1024p60_5_4); |
| 401 | break; |
| 402 | case HDMI_VFRMT_2560x1600p60_16_9: |
| 403 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_2560x1600p60_16_9); |
| 404 | break; |
| 405 | case HDMI_VFRMT_800x600p60_4_3: |
| 406 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_800x600p60_4_3); |
| 407 | break; |
| 408 | case HDMI_VFRMT_848x480p60_16_9: |
| 409 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_848x480p60_16_9); |
| 410 | break; |
| 411 | case HDMI_VFRMT_1280x960p60_4_3: |
| 412 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x960p60_4_3); |
| 413 | break; |
| 414 | case HDMI_VFRMT_1360x768p60_16_9: |
| 415 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1360x768p60_16_9); |
| 416 | break; |
| 417 | case HDMI_VFRMT_1440x900p60_16_10: |
| 418 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1440x900p60_16_10); |
| 419 | break; |
| 420 | case HDMI_VFRMT_1400x1050p60_4_3: |
| 421 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1400x1050p60_4_3); |
| 422 | break; |
| 423 | case HDMI_VFRMT_1680x1050p60_16_10: |
| 424 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1680x1050p60_16_10); |
| 425 | break; |
| 426 | case HDMI_VFRMT_1600x1200p60_4_3: |
| 427 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1600x1200p60_4_3); |
| 428 | break; |
| 429 | case HDMI_VFRMT_1920x1200p60_16_10: |
| 430 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1200p60_16_10); |
| 431 | break; |
| 432 | case HDMI_VFRMT_1366x768p60_16_10: |
| 433 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1366x768p60_16_10); |
| 434 | break; |
| 435 | case HDMI_VFRMT_1280x800p60_16_10: |
| 436 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x800p60_16_10); |
| 437 | break; |
| 438 | case HDMI_VFRMT_3840x2160p24_16_9: |
| 439 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p24_16_9); |
| 440 | break; |
| 441 | case HDMI_VFRMT_3840x2160p25_16_9: |
| 442 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p25_16_9); |
| 443 | break; |
| 444 | case HDMI_VFRMT_3840x2160p30_16_9: |
| 445 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p30_16_9); |
| 446 | break; |
| 447 | case HDMI_VFRMT_3840x2160p50_16_9: |
| 448 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p50_16_9); |
| 449 | break; |
| 450 | case HDMI_VFRMT_3840x2160p60_16_9: |
| 451 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p60_16_9); |
| 452 | break; |
| 453 | case HDMI_VFRMT_4096x2160p24_256_135: |
| 454 | MSM_HDMI_MODES_GET_DETAILS(mode, |
| 455 | HDMI_VFRMT_4096x2160p24_256_135); |
| 456 | break; |
| 457 | case HDMI_VFRMT_4096x2160p25_256_135: |
| 458 | MSM_HDMI_MODES_GET_DETAILS(mode, |
| 459 | HDMI_VFRMT_4096x2160p25_256_135); |
| 460 | break; |
| 461 | case HDMI_VFRMT_4096x2160p30_256_135: |
| 462 | MSM_HDMI_MODES_GET_DETAILS(mode, |
| 463 | HDMI_VFRMT_4096x2160p30_256_135); |
| 464 | break; |
| 465 | case HDMI_VFRMT_4096x2160p50_256_135: |
| 466 | MSM_HDMI_MODES_GET_DETAILS(mode, |
| 467 | HDMI_VFRMT_4096x2160p50_256_135); |
| 468 | break; |
| 469 | case HDMI_VFRMT_4096x2160p60_256_135: |
| 470 | MSM_HDMI_MODES_GET_DETAILS(mode, |
| 471 | HDMI_VFRMT_4096x2160p60_256_135); |
| 472 | break; |
| 473 | case HDMI_VFRMT_3840x2160p24_64_27: |
| 474 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p24_64_27); |
| 475 | break; |
| 476 | case HDMI_VFRMT_3840x2160p25_64_27: |
| 477 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p25_64_27); |
| 478 | break; |
| 479 | case HDMI_VFRMT_3840x2160p30_64_27: |
| 480 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p30_64_27); |
| 481 | break; |
| 482 | case HDMI_VFRMT_3840x2160p50_64_27: |
| 483 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p50_64_27); |
| 484 | break; |
| 485 | case HDMI_VFRMT_3840x2160p60_64_27: |
| 486 | MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p60_64_27); |
| 487 | break; |
| 488 | default: |
| 489 | ret = hdmi_get_resv_timing_info(mode, id); |
| 490 | } |
| 491 | |
| 492 | return ret; |
| 493 | } |
| 494 | |
| 495 | int hdmi_get_supported_mode(struct msm_hdmi_mode_timing_info *info, |
| 496 | struct hdmi_util_ds_data *ds_data, u32 mode) |
| 497 | { |
| 498 | int ret; |
| 499 | |
| 500 | if (!info) |
| 501 | return -EINVAL; |
| 502 | |
| 503 | if (mode >= HDMI_VFRMT_MAX) |
| 504 | return -EINVAL; |
| 505 | |
| 506 | ret = msm_hdmi_get_timing_info(info, mode); |
| 507 | |
| 508 | if (!ret && ds_data && ds_data->ds_registered && ds_data->ds_max_clk) { |
| 509 | if (info->pixel_freq > ds_data->ds_max_clk) |
| 510 | info->supported = false; |
| 511 | } |
| 512 | |
| 513 | return ret; |
| 514 | } /* hdmi_get_supported_mode */ |
| 515 | |
| 516 | const char *msm_hdmi_mode_2string(u32 mode) |
| 517 | { |
| 518 | static struct msm_hdmi_mode_timing_info ri = {0}; |
| 519 | char *aspect_ratio; |
| 520 | |
| 521 | if (mode >= HDMI_VFRMT_MAX) |
| 522 | return "???"; |
| 523 | |
| 524 | if (hdmi_get_supported_mode(&ri, NULL, mode)) |
| 525 | return "???"; |
| 526 | |
| 527 | memset(res_buf, 0, sizeof(res_buf)); |
| 528 | |
| 529 | if (!ri.supported) { |
| 530 | snprintf(res_buf, RESOLUTION_NAME_STR_LEN, "%d", mode); |
| 531 | return res_buf; |
| 532 | } |
| 533 | |
| 534 | switch (ri.ar) { |
| 535 | case HDMI_RES_AR_4_3: |
| 536 | aspect_ratio = "4/3"; |
| 537 | break; |
| 538 | case HDMI_RES_AR_5_4: |
| 539 | aspect_ratio = "5/4"; |
| 540 | break; |
| 541 | case HDMI_RES_AR_16_9: |
| 542 | aspect_ratio = "16/9"; |
| 543 | break; |
| 544 | case HDMI_RES_AR_16_10: |
| 545 | aspect_ratio = "16/10"; |
| 546 | break; |
| 547 | default: |
| 548 | aspect_ratio = "???"; |
| 549 | }; |
| 550 | |
| 551 | snprintf(res_buf, RESOLUTION_NAME_STR_LEN, "%dx%d %s%dHz %s", |
| 552 | ri.active_h, ri.active_v, ri.interlaced ? "i" : "p", |
| 553 | ri.refresh_rate / 1000, aspect_ratio); |
| 554 | |
| 555 | return res_buf; |
| 556 | } |
| 557 | |
| 558 | int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in, |
| 559 | struct hdmi_util_ds_data *ds_data) |
| 560 | { |
| 561 | int i, vic = -1; |
| 562 | struct msm_hdmi_mode_timing_info supported_timing = {0}; |
| 563 | u32 ret; |
| 564 | |
| 565 | if (!timing_in) { |
| 566 | pr_err("invalid input\n"); |
| 567 | goto exit; |
| 568 | } |
| 569 | |
| 570 | /* active_low_h, active_low_v and interlaced are not checked against */ |
| 571 | for (i = 0; i < HDMI_VFRMT_MAX; i++) { |
| 572 | ret = hdmi_get_supported_mode(&supported_timing, ds_data, i); |
| 573 | |
| 574 | if (ret || !supported_timing.supported) |
| 575 | continue; |
| 576 | if (timing_in->active_h != supported_timing.active_h) |
| 577 | continue; |
| 578 | if (timing_in->front_porch_h != supported_timing.front_porch_h) |
| 579 | continue; |
| 580 | if (timing_in->pulse_width_h != supported_timing.pulse_width_h) |
| 581 | continue; |
| 582 | if (timing_in->back_porch_h != supported_timing.back_porch_h) |
| 583 | continue; |
| 584 | if (timing_in->active_v != supported_timing.active_v) |
| 585 | continue; |
| 586 | if (timing_in->front_porch_v != supported_timing.front_porch_v) |
| 587 | continue; |
| 588 | if (timing_in->pulse_width_v != supported_timing.pulse_width_v) |
| 589 | continue; |
| 590 | if (timing_in->back_porch_v != supported_timing.back_porch_v) |
| 591 | continue; |
| 592 | if (timing_in->pixel_freq != supported_timing.pixel_freq) |
| 593 | continue; |
| 594 | if (timing_in->refresh_rate != supported_timing.refresh_rate) |
| 595 | continue; |
| 596 | |
| 597 | vic = (int)supported_timing.video_format; |
| 598 | break; |
| 599 | } |
| 600 | |
| 601 | if (vic < 0) |
| 602 | pr_err("timing is not supported h=%d v=%d\n", |
| 603 | timing_in->active_h, timing_in->active_v); |
| 604 | else |
| 605 | pr_debug("vic = %d timing = %s\n", vic, |
| 606 | msm_hdmi_mode_2string((u32)vic)); |
| 607 | exit: |
| 608 | |
| 609 | return vic; |
| 610 | } /* hdmi_get_video_id_code */ |
| 611 | |
| 612 | static const char *hdmi_get_single_video_3d_fmt_2string(u32 format) |
| 613 | { |
| 614 | switch (format) { |
| 615 | case TOP_AND_BOTTOM: return "TAB"; |
| 616 | case FRAME_PACKING: return "FP"; |
| 617 | case SIDE_BY_SIDE_HALF: return "SSH"; |
| 618 | } |
| 619 | return ""; |
| 620 | } /* hdmi_get_single_video_3d_fmt_2string */ |
| 621 | |
| 622 | ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size) |
| 623 | { |
| 624 | ssize_t ret, len = 0; |
| 625 | |
| 626 | ret = scnprintf(buf, size, "%s", |
| 627 | hdmi_get_single_video_3d_fmt_2string( |
| 628 | format & FRAME_PACKING)); |
| 629 | len += ret; |
| 630 | |
| 631 | if (len && (format & TOP_AND_BOTTOM)) |
| 632 | ret = scnprintf(buf + len, size - len, ":%s", |
| 633 | hdmi_get_single_video_3d_fmt_2string( |
| 634 | format & TOP_AND_BOTTOM)); |
| 635 | else |
| 636 | ret = scnprintf(buf + len, size - len, "%s", |
| 637 | hdmi_get_single_video_3d_fmt_2string( |
| 638 | format & TOP_AND_BOTTOM)); |
| 639 | len += ret; |
| 640 | |
| 641 | if (len && (format & SIDE_BY_SIDE_HALF)) |
| 642 | ret = scnprintf(buf + len, size - len, ":%s", |
| 643 | hdmi_get_single_video_3d_fmt_2string( |
| 644 | format & SIDE_BY_SIDE_HALF)); |
| 645 | else |
| 646 | ret = scnprintf(buf + len, size - len, "%s", |
| 647 | hdmi_get_single_video_3d_fmt_2string( |
| 648 | format & SIDE_BY_SIDE_HALF)); |
| 649 | len += ret; |
| 650 | |
| 651 | return len; |
| 652 | } /* hdmi_get_video_3d_fmt_2string */ |
| 653 | |
| 654 | static void hdmi_ddc_trigger(struct hdmi_tx_ddc_ctrl *ddc_ctrl, |
| 655 | enum trigger_mode mode, bool seg) |
| 656 | { |
| 657 | struct hdmi_tx_ddc_data *ddc_data = &ddc_ctrl->ddc_data; |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 658 | struct mdss_io_data *io = ddc_ctrl->io; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 659 | u32 const seg_addr = 0x60, seg_num = 0x01; |
| 660 | u32 ddc_ctrl_reg_val; |
| 661 | |
| 662 | ddc_data->dev_addr &= 0xFE; |
| 663 | |
| 664 | if (mode == TRIGGER_READ && seg) { |
| 665 | DSS_REG_W_ND(io, HDMI_DDC_DATA, BIT(31) | (seg_addr << 8)); |
| 666 | DSS_REG_W_ND(io, HDMI_DDC_DATA, seg_num << 8); |
| 667 | } |
| 668 | |
| 669 | /* handle portion #1 */ |
| 670 | DSS_REG_W_ND(io, HDMI_DDC_DATA, BIT(31) | (ddc_data->dev_addr << 8)); |
| 671 | |
| 672 | /* handle portion #2 */ |
| 673 | DSS_REG_W_ND(io, HDMI_DDC_DATA, ddc_data->offset << 8); |
| 674 | |
| 675 | if (mode == TRIGGER_READ) { |
| 676 | /* handle portion #3 */ |
| 677 | DSS_REG_W_ND(io, HDMI_DDC_DATA, |
| 678 | (ddc_data->dev_addr | BIT(0)) << 8); |
| 679 | |
| 680 | /* HDMI_I2C_TRANSACTION0 */ |
| 681 | DSS_REG_W_ND(io, HDMI_DDC_TRANS0, BIT(12) | BIT(16)); |
| 682 | |
| 683 | /* Write to HDMI_I2C_TRANSACTION1 */ |
| 684 | if (seg) { |
| 685 | DSS_REG_W_ND(io, HDMI_DDC_TRANS1, BIT(12) | BIT(16)); |
| 686 | DSS_REG_W_ND(io, HDMI_DDC_TRANS2, |
| 687 | BIT(0) | BIT(12) | BIT(13) | |
| 688 | (ddc_data->request_len << 16)); |
| 689 | |
| 690 | ddc_ctrl_reg_val = BIT(0) | BIT(21); |
| 691 | } else { |
| 692 | DSS_REG_W_ND(io, HDMI_DDC_TRANS1, |
| 693 | BIT(0) | BIT(12) | BIT(13) | |
| 694 | (ddc_data->request_len << 16)); |
| 695 | |
| 696 | ddc_ctrl_reg_val = BIT(0) | BIT(20); |
| 697 | } |
| 698 | } else { |
| 699 | int ndx; |
| 700 | |
| 701 | /* write buffer */ |
| 702 | for (ndx = 0; ndx < ddc_data->data_len; ++ndx) |
| 703 | DSS_REG_W_ND(io, HDMI_DDC_DATA, |
| 704 | ((u32)ddc_data->data_buf[ndx]) << 8); |
| 705 | |
| 706 | DSS_REG_W_ND(io, HDMI_DDC_TRANS0, |
| 707 | (ddc_data->data_len + 1) << 16 | BIT(12) | BIT(13)); |
| 708 | |
| 709 | ddc_ctrl_reg_val = BIT(0); |
| 710 | } |
| 711 | |
| 712 | /* Trigger the I2C transfer */ |
| 713 | DSS_REG_W_ND(io, HDMI_DDC_CTRL, ddc_ctrl_reg_val); |
| 714 | } |
| 715 | |
| 716 | static void hdmi_ddc_clear_status(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 717 | { |
| 718 | u32 reg_val; |
| 719 | |
| 720 | /* Read DDC status */ |
| 721 | reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS); |
| 722 | reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15); |
| 723 | |
| 724 | /* Check if any NACK occurred */ |
| 725 | if (reg_val) { |
| 726 | pr_debug("%s: NACK: HDMI_DDC_SW_STATUS 0x%x\n", |
| 727 | ddc_ctrl->ddc_data.what, reg_val); |
| 728 | |
| 729 | /* SW_STATUS_RESET, SOFT_RESET */ |
| 730 | reg_val = BIT(3) | BIT(1); |
| 731 | |
| 732 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, reg_val); |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | static int hdmi_ddc_read_retry(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 737 | { |
| 738 | u32 reg_val, ndx, time_out_count, wait_time; |
| 739 | struct hdmi_tx_ddc_data *ddc_data; |
| 740 | int status; |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 741 | int busy_wait_us = 0; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 742 | |
| 743 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 744 | pr_err("invalid input\n"); |
| 745 | return -EINVAL; |
| 746 | } |
| 747 | |
| 748 | ddc_data = &ddc_ctrl->ddc_data; |
| 749 | |
| 750 | if (!ddc_data->data_buf) { |
| 751 | status = -EINVAL; |
| 752 | pr_err("%s: invalid buf\n", ddc_data->what); |
| 753 | goto error; |
| 754 | } |
| 755 | |
| 756 | if (ddc_data->retry < 0) { |
| 757 | pr_err("invalid no. of retries %d\n", ddc_data->retry); |
| 758 | status = -EINVAL; |
| 759 | goto error; |
| 760 | } |
| 761 | |
| 762 | do { |
| 763 | status = hdmi_ddc_clear_irq(ddc_ctrl, ddc_data->what); |
| 764 | if (status) |
| 765 | continue; |
| 766 | |
| 767 | if (ddc_data->hard_timeout) { |
| 768 | pr_debug("using hard_timeout %dms\n", |
| 769 | ddc_data->hard_timeout); |
| 770 | |
| 771 | busy_wait_us = ddc_data->hard_timeout * HDMI_MS_TO_US; |
| 772 | atomic_set(&ddc_ctrl->read_busy_wait_done, 0); |
| 773 | } else { |
| 774 | reinit_completion(&ddc_ctrl->ddc_sw_done); |
| 775 | wait_time = HZ / 2; |
| 776 | } |
| 777 | |
| 778 | hdmi_ddc_trigger(ddc_ctrl, TRIGGER_READ, false); |
| 779 | |
| 780 | if (ddc_data->hard_timeout) { |
| 781 | while (busy_wait_us > 0 && |
| 782 | !atomic_read(&ddc_ctrl->read_busy_wait_done)) { |
| 783 | udelay(HDMI_BUSY_WAIT_DELAY_US); |
| 784 | busy_wait_us -= HDMI_BUSY_WAIT_DELAY_US; |
| 785 | }; |
| 786 | |
| 787 | if (busy_wait_us < 0) |
| 788 | busy_wait_us = 0; |
| 789 | |
| 790 | time_out_count = busy_wait_us / HDMI_MS_TO_US; |
| 791 | |
| 792 | ddc_data->timeout_left = time_out_count; |
| 793 | } else { |
| 794 | time_out_count = wait_for_completion_timeout( |
| 795 | &ddc_ctrl->ddc_sw_done, wait_time); |
| 796 | |
| 797 | ddc_data->timeout_left = |
| 798 | jiffies_to_msecs(time_out_count); |
| 799 | } |
| 800 | |
| 801 | pr_debug("ddc read done at %dms\n", jiffies_to_msecs(jiffies)); |
| 802 | |
| 803 | if (!time_out_count) { |
| 804 | pr_debug("%s: timedout\n", ddc_data->what); |
| 805 | |
| 806 | status = -ETIMEDOUT; |
| 807 | } |
| 808 | |
| 809 | hdmi_ddc_clear_status(ddc_ctrl); |
| 810 | } while (status && ddc_data->retry--); |
| 811 | |
| 812 | if (status) |
| 813 | goto error; |
| 814 | |
| 815 | /* Write data to DDC buffer */ |
| 816 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, |
| 817 | BIT(0) | (3 << 16) | BIT(31)); |
| 818 | |
| 819 | /* Discard first byte */ |
| 820 | DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA); |
| 821 | for (ndx = 0; ndx < ddc_data->data_len; ++ndx) { |
| 822 | reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA); |
| 823 | ddc_data->data_buf[ndx] = (u8)((reg_val & 0x0000FF00) >> 8); |
| 824 | } |
| 825 | |
| 826 | pr_debug("%s: success\n", ddc_data->what); |
| 827 | |
| 828 | error: |
| 829 | return status; |
| 830 | } /* hdmi_ddc_read_retry */ |
| 831 | |
| 832 | void hdmi_ddc_config(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 833 | { |
| 834 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 835 | pr_err("invalid input\n"); |
| 836 | return; |
| 837 | } |
| 838 | |
| 839 | /* Configure Pre-Scale multiplier & Threshold */ |
| 840 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SPEED, (10 << 16) | (2 << 0)); |
| 841 | |
| 842 | /* |
| 843 | * Setting 31:24 bits : Time units to wait before timeout |
| 844 | * when clock is being stalled by external sink device |
| 845 | */ |
| 846 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SETUP, 0xFF000000); |
| 847 | |
| 848 | /* Enable reference timer to 19 micro-seconds */ |
| 849 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_REF, (1 << 16) | (19 << 0)); |
| 850 | } /* hdmi_ddc_config */ |
| 851 | |
| 852 | static void hdmi_hdcp2p2_ddc_clear_status(struct hdmi_tx_ddc_ctrl *ctrl) |
| 853 | { |
| 854 | u32 reg_val; |
| 855 | |
| 856 | if (!ctrl) { |
| 857 | pr_err("invalid ddc ctrl\n"); |
| 858 | return; |
| 859 | } |
| 860 | |
| 861 | /* check for errors and clear status */ |
| 862 | reg_val = DSS_REG_R(ctrl->io, HDMI_HDCP2P2_DDC_STATUS); |
| 863 | |
| 864 | if (reg_val & BIT(4)) { |
| 865 | pr_debug("ddc aborted\n"); |
| 866 | reg_val |= BIT(5); |
| 867 | } |
| 868 | |
| 869 | if (reg_val & BIT(8)) { |
| 870 | pr_debug("timed out\n"); |
| 871 | reg_val |= BIT(9); |
| 872 | } |
| 873 | |
| 874 | if (reg_val & BIT(12)) { |
| 875 | pr_debug("NACK0\n"); |
| 876 | reg_val |= BIT(13); |
| 877 | } |
| 878 | |
| 879 | if (reg_val & BIT(14)) { |
| 880 | pr_debug("NACK1\n"); |
| 881 | reg_val |= BIT(15); |
| 882 | } |
| 883 | |
| 884 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_STATUS, reg_val); |
| 885 | } |
| 886 | |
| 887 | static int hdmi_ddc_hdcp2p2_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 888 | { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 889 | struct mdss_io_data *io = NULL; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 890 | struct hdmi_tx_hdcp2p2_ddc_data *data; |
| 891 | u32 intr0, intr2, intr5; |
| 892 | u32 msg_size; |
| 893 | int rc = 0; |
| 894 | |
| 895 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 896 | pr_err("invalid input\n"); |
| 897 | return -EINVAL; |
| 898 | } |
| 899 | |
| 900 | io = ddc_ctrl->io; |
| 901 | |
| 902 | data = &ddc_ctrl->hdcp2p2_ddc_data; |
| 903 | |
| 904 | intr0 = DSS_REG_R(io, HDMI_DDC_INT_CTRL0); |
| 905 | intr2 = DSS_REG_R(io, HDMI_HDCP_INT_CTRL2); |
| 906 | intr5 = DSS_REG_R_ND(io, HDMI_DDC_INT_CTRL5); |
| 907 | |
| 908 | pr_debug("intr0: 0x%x, intr2: 0x%x, intr5: 0x%x\n", |
| 909 | intr0, intr2, intr5); |
| 910 | |
| 911 | /* check if encryption is enabled */ |
| 912 | if (intr2 & BIT(0)) { |
| 913 | /* |
| 914 | * ack encryption ready interrupt. |
| 915 | * disable encryption ready interrupt. |
| 916 | * enable encryption not ready interrupt. |
| 917 | */ |
| 918 | intr2 &= ~BIT(2); |
| 919 | intr2 |= BIT(1) | BIT(6); |
| 920 | |
| 921 | pr_debug("HDCP 2.2 Encryption enabled\n"); |
| 922 | data->encryption_ready = true; |
| 923 | } |
| 924 | |
| 925 | /* check if encryption is disabled */ |
| 926 | if (intr2 & BIT(4)) { |
| 927 | /* |
| 928 | * ack encryption not ready interrupt. |
| 929 | * disable encryption not ready interrupt. |
| 930 | * enable encryption ready interrupt. |
| 931 | */ |
| 932 | intr2 &= ~BIT(6); |
| 933 | intr2 |= BIT(5) | BIT(2); |
| 934 | |
| 935 | pr_debug("HDCP 2.2 Encryption disabled\n"); |
| 936 | data->encryption_ready = false; |
| 937 | } |
| 938 | |
| 939 | DSS_REG_W_ND(io, HDMI_HDCP_INT_CTRL2, intr2); |
| 940 | |
| 941 | /* get the message size bits 29:20 */ |
| 942 | msg_size = (intr0 & (0x3FF << 20)) >> 20; |
| 943 | |
| 944 | if (msg_size) { |
| 945 | /* ack and disable message size interrupt */ |
| 946 | intr0 |= BIT(30); |
| 947 | intr0 &= ~BIT(31); |
| 948 | |
| 949 | data->message_size = msg_size; |
| 950 | } |
| 951 | |
| 952 | /* check and disable ready interrupt */ |
| 953 | if (intr0 & BIT(16)) { |
| 954 | /* ack ready/not ready interrupt */ |
| 955 | intr0 |= BIT(17); |
| 956 | |
| 957 | intr0 &= ~BIT(18); |
| 958 | data->ready = true; |
| 959 | } |
| 960 | |
| 961 | /* check for reauth req interrupt */ |
| 962 | if (intr0 & BIT(12)) { |
| 963 | /* ack and disable reauth req interrupt */ |
| 964 | intr0 |= BIT(13); |
| 965 | intr0 &= ~BIT(14); |
| 966 | |
| 967 | data->reauth_req = true; |
| 968 | } |
| 969 | |
| 970 | /* check for ddc fail interrupt */ |
| 971 | if (intr0 & BIT(8)) { |
| 972 | /* ack ddc fail interrupt */ |
| 973 | intr0 |= BIT(9); |
| 974 | |
| 975 | data->ddc_max_retries_fail = true; |
| 976 | } |
| 977 | |
| 978 | /* check for ddc done interrupt */ |
| 979 | if (intr0 & BIT(4)) { |
| 980 | /* ack ddc done interrupt */ |
| 981 | intr0 |= BIT(5); |
| 982 | |
| 983 | data->ddc_done = true; |
| 984 | } |
| 985 | |
| 986 | /* check for ddc read req interrupt */ |
| 987 | if (intr0 & BIT(0)) { |
| 988 | /* ack read req interrupt */ |
| 989 | intr0 |= BIT(1); |
| 990 | |
| 991 | data->ddc_read_req = true; |
| 992 | } |
| 993 | |
| 994 | DSS_REG_W_ND(io, HDMI_DDC_INT_CTRL0, intr0); |
| 995 | |
| 996 | if (intr5 & BIT(0)) { |
| 997 | pr_err("RXSTATUS_DDC_REQ_TIMEOUT\n"); |
| 998 | |
| 999 | /* ack and disable timeout interrupt */ |
| 1000 | intr5 |= BIT(1); |
| 1001 | intr5 &= ~BIT(2); |
| 1002 | |
| 1003 | data->ddc_timeout = true; |
| 1004 | } |
| 1005 | DSS_REG_W_ND(io, HDMI_DDC_INT_CTRL5, intr5); |
| 1006 | |
| 1007 | if (data->message_size || data->ready || data->reauth_req) { |
| 1008 | if (data->wait) { |
| 1009 | atomic_set(&ddc_ctrl->rxstatus_busy_wait_done, 1); |
| 1010 | } else if (data->link_cb && data->link_data) { |
| 1011 | data->link_cb(data->link_data); |
| 1012 | } else { |
| 1013 | pr_err("new msg/reauth not handled\n"); |
| 1014 | rc = -EINVAL; |
| 1015 | } |
| 1016 | } |
| 1017 | |
| 1018 | hdmi_hdcp2p2_ddc_clear_status(ddc_ctrl); |
| 1019 | |
| 1020 | return rc; |
| 1021 | } |
| 1022 | |
| 1023 | static int hdmi_ddc_scrambling_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 1024 | { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 1025 | struct mdss_io_data *io; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1026 | bool scrambler_timer_off = false; |
| 1027 | u32 intr2, intr5; |
| 1028 | |
| 1029 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 1030 | pr_err("invalid input\n"); |
| 1031 | return -EINVAL; |
| 1032 | } |
| 1033 | |
| 1034 | io = ddc_ctrl->io; |
| 1035 | |
| 1036 | intr2 = DSS_REG_R_ND(io, HDMI_DDC_INT_CTRL2); |
| 1037 | intr5 = DSS_REG_R_ND(io, HDMI_DDC_INT_CTRL5); |
| 1038 | |
| 1039 | pr_debug("intr2: 0x%x, intr5: 0x%x\n", intr2, intr5); |
| 1040 | |
| 1041 | if (intr2 & BIT(12)) { |
| 1042 | pr_err("SCRAMBLER_STATUS_NOT\n"); |
| 1043 | |
| 1044 | intr2 |= BIT(14); |
| 1045 | |
| 1046 | scrambler_timer_off = true; |
| 1047 | } |
| 1048 | |
| 1049 | if (intr2 & BIT(8)) { |
| 1050 | pr_err("SCRAMBLER_STATUS_DDC_FAILED\n"); |
| 1051 | |
| 1052 | intr2 |= BIT(9); |
| 1053 | |
| 1054 | scrambler_timer_off = true; |
| 1055 | } |
| 1056 | DSS_REG_W_ND(io, HDMI_DDC_INT_CTRL2, intr2); |
| 1057 | |
| 1058 | if (intr5 & BIT(8)) { |
| 1059 | pr_err("SCRAMBLER_STATUS_DDC_REQ_TIMEOUT\n"); |
| 1060 | |
| 1061 | intr5 |= BIT(9); |
| 1062 | intr5 &= ~BIT(10); |
| 1063 | |
| 1064 | scrambler_timer_off = true; |
| 1065 | } |
| 1066 | DSS_REG_W_ND(io, HDMI_DDC_INT_CTRL5, intr5); |
| 1067 | |
| 1068 | if (scrambler_timer_off) |
| 1069 | hdmi_scrambler_ddc_disable(ddc_ctrl); |
| 1070 | |
| 1071 | return 0; |
| 1072 | } |
| 1073 | |
| 1074 | int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl, u32 version) |
| 1075 | { |
| 1076 | u32 ddc_int_ctrl, ret = 0; |
| 1077 | |
| 1078 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 1079 | pr_err("invalid input\n"); |
| 1080 | return -EINVAL; |
| 1081 | } |
| 1082 | |
| 1083 | ddc_int_ctrl = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL); |
| 1084 | pr_debug("intr: 0x%x\n", ddc_int_ctrl); |
| 1085 | |
| 1086 | if (ddc_int_ctrl & BIT(0)) { |
| 1087 | pr_debug("sw done\n"); |
| 1088 | |
| 1089 | ddc_int_ctrl |= BIT(1); |
| 1090 | if (ddc_ctrl->ddc_data.hard_timeout) { |
| 1091 | atomic_set(&ddc_ctrl->read_busy_wait_done, 1); |
| 1092 | atomic_set(&ddc_ctrl->write_busy_wait_done, 1); |
| 1093 | } else { |
| 1094 | complete(&ddc_ctrl->ddc_sw_done); |
| 1095 | } |
| 1096 | } |
| 1097 | |
| 1098 | if (ddc_int_ctrl & BIT(4)) { |
| 1099 | pr_debug("hw done\n"); |
| 1100 | ddc_int_ctrl |= BIT(5); |
| 1101 | } |
| 1102 | |
| 1103 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, ddc_int_ctrl); |
| 1104 | |
| 1105 | if (version >= HDMI_TX_SCRAMBLER_MIN_TX_VERSION) { |
| 1106 | ret = hdmi_ddc_scrambling_isr(ddc_ctrl); |
| 1107 | if (ret) |
| 1108 | pr_err("err in scrambling isr\n"); |
| 1109 | } |
| 1110 | |
| 1111 | ret = hdmi_ddc_hdcp2p2_isr(ddc_ctrl); |
| 1112 | if (ret) |
| 1113 | pr_err("err in hdcp2p2 isr\n"); |
| 1114 | |
| 1115 | return ret; |
| 1116 | } /* hdmi_ddc_isr */ |
| 1117 | |
| 1118 | int hdmi_ddc_read(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 1119 | { |
| 1120 | int rc = 0; |
| 1121 | int retry; |
| 1122 | struct hdmi_tx_ddc_data *ddc_data; |
| 1123 | |
| 1124 | if (!ddc_ctrl) { |
| 1125 | pr_err("invalid ddc ctrl\n"); |
| 1126 | return -EINVAL; |
| 1127 | } |
| 1128 | |
| 1129 | ddc_data = &ddc_ctrl->ddc_data; |
| 1130 | retry = ddc_data->retry; |
| 1131 | |
| 1132 | rc = hdmi_ddc_read_retry(ddc_ctrl); |
| 1133 | if (!rc) |
| 1134 | return rc; |
| 1135 | |
| 1136 | if (ddc_data->retry_align) { |
| 1137 | ddc_data->retry = retry; |
| 1138 | |
| 1139 | ddc_data->request_len = 32 * ((ddc_data->data_len + 31) / 32); |
| 1140 | rc = hdmi_ddc_read_retry(ddc_ctrl); |
| 1141 | } |
| 1142 | |
| 1143 | return rc; |
| 1144 | } /* hdmi_ddc_read */ |
| 1145 | |
| 1146 | int hdmi_ddc_read_seg(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 1147 | { |
| 1148 | int status; |
| 1149 | u32 reg_val, ndx, time_out_count; |
| 1150 | struct hdmi_tx_ddc_data *ddc_data; |
| 1151 | |
| 1152 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 1153 | pr_err("invalid input\n"); |
| 1154 | return -EINVAL; |
| 1155 | } |
| 1156 | |
| 1157 | ddc_data = &ddc_ctrl->ddc_data; |
| 1158 | |
| 1159 | if (!ddc_data->data_buf) { |
| 1160 | status = -EINVAL; |
| 1161 | pr_err("%s: invalid buf\n", ddc_data->what); |
| 1162 | goto error; |
| 1163 | } |
| 1164 | |
| 1165 | if (ddc_data->retry < 0) { |
| 1166 | pr_err("invalid no. of retries %d\n", ddc_data->retry); |
| 1167 | status = -EINVAL; |
| 1168 | goto error; |
| 1169 | } |
| 1170 | |
| 1171 | do { |
| 1172 | status = hdmi_ddc_clear_irq(ddc_ctrl, ddc_data->what); |
| 1173 | if (status) |
| 1174 | continue; |
| 1175 | |
| 1176 | reinit_completion(&ddc_ctrl->ddc_sw_done); |
| 1177 | |
| 1178 | hdmi_ddc_trigger(ddc_ctrl, TRIGGER_READ, true); |
| 1179 | |
| 1180 | time_out_count = wait_for_completion_timeout( |
| 1181 | &ddc_ctrl->ddc_sw_done, HZ / 2); |
| 1182 | |
| 1183 | if (!time_out_count) { |
| 1184 | pr_debug("%s: timedout\n", ddc_data->what); |
| 1185 | |
| 1186 | status = -ETIMEDOUT; |
| 1187 | } |
| 1188 | |
| 1189 | hdmi_ddc_clear_status(ddc_ctrl); |
| 1190 | } while (status && ddc_data->retry--); |
| 1191 | |
| 1192 | if (status) |
| 1193 | goto error; |
| 1194 | |
| 1195 | /* Write data to DDC buffer */ |
| 1196 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, |
| 1197 | BIT(0) | (5 << 16) | BIT(31)); |
| 1198 | |
| 1199 | /* Discard first byte */ |
| 1200 | DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA); |
| 1201 | |
| 1202 | for (ndx = 0; ndx < ddc_data->data_len; ++ndx) { |
| 1203 | reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA); |
| 1204 | ddc_data->data_buf[ndx] = (u8) ((reg_val & 0x0000FF00) >> 8); |
| 1205 | } |
| 1206 | |
| 1207 | pr_debug("%s: success\n", ddc_data->what); |
| 1208 | |
| 1209 | error: |
| 1210 | return status; |
| 1211 | } /* hdmi_ddc_read_seg */ |
| 1212 | |
| 1213 | int hdmi_ddc_write(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 1214 | { |
| 1215 | int status; |
| 1216 | u32 time_out_count; |
| 1217 | struct hdmi_tx_ddc_data *ddc_data; |
| 1218 | u32 wait_time; |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 1219 | int busy_wait_us = 0; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1220 | |
| 1221 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 1222 | pr_err("invalid input\n"); |
| 1223 | return -EINVAL; |
| 1224 | } |
| 1225 | |
| 1226 | ddc_data = &ddc_ctrl->ddc_data; |
| 1227 | |
| 1228 | if (!ddc_data->data_buf) { |
| 1229 | status = -EINVAL; |
| 1230 | pr_err("%s: invalid buf\n", ddc_data->what); |
| 1231 | goto error; |
| 1232 | } |
| 1233 | |
| 1234 | if (ddc_data->retry < 0) { |
| 1235 | pr_err("invalid no. of retries %d\n", ddc_data->retry); |
| 1236 | status = -EINVAL; |
| 1237 | goto error; |
| 1238 | } |
| 1239 | |
| 1240 | do { |
| 1241 | status = hdmi_ddc_clear_irq(ddc_ctrl, ddc_data->what); |
| 1242 | if (status) |
| 1243 | continue; |
| 1244 | |
| 1245 | if (ddc_data->hard_timeout) { |
| 1246 | pr_debug("using hard_timeout %dms\n", |
| 1247 | ddc_data->hard_timeout); |
| 1248 | |
| 1249 | busy_wait_us = ddc_data->hard_timeout * HDMI_MS_TO_US; |
| 1250 | atomic_set(&ddc_ctrl->write_busy_wait_done, 0); |
| 1251 | } else { |
| 1252 | reinit_completion(&ddc_ctrl->ddc_sw_done); |
| 1253 | wait_time = HZ / 2; |
| 1254 | } |
| 1255 | |
| 1256 | hdmi_ddc_trigger(ddc_ctrl, TRIGGER_WRITE, false); |
| 1257 | |
| 1258 | if (ddc_data->hard_timeout) { |
| 1259 | while (busy_wait_us > 0 && |
| 1260 | !atomic_read(&ddc_ctrl->write_busy_wait_done)) { |
| 1261 | udelay(HDMI_BUSY_WAIT_DELAY_US); |
| 1262 | busy_wait_us -= HDMI_BUSY_WAIT_DELAY_US; |
| 1263 | }; |
| 1264 | |
| 1265 | if (busy_wait_us < 0) |
| 1266 | busy_wait_us = 0; |
| 1267 | |
| 1268 | time_out_count = busy_wait_us / HDMI_MS_TO_US; |
| 1269 | |
| 1270 | ddc_data->timeout_left = time_out_count; |
| 1271 | } else { |
| 1272 | time_out_count = wait_for_completion_timeout( |
| 1273 | &ddc_ctrl->ddc_sw_done, wait_time); |
| 1274 | |
| 1275 | ddc_data->timeout_left = |
| 1276 | jiffies_to_msecs(time_out_count); |
| 1277 | } |
| 1278 | |
| 1279 | pr_debug("DDC write done at %dms\n", jiffies_to_msecs(jiffies)); |
| 1280 | |
| 1281 | if (!time_out_count) { |
| 1282 | pr_debug("%s timout\n", ddc_data->what); |
| 1283 | |
| 1284 | status = -ETIMEDOUT; |
| 1285 | } |
| 1286 | |
| 1287 | hdmi_ddc_clear_status(ddc_ctrl); |
| 1288 | } while (status && ddc_data->retry--); |
| 1289 | |
| 1290 | if (status) |
| 1291 | goto error; |
| 1292 | |
| 1293 | pr_debug("%s: success\n", ddc_data->what); |
| 1294 | error: |
| 1295 | return status; |
| 1296 | } /* hdmi_ddc_write */ |
| 1297 | |
| 1298 | |
| 1299 | int hdmi_ddc_abort_transaction(struct hdmi_tx_ddc_ctrl *ddc_ctrl) |
| 1300 | { |
| 1301 | int status; |
| 1302 | struct hdmi_tx_ddc_data *ddc_data; |
| 1303 | |
| 1304 | if (!ddc_ctrl || !ddc_ctrl->io) { |
| 1305 | pr_err("invalid input\n"); |
| 1306 | return -EINVAL; |
| 1307 | } |
| 1308 | |
| 1309 | ddc_data = &ddc_ctrl->ddc_data; |
| 1310 | |
| 1311 | status = hdmi_ddc_clear_irq(ddc_ctrl, ddc_data->what); |
| 1312 | if (status) |
| 1313 | goto error; |
| 1314 | |
| 1315 | DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_ARBITRATION, BIT(12)|BIT(8)); |
| 1316 | |
| 1317 | error: |
| 1318 | return status; |
| 1319 | |
| 1320 | } |
| 1321 | |
| 1322 | int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val) |
| 1323 | { |
| 1324 | struct hdmi_tx_ddc_data data = {0}; |
| 1325 | int rc = 0; |
| 1326 | u8 data_buf[2] = {0}; |
| 1327 | |
| 1328 | if (!ctrl || !ctrl->io || !val) { |
| 1329 | pr_err("Bad Parameters\n"); |
| 1330 | return -EINVAL; |
| 1331 | } |
| 1332 | |
| 1333 | if (data_type >= HDMI_TX_SCDC_MAX) { |
| 1334 | pr_err("Unsupported data type\n"); |
| 1335 | return -EINVAL; |
| 1336 | } |
| 1337 | |
| 1338 | data.what = hdmi_scdc_reg2string(data_type); |
| 1339 | data.dev_addr = 0xA8; |
| 1340 | data.retry = 1; |
| 1341 | data.data_buf = data_buf; |
| 1342 | |
| 1343 | switch (data_type) { |
| 1344 | case HDMI_TX_SCDC_SCRAMBLING_STATUS: |
| 1345 | data.data_len = 1; |
| 1346 | data.request_len = 1; |
| 1347 | data.offset = HDMI_SCDC_SCRAMBLER_STATUS; |
| 1348 | break; |
| 1349 | case HDMI_TX_SCDC_SCRAMBLING_ENABLE: |
| 1350 | case HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE: |
| 1351 | data.data_len = 1; |
| 1352 | data.request_len = 1; |
| 1353 | data.offset = HDMI_SCDC_TMDS_CONFIG; |
| 1354 | break; |
| 1355 | case HDMI_TX_SCDC_CLOCK_DET_STATUS: |
| 1356 | case HDMI_TX_SCDC_CH0_LOCK_STATUS: |
| 1357 | case HDMI_TX_SCDC_CH1_LOCK_STATUS: |
| 1358 | case HDMI_TX_SCDC_CH2_LOCK_STATUS: |
| 1359 | data.data_len = 1; |
| 1360 | data.request_len = 1; |
| 1361 | data.offset = HDMI_SCDC_STATUS_FLAGS_0; |
| 1362 | break; |
| 1363 | case HDMI_TX_SCDC_CH0_ERROR_COUNT: |
| 1364 | data.data_len = 2; |
| 1365 | data.request_len = 2; |
| 1366 | data.offset = HDMI_SCDC_ERR_DET_0_L; |
| 1367 | break; |
| 1368 | case HDMI_TX_SCDC_CH1_ERROR_COUNT: |
| 1369 | data.data_len = 2; |
| 1370 | data.request_len = 2; |
| 1371 | data.offset = HDMI_SCDC_ERR_DET_1_L; |
| 1372 | break; |
| 1373 | case HDMI_TX_SCDC_CH2_ERROR_COUNT: |
| 1374 | data.data_len = 2; |
| 1375 | data.request_len = 2; |
| 1376 | data.offset = HDMI_SCDC_ERR_DET_2_L; |
| 1377 | break; |
| 1378 | case HDMI_TX_SCDC_READ_ENABLE: |
| 1379 | data.data_len = 1; |
| 1380 | data.request_len = 1; |
| 1381 | data.offset = HDMI_SCDC_CONFIG_0; |
| 1382 | break; |
| 1383 | default: |
| 1384 | break; |
| 1385 | } |
| 1386 | |
| 1387 | ctrl->ddc_data = data; |
| 1388 | |
| 1389 | rc = hdmi_ddc_read(ctrl); |
| 1390 | if (rc) { |
| 1391 | pr_err("DDC Read failed for %s\n", data.what); |
| 1392 | return rc; |
| 1393 | } |
| 1394 | |
| 1395 | switch (data_type) { |
| 1396 | case HDMI_TX_SCDC_SCRAMBLING_STATUS: |
| 1397 | *val = (data_buf[0] & BIT(0)) ? 1 : 0; |
| 1398 | break; |
| 1399 | case HDMI_TX_SCDC_SCRAMBLING_ENABLE: |
| 1400 | *val = (data_buf[0] & BIT(0)) ? 1 : 0; |
| 1401 | break; |
| 1402 | case HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE: |
| 1403 | *val = (data_buf[0] & BIT(1)) ? 1 : 0; |
| 1404 | break; |
| 1405 | case HDMI_TX_SCDC_CLOCK_DET_STATUS: |
| 1406 | *val = (data_buf[0] & BIT(0)) ? 1 : 0; |
| 1407 | break; |
| 1408 | case HDMI_TX_SCDC_CH0_LOCK_STATUS: |
| 1409 | *val = (data_buf[0] & BIT(1)) ? 1 : 0; |
| 1410 | break; |
| 1411 | case HDMI_TX_SCDC_CH1_LOCK_STATUS: |
| 1412 | *val = (data_buf[0] & BIT(2)) ? 1 : 0; |
| 1413 | break; |
| 1414 | case HDMI_TX_SCDC_CH2_LOCK_STATUS: |
| 1415 | *val = (data_buf[0] & BIT(3)) ? 1 : 0; |
| 1416 | break; |
| 1417 | case HDMI_TX_SCDC_CH0_ERROR_COUNT: |
| 1418 | case HDMI_TX_SCDC_CH1_ERROR_COUNT: |
| 1419 | case HDMI_TX_SCDC_CH2_ERROR_COUNT: |
| 1420 | if (data_buf[1] & BIT(7)) |
| 1421 | *val = (data_buf[0] | ((data_buf[1] & 0x7F) << 8)); |
| 1422 | else |
| 1423 | *val = 0; |
| 1424 | break; |
| 1425 | case HDMI_TX_SCDC_READ_ENABLE: |
| 1426 | *val = (data_buf[0] & BIT(0)) ? 1 : 0; |
| 1427 | break; |
| 1428 | default: |
| 1429 | break; |
| 1430 | } |
| 1431 | |
| 1432 | return 0; |
| 1433 | } |
| 1434 | |
| 1435 | int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val) |
| 1436 | { |
| 1437 | struct hdmi_tx_ddc_data data = {0}; |
| 1438 | struct hdmi_tx_ddc_data rdata = {0}; |
| 1439 | int rc = 0; |
| 1440 | u8 data_buf[2] = {0}; |
| 1441 | u8 read_val = 0; |
| 1442 | |
| 1443 | if (!ctrl || !ctrl->io) { |
| 1444 | pr_err("Bad Parameters\n"); |
| 1445 | return -EINVAL; |
| 1446 | } |
| 1447 | |
| 1448 | if (data_type >= HDMI_TX_SCDC_MAX) { |
| 1449 | pr_err("Unsupported data type\n"); |
| 1450 | return -EINVAL; |
| 1451 | } |
| 1452 | |
| 1453 | data.what = hdmi_scdc_reg2string(data_type); |
| 1454 | data.dev_addr = 0xA8; |
| 1455 | data.retry = 1; |
| 1456 | data.data_buf = data_buf; |
| 1457 | |
| 1458 | switch (data_type) { |
| 1459 | case HDMI_TX_SCDC_SCRAMBLING_ENABLE: |
| 1460 | case HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE: |
| 1461 | rdata.what = "TMDS CONFIG"; |
| 1462 | rdata.dev_addr = 0xA8; |
| 1463 | rdata.retry = 2; |
| 1464 | rdata.data_buf = &read_val; |
| 1465 | rdata.data_len = 1; |
| 1466 | rdata.offset = HDMI_SCDC_TMDS_CONFIG; |
| 1467 | rdata.request_len = 1; |
| 1468 | ctrl->ddc_data = rdata; |
| 1469 | rc = hdmi_ddc_read(ctrl); |
| 1470 | if (rc) { |
| 1471 | pr_err("scdc read failed\n"); |
| 1472 | return rc; |
| 1473 | } |
| 1474 | if (data_type == HDMI_TX_SCDC_SCRAMBLING_ENABLE) { |
| 1475 | data_buf[0] = ((((u8)(read_val & 0xFF)) & (~BIT(0))) | |
| 1476 | ((u8)(val & BIT(0)))); |
| 1477 | } else { |
| 1478 | data_buf[0] = ((((u8)(read_val & 0xFF)) & (~BIT(1))) | |
| 1479 | (((u8)(val & BIT(0))) << 1)); |
| 1480 | } |
| 1481 | data.data_len = 1; |
| 1482 | data.request_len = 1; |
| 1483 | data.offset = HDMI_SCDC_TMDS_CONFIG; |
| 1484 | break; |
| 1485 | case HDMI_TX_SCDC_READ_ENABLE: |
| 1486 | data.data_len = 1; |
| 1487 | data.request_len = 1; |
| 1488 | data.offset = HDMI_SCDC_CONFIG_0; |
| 1489 | data_buf[0] = (u8)(val & 0x1); |
| 1490 | break; |
| 1491 | default: |
| 1492 | pr_err("Cannot write to read only reg (%d)\n", |
| 1493 | data_type); |
| 1494 | return -EINVAL; |
| 1495 | } |
| 1496 | |
| 1497 | ctrl->ddc_data = data; |
| 1498 | |
| 1499 | rc = hdmi_ddc_write(ctrl); |
| 1500 | if (rc) { |
| 1501 | pr_err("DDC Read failed for %s\n", data.what); |
| 1502 | return rc; |
| 1503 | } |
| 1504 | |
| 1505 | return 0; |
| 1506 | } |
| 1507 | |
| 1508 | int hdmi_setup_ddc_timers(struct hdmi_tx_ddc_ctrl *ctrl, |
| 1509 | u32 type, u32 to_in_num_lines) |
| 1510 | { |
| 1511 | if (!ctrl) { |
| 1512 | pr_err("Invalid parameters\n"); |
| 1513 | return -EINVAL; |
| 1514 | } |
| 1515 | |
| 1516 | if (type >= HDMI_TX_DDC_TIMER_MAX) { |
| 1517 | pr_err("Invalid timer type %d\n", type); |
| 1518 | return -EINVAL; |
| 1519 | } |
| 1520 | |
| 1521 | switch (type) { |
| 1522 | case HDMI_TX_DDC_TIMER_SCRAMBLER_STATUS: |
| 1523 | hdmi_scrambler_status_timer_setup(ctrl, to_in_num_lines); |
| 1524 | break; |
| 1525 | default: |
| 1526 | pr_err("%d type not supported\n", type); |
| 1527 | return -EINVAL; |
| 1528 | } |
| 1529 | |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | static void hdmi_hdcp2p2_ddc_reset(struct hdmi_tx_ddc_ctrl *ctrl) |
| 1534 | { |
| 1535 | u32 reg_val; |
| 1536 | |
| 1537 | if (!ctrl) { |
| 1538 | pr_err("Invalid parameters\n"); |
| 1539 | return; |
| 1540 | } |
| 1541 | |
| 1542 | /* |
| 1543 | * Clear acks for DDC_REQ, DDC_DONE, DDC_FAILED, RXSTATUS_READY, |
| 1544 | * RXSTATUS_MSG_SIZE |
| 1545 | */ |
| 1546 | reg_val = BIT(30) | BIT(17) | BIT(13) | BIT(9) | BIT(5) | BIT(1); |
| 1547 | DSS_REG_W(ctrl->io, HDMI_DDC_INT_CTRL0, reg_val); |
| 1548 | |
| 1549 | /* Reset DDC timers */ |
| 1550 | reg_val = BIT(0) | DSS_REG_R(ctrl->io, HDMI_HDCP2P2_DDC_CTRL); |
| 1551 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_CTRL, reg_val); |
| 1552 | reg_val = DSS_REG_R(ctrl->io, HDMI_HDCP2P2_DDC_CTRL); |
| 1553 | reg_val &= ~BIT(0); |
| 1554 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_CTRL, reg_val); |
| 1555 | } |
| 1556 | |
| 1557 | void hdmi_hdcp2p2_ddc_disable(struct hdmi_tx_ddc_ctrl *ctrl) |
| 1558 | { |
| 1559 | u32 reg_val; |
| 1560 | |
| 1561 | if (!ctrl) { |
| 1562 | pr_err("Invalid parameters\n"); |
| 1563 | return; |
| 1564 | } |
| 1565 | |
| 1566 | hdmi_hdcp2p2_ddc_reset(ctrl); |
| 1567 | |
| 1568 | /* Disable HW DDC access to RxStatus register */ |
| 1569 | reg_val = DSS_REG_R(ctrl->io, HDMI_HW_DDC_CTRL); |
| 1570 | reg_val &= ~(BIT(1) | BIT(0)); |
| 1571 | |
| 1572 | DSS_REG_W(ctrl->io, HDMI_HW_DDC_CTRL, reg_val); |
| 1573 | } |
| 1574 | |
| 1575 | int hdmi_hdcp2p2_ddc_read_rxstatus(struct hdmi_tx_ddc_ctrl *ctrl) |
| 1576 | { |
| 1577 | u32 reg_val; |
| 1578 | u32 intr_en_mask; |
| 1579 | u32 timeout; |
| 1580 | u32 timer; |
| 1581 | int rc = 0; |
| 1582 | struct hdmi_tx_hdcp2p2_ddc_data *data; |
| 1583 | int busy_wait_us; |
| 1584 | |
| 1585 | if (!ctrl) { |
| 1586 | pr_err("Invalid ctrl data\n"); |
| 1587 | return -EINVAL; |
| 1588 | } |
| 1589 | |
| 1590 | data = &ctrl->hdcp2p2_ddc_data; |
| 1591 | if (!data) { |
| 1592 | pr_err("Invalid ddc data\n"); |
| 1593 | return -EINVAL; |
| 1594 | } |
| 1595 | |
| 1596 | rc = hdmi_ddc_clear_irq(ctrl, "rxstatus"); |
| 1597 | if (rc) |
| 1598 | return rc; |
| 1599 | |
| 1600 | intr_en_mask = data->intr_mask; |
| 1601 | intr_en_mask |= BIT(HDCP2P2_RXSTATUS_DDC_FAILED_INTR_MASK); |
| 1602 | |
| 1603 | /* Disable short read for now, sinks don't support it */ |
| 1604 | reg_val = DSS_REG_R(ctrl->io, HDMI_HDCP2P2_DDC_CTRL); |
| 1605 | reg_val |= BIT(4); |
| 1606 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_CTRL, reg_val); |
| 1607 | |
| 1608 | /* |
| 1609 | * Setup the DDC timers for HDMI_HDCP2P2_DDC_TIMER_CTRL1 and |
| 1610 | * HDMI_HDCP2P2_DDC_TIMER_CTRL2. |
| 1611 | * Following are the timers: |
| 1612 | * 1. DDC_REQUEST_TIMER: Timeout in hsyncs in which to wait for the |
| 1613 | * HDCP 2.2 sink to respond to an RxStatus request |
| 1614 | * 2. DDC_URGENT_TIMER: Time period in hsyncs to issue an urgent flag |
| 1615 | * when an RxStatus DDC request is made but not accepted by I2C |
| 1616 | * engine |
| 1617 | * 3. DDC_TIMEOUT_TIMER: Timeout in hsyncs which starts counting when |
| 1618 | * a request is made and stops when it is accepted by DDC arbiter |
| 1619 | */ |
| 1620 | timeout = data->timeout_hsync; |
| 1621 | timer = data->periodic_timer_hsync; |
| 1622 | pr_debug("timeout: %d hsyncs, timer %d hsync\n", timeout, timer); |
| 1623 | |
| 1624 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_TIMER_CTRL, timer); |
| 1625 | |
| 1626 | /* Set both urgent and hw-timeout fields to the same value */ |
| 1627 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_TIMER_CTRL2, |
| 1628 | (timeout << 16 | timeout)); |
| 1629 | |
| 1630 | /* enable interrupts */ |
| 1631 | reg_val = intr_en_mask; |
| 1632 | /* Clear interrupt status bits */ |
| 1633 | reg_val |= intr_en_mask >> 1; |
| 1634 | |
| 1635 | pr_debug("writing HDMI_DDC_INT_CTRL0 0x%x\n", reg_val); |
| 1636 | DSS_REG_W(ctrl->io, HDMI_DDC_INT_CTRL0, reg_val); |
| 1637 | |
| 1638 | reg_val = DSS_REG_R(ctrl->io, HDMI_DDC_INT_CTRL5); |
| 1639 | /* clear and enable RxStatus read timeout */ |
| 1640 | reg_val |= BIT(2) | BIT(1); |
| 1641 | |
| 1642 | DSS_REG_W(ctrl->io, HDMI_DDC_INT_CTRL5, reg_val); |
| 1643 | |
| 1644 | /* |
| 1645 | * Enable hardware DDC access to RxStatus register |
| 1646 | * |
| 1647 | * HDMI_HW_DDC_CTRL:Bits 1:0 (RXSTATUS_DDC_ENABLE) read like this: |
| 1648 | * |
| 1649 | * 0 = disable HW controlled DDC access to RxStatus |
| 1650 | * 1 = automatic on when HDCP 2.2 is authenticated and loop based on |
| 1651 | * request timer (i.e. the hardware will loop automatically) |
| 1652 | * 2 = force on and loop based on request timer (hardware will loop) |
| 1653 | * 3 = enable by sw trigger and loop until interrupt is generated for |
| 1654 | * RxStatus.reauth_req, RxStatus.ready or RxStatus.message_Size. |
| 1655 | * |
| 1656 | * Depending on the value of ddc_data::poll_sink, we make the decision |
| 1657 | * to use either SW_TRIGGER(3) (poll_sink = false) which means that the |
| 1658 | * hardware will poll sink and generate interrupt when sink responds, |
| 1659 | * or use AUTOMATIC_LOOP(1) (poll_sink = true) which will poll the sink |
| 1660 | * based on request timer |
| 1661 | */ |
| 1662 | reg_val = DSS_REG_R(ctrl->io, HDMI_HW_DDC_CTRL); |
| 1663 | reg_val &= ~(BIT(1) | BIT(0)); |
| 1664 | |
| 1665 | busy_wait_us = data->timeout_ms * HDMI_MS_TO_US; |
| 1666 | atomic_set(&ctrl->rxstatus_busy_wait_done, 0); |
| 1667 | |
| 1668 | /* read method: HDCP2P2_RXSTATUS_HW_DDC_SW_TRIGGER */ |
| 1669 | reg_val |= BIT(1) | BIT(0); |
| 1670 | DSS_REG_W(ctrl->io, HDMI_HW_DDC_CTRL, reg_val); |
| 1671 | DSS_REG_W(ctrl->io, HDMI_HDCP2P2_DDC_SW_TRIGGER, 1); |
| 1672 | |
| 1673 | if (data->wait) { |
| 1674 | while (busy_wait_us > 0 && |
| 1675 | !atomic_read(&ctrl->rxstatus_busy_wait_done)) { |
| 1676 | udelay(HDMI_BUSY_WAIT_DELAY_US); |
| 1677 | busy_wait_us -= HDMI_BUSY_WAIT_DELAY_US; |
| 1678 | }; |
| 1679 | |
| 1680 | if (busy_wait_us < 0) |
| 1681 | busy_wait_us = 0; |
| 1682 | |
| 1683 | data->timeout_left = busy_wait_us / HDMI_MS_TO_US; |
| 1684 | |
| 1685 | if (!data->timeout_left) { |
| 1686 | pr_err("sw ddc rxstatus timeout\n"); |
| 1687 | rc = -ETIMEDOUT; |
| 1688 | } |
| 1689 | |
| 1690 | hdmi_hdcp2p2_ddc_disable(ctrl); |
| 1691 | } |
| 1692 | |
| 1693 | return rc; |
| 1694 | } |