Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame^] | 1 | /* 10G controller driver for Samsung SoCs |
| 2 | * |
| 3 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * Author: Siva Reddy Kallam <siva.kallam@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 14 | |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/crc32.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/etherdevice.h> |
| 19 | #include <linux/ethtool.h> |
| 20 | #include <linux/if.h> |
| 21 | #include <linux/if_ether.h> |
| 22 | #include <linux/if_vlan.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/ip.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/mii.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/net_tstamp.h> |
| 30 | #include <linux/netdevice.h> |
| 31 | #include <linux/phy.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/prefetch.h> |
| 34 | #include <linux/skbuff.h> |
| 35 | #include <linux/slab.h> |
| 36 | #include <linux/tcp.h> |
| 37 | #include <linux/sxgbe_platform.h> |
| 38 | |
| 39 | #include "sxgbe_common.h" |
| 40 | #include "sxgbe_desc.h" |
| 41 | #include "sxgbe_dma.h" |
| 42 | #include "sxgbe_mtl.h" |
| 43 | #include "sxgbe_reg.h" |
| 44 | |
| 45 | #define SXGBE_ALIGN(x) L1_CACHE_ALIGN(x) |
| 46 | #define JUMBO_LEN 9000 |
| 47 | |
| 48 | /* Module parameters */ |
| 49 | #define TX_TIMEO 5000 |
| 50 | #define DMA_TX_SIZE 512 |
| 51 | #define DMA_RX_SIZE 1024 |
| 52 | #define TC_DEFAULT 64 |
| 53 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB |
| 54 | /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */ |
| 55 | #define SXGBE_DEFAULT_LPI_TIMER 1000 |
| 56 | |
| 57 | static int debug = -1; |
| 58 | |
| 59 | module_param(debug, int, S_IRUGO | S_IWUSR); |
| 60 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
| 61 | NETIF_MSG_LINK | NETIF_MSG_IFUP | |
| 62 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); |
| 63 | |
| 64 | static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id); |
| 65 | static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id); |
| 66 | static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id); |
| 67 | |
| 68 | #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
| 69 | |
| 70 | /** |
| 71 | * sxgbe_clk_csr_set - dynamically set the MDC clock |
| 72 | * @priv: driver private structure |
| 73 | * Description: this is to dynamically set the MDC clock according to the csr |
| 74 | * clock input. |
| 75 | */ |
| 76 | static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv) |
| 77 | { |
| 78 | u32 clk_rate = clk_get_rate(priv->sxgbe_clk); |
| 79 | |
| 80 | /* assign the proper divider, this will be used during |
| 81 | * mdio communication |
| 82 | */ |
| 83 | if (clk_rate < SXGBE_CSR_F_150M) |
| 84 | priv->clk_csr = SXGBE_CSR_100_150M; |
| 85 | else if (clk_rate <= SXGBE_CSR_F_250M) |
| 86 | priv->clk_csr = SXGBE_CSR_150_250M; |
| 87 | else if (clk_rate <= SXGBE_CSR_F_300M) |
| 88 | priv->clk_csr = SXGBE_CSR_250_300M; |
| 89 | else if (clk_rate <= SXGBE_CSR_F_350M) |
| 90 | priv->clk_csr = SXGBE_CSR_300_350M; |
| 91 | else if (clk_rate <= SXGBE_CSR_F_400M) |
| 92 | priv->clk_csr = SXGBE_CSR_350_400M; |
| 93 | else if (clk_rate <= SXGBE_CSR_F_500M) |
| 94 | priv->clk_csr = SXGBE_CSR_400_500M; |
| 95 | } |
| 96 | |
| 97 | /* minimum number of free TX descriptors required to wake up TX process */ |
| 98 | #define SXGBE_TX_THRESH(x) (x->dma_tx_size/4) |
| 99 | |
| 100 | static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize) |
| 101 | { |
| 102 | return queue->dirty_tx + tx_qsize - queue->cur_tx - 1; |
| 103 | } |
| 104 | |
| 105 | /** |
| 106 | * sxgbe_adjust_link |
| 107 | * @dev: net device structure |
| 108 | * Description: it adjusts the link parameters. |
| 109 | */ |
| 110 | static void sxgbe_adjust_link(struct net_device *dev) |
| 111 | { |
| 112 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 113 | struct phy_device *phydev = priv->phydev; |
| 114 | u8 new_state = 0; |
| 115 | u8 speed = 0xff; |
| 116 | |
| 117 | if (!phydev) |
| 118 | return; |
| 119 | |
| 120 | /* SXGBE is not supporting auto-negotiation and |
| 121 | * half duplex mode. so, not handling duplex change |
| 122 | * in this function. only handling speed and link status |
| 123 | */ |
| 124 | if (phydev->link) { |
| 125 | if (phydev->speed != priv->speed) { |
| 126 | new_state = 1; |
| 127 | switch (phydev->speed) { |
| 128 | case SPEED_10000: |
| 129 | speed = SXGBE_SPEED_10G; |
| 130 | break; |
| 131 | case SPEED_2500: |
| 132 | speed = SXGBE_SPEED_2_5G; |
| 133 | break; |
| 134 | case SPEED_1000: |
| 135 | speed = SXGBE_SPEED_1G; |
| 136 | break; |
| 137 | default: |
| 138 | netif_err(priv, link, dev, |
| 139 | "Speed (%d) not supported\n", |
| 140 | phydev->speed); |
| 141 | } |
| 142 | |
| 143 | priv->speed = phydev->speed; |
| 144 | priv->hw->mac->set_speed(priv->ioaddr, speed); |
| 145 | } |
| 146 | |
| 147 | if (!priv->oldlink) { |
| 148 | new_state = 1; |
| 149 | priv->oldlink = 1; |
| 150 | } |
| 151 | } else if (priv->oldlink) { |
| 152 | new_state = 1; |
| 153 | priv->oldlink = 0; |
| 154 | priv->speed = SPEED_UNKNOWN; |
| 155 | } |
| 156 | |
| 157 | if (new_state & netif_msg_link(priv)) |
| 158 | phy_print_status(phydev); |
| 159 | } |
| 160 | |
| 161 | /** |
| 162 | * sxgbe_init_phy - PHY initialization |
| 163 | * @dev: net device structure |
| 164 | * Description: it initializes the driver's PHY state, and attaches the PHY |
| 165 | * to the mac driver. |
| 166 | * Return value: |
| 167 | * 0 on success |
| 168 | */ |
| 169 | static int sxgbe_init_phy(struct net_device *ndev) |
| 170 | { |
| 171 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
| 172 | char bus_id[MII_BUS_ID_SIZE]; |
| 173 | struct phy_device *phydev; |
| 174 | struct sxgbe_priv_data *priv = netdev_priv(ndev); |
| 175 | int phy_iface = priv->plat->interface; |
| 176 | |
| 177 | /* assign default link status */ |
| 178 | priv->oldlink = 0; |
| 179 | priv->speed = SPEED_UNKNOWN; |
| 180 | priv->oldduplex = DUPLEX_UNKNOWN; |
| 181 | |
| 182 | if (priv->plat->phy_bus_name) |
| 183 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", |
| 184 | priv->plat->phy_bus_name, priv->plat->bus_id); |
| 185 | else |
| 186 | snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x", |
| 187 | priv->plat->bus_id); |
| 188 | |
| 189 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
| 190 | priv->plat->phy_addr); |
| 191 | netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt); |
| 192 | |
| 193 | phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface); |
| 194 | |
| 195 | if (IS_ERR(phydev)) { |
| 196 | netdev_err(ndev, "Could not attach to PHY\n"); |
| 197 | return PTR_ERR(phydev); |
| 198 | } |
| 199 | |
| 200 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
| 201 | if ((phy_iface == PHY_INTERFACE_MODE_MII) || |
| 202 | (phy_iface == PHY_INTERFACE_MODE_RMII)) |
| 203 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
| 204 | SUPPORTED_1000baseT_Full); |
| 205 | if (phydev->phy_id == 0) { |
| 206 | phy_disconnect(phydev); |
| 207 | return -ENODEV; |
| 208 | } |
| 209 | |
| 210 | netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n", |
| 211 | __func__, phydev->phy_id, phydev->link); |
| 212 | |
| 213 | /* save phy device in private structure */ |
| 214 | priv->phydev = phydev; |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | /** |
| 220 | * sxgbe_clear_descriptors: clear descriptors |
| 221 | * @priv: driver private structure |
| 222 | * Description: this function is called to clear the tx and rx descriptors |
| 223 | * in case of both basic and extended descriptors are used. |
| 224 | */ |
| 225 | static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv) |
| 226 | { |
| 227 | int i, j; |
| 228 | unsigned int txsize = priv->dma_tx_size; |
| 229 | unsigned int rxsize = priv->dma_rx_size; |
| 230 | |
| 231 | /* Clear the Rx/Tx descriptors */ |
| 232 | for (j = 0; j < SXGBE_RX_QUEUES; j++) { |
| 233 | for (i = 0; i < rxsize; i++) |
| 234 | priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i], |
| 235 | priv->use_riwt, priv->mode, |
| 236 | (i == rxsize - 1)); |
| 237 | } |
| 238 | |
| 239 | for (j = 0; j < SXGBE_TX_QUEUES; j++) { |
| 240 | for (i = 0; i < txsize; i++) |
| 241 | priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | static int sxgbe_init_rx_buffers(struct net_device *dev, |
| 246 | struct sxgbe_rx_norm_desc *p, int i, |
| 247 | unsigned int dma_buf_sz, |
| 248 | struct sxgbe_rx_queue *rx_ring) |
| 249 | { |
| 250 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 251 | struct sk_buff *skb; |
| 252 | |
| 253 | skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL); |
| 254 | if (!skb) |
| 255 | return -ENOMEM; |
| 256 | |
| 257 | rx_ring->rx_skbuff[i] = skb; |
| 258 | rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, |
| 259 | dma_buf_sz, DMA_FROM_DEVICE); |
| 260 | |
| 261 | if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) { |
| 262 | netdev_err(dev, "%s: DMA mapping error\n", __func__); |
| 263 | dev_kfree_skb_any(skb); |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i]; |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | /** |
| 272 | * init_tx_ring - init the TX descriptor ring |
| 273 | * @dev: net device structure |
| 274 | * @tx_ring: ring to be intialised |
| 275 | * @tx_rsize: ring size |
| 276 | * Description: this function initializes the DMA TX descriptor |
| 277 | */ |
| 278 | static int init_tx_ring(struct device *dev, u8 queue_no, |
| 279 | struct sxgbe_tx_queue *tx_ring, int tx_rsize) |
| 280 | { |
| 281 | /* TX ring is not allcoated */ |
| 282 | if (!tx_ring) { |
| 283 | dev_err(dev, "No memory for TX queue of SXGBE\n"); |
| 284 | return -ENOMEM; |
| 285 | } |
| 286 | |
| 287 | /* allocate memory for TX descriptors */ |
| 288 | tx_ring->dma_tx = dma_zalloc_coherent(dev, |
| 289 | tx_rsize * sizeof(struct sxgbe_tx_norm_desc), |
| 290 | &tx_ring->dma_tx_phy, GFP_KERNEL); |
| 291 | if (!tx_ring->dma_tx) |
| 292 | return -ENOMEM; |
| 293 | |
| 294 | /* allocate memory for TX skbuff array */ |
| 295 | tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize, |
| 296 | sizeof(dma_addr_t), GFP_KERNEL); |
| 297 | if (!tx_ring->tx_skbuff_dma) |
| 298 | goto dmamem_err; |
| 299 | |
| 300 | tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize, |
| 301 | sizeof(struct sk_buff *), GFP_KERNEL); |
| 302 | |
| 303 | if (!tx_ring->tx_skbuff) |
| 304 | goto dmamem_err; |
| 305 | |
| 306 | /* assign queue number */ |
| 307 | tx_ring->queue_no = queue_no; |
| 308 | |
| 309 | /* initalise counters */ |
| 310 | tx_ring->dirty_tx = 0; |
| 311 | tx_ring->cur_tx = 0; |
| 312 | |
| 313 | /* initalise TX queue lock */ |
| 314 | spin_lock_init(&tx_ring->tx_lock); |
| 315 | |
| 316 | return 0; |
| 317 | |
| 318 | dmamem_err: |
| 319 | dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc), |
| 320 | tx_ring->dma_tx, tx_ring->dma_tx_phy); |
| 321 | return -ENOMEM; |
| 322 | } |
| 323 | |
| 324 | /** |
| 325 | * free_rx_ring - free the RX descriptor ring |
| 326 | * @dev: net device structure |
| 327 | * @rx_ring: ring to be intialised |
| 328 | * @rx_rsize: ring size |
| 329 | * Description: this function initializes the DMA RX descriptor |
| 330 | */ |
| 331 | void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring, |
| 332 | int rx_rsize) |
| 333 | { |
| 334 | dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc), |
| 335 | rx_ring->dma_rx, rx_ring->dma_rx_phy); |
| 336 | kfree(rx_ring->rx_skbuff_dma); |
| 337 | kfree(rx_ring->rx_skbuff); |
| 338 | } |
| 339 | |
| 340 | /** |
| 341 | * init_rx_ring - init the RX descriptor ring |
| 342 | * @dev: net device structure |
| 343 | * @rx_ring: ring to be intialised |
| 344 | * @rx_rsize: ring size |
| 345 | * Description: this function initializes the DMA RX descriptor |
| 346 | */ |
| 347 | static int init_rx_ring(struct net_device *dev, u8 queue_no, |
| 348 | struct sxgbe_rx_queue *rx_ring, int rx_rsize) |
| 349 | { |
| 350 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 351 | int desc_index; |
| 352 | unsigned int bfsize = 0; |
| 353 | unsigned int ret = 0; |
| 354 | |
| 355 | /* Set the max buffer size according to the MTU. */ |
| 356 | bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8); |
| 357 | |
| 358 | netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize); |
| 359 | |
| 360 | /* RX ring is not allcoated */ |
| 361 | if (rx_ring == NULL) { |
| 362 | netdev_err(dev, "No memory for RX queue\n"); |
| 363 | goto error; |
| 364 | } |
| 365 | |
| 366 | /* assign queue number */ |
| 367 | rx_ring->queue_no = queue_no; |
| 368 | |
| 369 | /* allocate memory for RX descriptors */ |
| 370 | rx_ring->dma_rx = dma_zalloc_coherent(priv->device, |
| 371 | rx_rsize * sizeof(struct sxgbe_rx_norm_desc), |
| 372 | &rx_ring->dma_rx_phy, GFP_KERNEL); |
| 373 | |
| 374 | if (rx_ring->dma_rx == NULL) |
| 375 | goto error; |
| 376 | |
| 377 | /* allocate memory for RX skbuff array */ |
| 378 | rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize, |
| 379 | sizeof(dma_addr_t), GFP_KERNEL); |
| 380 | if (rx_ring->rx_skbuff_dma == NULL) |
| 381 | goto dmamem_err; |
| 382 | |
| 383 | rx_ring->rx_skbuff = kmalloc_array(rx_rsize, |
| 384 | sizeof(struct sk_buff *), GFP_KERNEL); |
| 385 | if (rx_ring->rx_skbuff == NULL) |
| 386 | goto rxbuff_err; |
| 387 | |
| 388 | /* initialise the buffers */ |
| 389 | for (desc_index = 0; desc_index < rx_rsize; desc_index++) { |
| 390 | struct sxgbe_rx_norm_desc *p; |
| 391 | p = rx_ring->dma_rx + desc_index; |
| 392 | ret = sxgbe_init_rx_buffers(dev, p, desc_index, |
| 393 | bfsize, rx_ring); |
| 394 | if (ret) |
| 395 | goto err_init_rx_buffers; |
| 396 | } |
| 397 | |
| 398 | /* initalise counters */ |
| 399 | rx_ring->cur_rx = 0; |
| 400 | rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize); |
| 401 | priv->dma_buf_sz = bfsize; |
| 402 | |
| 403 | return 0; |
| 404 | |
| 405 | err_init_rx_buffers: |
| 406 | while (--desc_index >= 0) |
| 407 | free_rx_ring(priv->device, rx_ring, desc_index); |
| 408 | kfree(rx_ring->rx_skbuff); |
| 409 | rxbuff_err: |
| 410 | kfree(rx_ring->rx_skbuff_dma); |
| 411 | dmamem_err: |
| 412 | dma_free_coherent(priv->device, |
| 413 | rx_rsize * sizeof(struct sxgbe_rx_norm_desc), |
| 414 | rx_ring->dma_rx, rx_ring->dma_rx_phy); |
| 415 | error: |
| 416 | return -ENOMEM; |
| 417 | } |
| 418 | /** |
| 419 | * free_tx_ring - free the TX descriptor ring |
| 420 | * @dev: net device structure |
| 421 | * @tx_ring: ring to be intialised |
| 422 | * @tx_rsize: ring size |
| 423 | * Description: this function initializes the DMA TX descriptor |
| 424 | */ |
| 425 | void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring, |
| 426 | int tx_rsize) |
| 427 | { |
| 428 | dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc), |
| 429 | tx_ring->dma_tx, tx_ring->dma_tx_phy); |
| 430 | } |
| 431 | |
| 432 | /** |
| 433 | * init_dma_desc_rings - init the RX/TX descriptor rings |
| 434 | * @dev: net device structure |
| 435 | * Description: this function initializes the DMA RX/TX descriptors |
| 436 | * and allocates the socket buffers. It suppors the chained and ring |
| 437 | * modes. |
| 438 | */ |
| 439 | static int init_dma_desc_rings(struct net_device *netd) |
| 440 | { |
| 441 | int queue_num, ret; |
| 442 | struct sxgbe_priv_data *priv = netdev_priv(netd); |
| 443 | int tx_rsize = priv->dma_tx_size; |
| 444 | int rx_rsize = priv->dma_rx_size; |
| 445 | |
| 446 | /* Allocate memory for queue structures and TX descs */ |
| 447 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 448 | ret = init_tx_ring(priv->device, queue_num, |
| 449 | priv->txq[queue_num], tx_rsize); |
| 450 | if (ret) { |
| 451 | dev_err(&netd->dev, "TX DMA ring allocation failed!\n"); |
| 452 | goto txalloc_err; |
| 453 | } |
| 454 | |
| 455 | /* save private pointer in each ring this |
| 456 | * pointer is needed during cleaing TX queue |
| 457 | */ |
| 458 | priv->txq[queue_num]->priv_ptr = priv; |
| 459 | } |
| 460 | |
| 461 | /* Allocate memory for queue structures and RX descs */ |
| 462 | SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { |
| 463 | ret = init_rx_ring(netd, queue_num, |
| 464 | priv->rxq[queue_num], rx_rsize); |
| 465 | if (ret) { |
| 466 | netdev_err(netd, "RX DMA ring allocation failed!!\n"); |
| 467 | goto rxalloc_err; |
| 468 | } |
| 469 | |
| 470 | /* save private pointer in each ring this |
| 471 | * pointer is needed during cleaing TX queue |
| 472 | */ |
| 473 | priv->rxq[queue_num]->priv_ptr = priv; |
| 474 | } |
| 475 | |
| 476 | sxgbe_clear_descriptors(priv); |
| 477 | |
| 478 | return 0; |
| 479 | |
| 480 | txalloc_err: |
| 481 | while (queue_num--) |
| 482 | free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize); |
| 483 | return ret; |
| 484 | |
| 485 | rxalloc_err: |
| 486 | while (queue_num--) |
| 487 | free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize); |
| 488 | return ret; |
| 489 | } |
| 490 | |
| 491 | static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue) |
| 492 | { |
| 493 | int dma_desc; |
| 494 | struct sxgbe_priv_data *priv = txqueue->priv_ptr; |
| 495 | int tx_rsize = priv->dma_tx_size; |
| 496 | |
| 497 | for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) { |
| 498 | struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc; |
| 499 | |
| 500 | if (txqueue->tx_skbuff_dma[dma_desc]) |
| 501 | dma_unmap_single(priv->device, |
| 502 | txqueue->tx_skbuff_dma[dma_desc], |
| 503 | priv->hw->desc->get_tx_len(tdesc), |
| 504 | DMA_TO_DEVICE); |
| 505 | |
| 506 | dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]); |
| 507 | txqueue->tx_skbuff[dma_desc] = NULL; |
| 508 | txqueue->tx_skbuff_dma[dma_desc] = 0; |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | |
| 513 | static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv) |
| 514 | { |
| 515 | int queue_num; |
| 516 | |
| 517 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 518 | struct sxgbe_tx_queue *tqueue = priv->txq[queue_num]; |
| 519 | tx_free_ring_skbufs(tqueue); |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void free_dma_desc_resources(struct sxgbe_priv_data *priv) |
| 524 | { |
| 525 | int queue_num; |
| 526 | int tx_rsize = priv->dma_tx_size; |
| 527 | int rx_rsize = priv->dma_rx_size; |
| 528 | |
| 529 | /* Release the DMA TX buffers */ |
| 530 | dma_free_tx_skbufs(priv); |
| 531 | |
| 532 | /* Release the TX ring memory also */ |
| 533 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 534 | free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize); |
| 535 | } |
| 536 | |
| 537 | /* Release the RX ring memory also */ |
| 538 | SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { |
| 539 | free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize); |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | static int txring_mem_alloc(struct sxgbe_priv_data *priv) |
| 544 | { |
| 545 | int queue_num; |
| 546 | |
| 547 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 548 | priv->txq[queue_num] = devm_kmalloc(priv->device, |
| 549 | sizeof(struct sxgbe_tx_queue), GFP_KERNEL); |
| 550 | if (!priv->txq[queue_num]) |
| 551 | return -ENOMEM; |
| 552 | } |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int rxring_mem_alloc(struct sxgbe_priv_data *priv) |
| 558 | { |
| 559 | int queue_num; |
| 560 | |
| 561 | SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { |
| 562 | priv->rxq[queue_num] = devm_kmalloc(priv->device, |
| 563 | sizeof(struct sxgbe_rx_queue), GFP_KERNEL); |
| 564 | if (!priv->rxq[queue_num]) |
| 565 | return -ENOMEM; |
| 566 | } |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | /** |
| 572 | * sxgbe_mtl_operation_mode - HW MTL operation mode |
| 573 | * @priv: driver private structure |
| 574 | * Description: it sets the MTL operation mode: tx/rx MTL thresholds |
| 575 | * or Store-And-Forward capability. |
| 576 | */ |
| 577 | static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv) |
| 578 | { |
| 579 | int queue_num; |
| 580 | |
| 581 | /* TX/RX threshold control */ |
| 582 | if (likely(priv->plat->force_sf_dma_mode)) { |
| 583 | /* set TC mode for TX QUEUES */ |
| 584 | SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) |
| 585 | priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num, |
| 586 | SXGBE_MTL_SFMODE); |
| 587 | priv->tx_tc = SXGBE_MTL_SFMODE; |
| 588 | |
| 589 | /* set TC mode for RX QUEUES */ |
| 590 | SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) |
| 591 | priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num, |
| 592 | SXGBE_MTL_SFMODE); |
| 593 | priv->rx_tc = SXGBE_MTL_SFMODE; |
| 594 | } else if (unlikely(priv->plat->force_thresh_dma_mode)) { |
| 595 | /* set TC mode for TX QUEUES */ |
| 596 | SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) |
| 597 | priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num, |
| 598 | priv->tx_tc); |
| 599 | /* set TC mode for RX QUEUES */ |
| 600 | SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) |
| 601 | priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num, |
| 602 | priv->rx_tc); |
| 603 | } else { |
| 604 | pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | /** |
| 609 | * sxgbe_tx_queue_clean: |
| 610 | * @priv: driver private structure |
| 611 | * Description: it reclaims resources after transmission completes. |
| 612 | */ |
| 613 | static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue) |
| 614 | { |
| 615 | struct sxgbe_priv_data *priv = tqueue->priv_ptr; |
| 616 | unsigned int tx_rsize = priv->dma_tx_size; |
| 617 | struct netdev_queue *dev_txq; |
| 618 | u8 queue_no = tqueue->queue_no; |
| 619 | |
| 620 | dev_txq = netdev_get_tx_queue(priv->dev, queue_no); |
| 621 | |
| 622 | spin_lock(&tqueue->tx_lock); |
| 623 | |
| 624 | priv->xstats.tx_clean++; |
| 625 | while (tqueue->dirty_tx != tqueue->cur_tx) { |
| 626 | unsigned int entry = tqueue->dirty_tx % tx_rsize; |
| 627 | struct sk_buff *skb = tqueue->tx_skbuff[entry]; |
| 628 | struct sxgbe_tx_norm_desc *p; |
| 629 | |
| 630 | p = tqueue->dma_tx + entry; |
| 631 | |
| 632 | /* Check if the descriptor is owned by the DMA. */ |
| 633 | if (priv->hw->desc->get_tx_owner(p)) |
| 634 | break; |
| 635 | |
| 636 | if (netif_msg_tx_done(priv)) |
| 637 | pr_debug("%s: curr %d, dirty %d\n", |
| 638 | __func__, tqueue->cur_tx, tqueue->dirty_tx); |
| 639 | |
| 640 | if (likely(tqueue->tx_skbuff_dma[entry])) { |
| 641 | dma_unmap_single(priv->device, |
| 642 | tqueue->tx_skbuff_dma[entry], |
| 643 | priv->hw->desc->get_tx_len(p), |
| 644 | DMA_TO_DEVICE); |
| 645 | tqueue->tx_skbuff_dma[entry] = 0; |
| 646 | } |
| 647 | |
| 648 | if (likely(skb)) { |
| 649 | dev_kfree_skb(skb); |
| 650 | tqueue->tx_skbuff[entry] = NULL; |
| 651 | } |
| 652 | |
| 653 | priv->hw->desc->release_tx_desc(p); |
| 654 | |
| 655 | tqueue->dirty_tx++; |
| 656 | } |
| 657 | |
| 658 | /* wake up queue */ |
| 659 | if (unlikely(netif_tx_queue_stopped(dev_txq) && |
| 660 | sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) { |
| 661 | netif_tx_lock(priv->dev); |
| 662 | if (netif_tx_queue_stopped(dev_txq) && |
| 663 | sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv)) { |
| 664 | if (netif_msg_tx_done(priv)) |
| 665 | pr_debug("%s: restart transmit\n", __func__); |
| 666 | netif_tx_wake_queue(dev_txq); |
| 667 | } |
| 668 | netif_tx_unlock(priv->dev); |
| 669 | } |
| 670 | |
| 671 | spin_unlock(&tqueue->tx_lock); |
| 672 | } |
| 673 | |
| 674 | /** |
| 675 | * sxgbe_tx_clean: |
| 676 | * @priv: driver private structure |
| 677 | * Description: it reclaims resources after transmission completes. |
| 678 | */ |
| 679 | static void sxgbe_tx_all_clean(struct sxgbe_priv_data *priv) |
| 680 | { |
| 681 | u8 queue_num; |
| 682 | |
| 683 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 684 | struct sxgbe_tx_queue *tqueue = priv->txq[queue_num]; |
| 685 | |
| 686 | sxgbe_tx_queue_clean(tqueue); |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | /** |
| 691 | * sxgbe_restart_tx_queue: irq tx error mng function |
| 692 | * @priv: driver private structure |
| 693 | * Description: it cleans the descriptors and restarts the transmission |
| 694 | * in case of errors. |
| 695 | */ |
| 696 | static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num) |
| 697 | { |
| 698 | struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num]; |
| 699 | struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev, |
| 700 | queue_num); |
| 701 | |
| 702 | /* stop the queue */ |
| 703 | netif_tx_stop_queue(dev_txq); |
| 704 | |
| 705 | /* stop the tx dma */ |
| 706 | priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num); |
| 707 | |
| 708 | /* free the skbuffs of the ring */ |
| 709 | tx_free_ring_skbufs(tx_ring); |
| 710 | |
| 711 | /* initalise counters */ |
| 712 | tx_ring->cur_tx = 0; |
| 713 | tx_ring->dirty_tx = 0; |
| 714 | |
| 715 | /* start the tx dma */ |
| 716 | priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num); |
| 717 | |
| 718 | priv->dev->stats.tx_errors++; |
| 719 | |
| 720 | /* wakeup the queue */ |
| 721 | netif_tx_wake_queue(dev_txq); |
| 722 | } |
| 723 | |
| 724 | /** |
| 725 | * sxgbe_reset_all_tx_queues: irq tx error mng function |
| 726 | * @priv: driver private structure |
| 727 | * Description: it cleans all the descriptors and |
| 728 | * restarts the transmission on all queues in case of errors. |
| 729 | */ |
| 730 | static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv) |
| 731 | { |
| 732 | int queue_num; |
| 733 | |
| 734 | /* On TX timeout of net device, resetting of all queues |
| 735 | * may not be proper way, revisit this later if needed |
| 736 | */ |
| 737 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) |
| 738 | sxgbe_restart_tx_queue(priv, queue_num); |
| 739 | } |
| 740 | |
| 741 | /** |
| 742 | * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register. |
| 743 | * @priv: driver private structure |
| 744 | * Description: |
| 745 | * new GMAC chip generations have a new register to indicate the |
| 746 | * presence of the optional feature/functions. |
| 747 | * This can be also used to override the value passed through the |
| 748 | * platform and necessary for old MAC10/100 and GMAC chips. |
| 749 | */ |
| 750 | static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv) |
| 751 | { |
| 752 | int rval = 0; |
| 753 | struct sxgbe_hw_features *features = &priv->hw_cap; |
| 754 | |
| 755 | /* Read First Capability Register CAP[0] */ |
| 756 | rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0); |
| 757 | if (rval) { |
| 758 | features->pmt_remote_wake_up = |
| 759 | SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval); |
| 760 | features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval); |
| 761 | features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval); |
| 762 | features->tx_csum_offload = |
| 763 | SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval); |
| 764 | features->rx_csum_offload = |
| 765 | SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval); |
| 766 | features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval); |
| 767 | features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval); |
| 768 | features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval); |
| 769 | } |
| 770 | |
| 771 | /* Read First Capability Register CAP[1] */ |
| 772 | rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1); |
| 773 | if (rval) { |
| 774 | features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval); |
| 775 | features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval); |
| 776 | features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval); |
| 777 | features->dcb_enable = SXGBE_HW_FEAT_DCB(rval); |
| 778 | features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval); |
| 779 | features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval); |
| 780 | features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval); |
| 781 | features->rss_enable = SXGBE_HW_FEAT_RSS(rval); |
| 782 | features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval); |
| 783 | features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval); |
| 784 | } |
| 785 | |
| 786 | /* Read First Capability Register CAP[2] */ |
| 787 | rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2); |
| 788 | if (rval) { |
| 789 | features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval); |
| 790 | features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval); |
| 791 | features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval); |
| 792 | features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval); |
| 793 | features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval); |
| 794 | features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval); |
| 795 | } |
| 796 | |
| 797 | return rval; |
| 798 | } |
| 799 | |
| 800 | /** |
| 801 | * sxgbe_check_ether_addr: check if the MAC addr is valid |
| 802 | * @priv: driver private structure |
| 803 | * Description: |
| 804 | * it is to verify if the MAC address is valid, in case of failures it |
| 805 | * generates a random MAC address |
| 806 | */ |
| 807 | static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv) |
| 808 | { |
| 809 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
| 810 | priv->hw->mac->get_umac_addr((void __iomem *) |
| 811 | priv->ioaddr, |
| 812 | priv->dev->dev_addr, 0); |
| 813 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
| 814 | eth_hw_addr_random(priv->dev); |
| 815 | } |
| 816 | dev_info(priv->device, "device MAC address %pM\n", |
| 817 | priv->dev->dev_addr); |
| 818 | } |
| 819 | |
| 820 | /** |
| 821 | * sxgbe_init_dma_engine: DMA init. |
| 822 | * @priv: driver private structure |
| 823 | * Description: |
| 824 | * It inits the DMA invoking the specific SXGBE callback. |
| 825 | * Some DMA parameters can be passed from the platform; |
| 826 | * in case of these are not passed a default is kept for the MAC or GMAC. |
| 827 | */ |
| 828 | static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv) |
| 829 | { |
| 830 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0; |
| 831 | int queue_num; |
| 832 | |
| 833 | if (priv->plat->dma_cfg) { |
| 834 | pbl = priv->plat->dma_cfg->pbl; |
| 835 | fixed_burst = priv->plat->dma_cfg->fixed_burst; |
| 836 | burst_map = priv->plat->dma_cfg->burst_map; |
| 837 | } |
| 838 | |
| 839 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) |
| 840 | priv->hw->dma->cha_init(priv->ioaddr, queue_num, |
| 841 | fixed_burst, pbl, |
| 842 | (priv->txq[queue_num])->dma_tx_phy, |
| 843 | (priv->rxq[queue_num])->dma_rx_phy, |
| 844 | priv->dma_tx_size, priv->dma_rx_size); |
| 845 | |
| 846 | return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map); |
| 847 | } |
| 848 | |
| 849 | /** |
| 850 | * sxgbe_init_mtl_engine: MTL init. |
| 851 | * @priv: driver private structure |
| 852 | * Description: |
| 853 | * It inits the MTL invoking the specific SXGBE callback. |
| 854 | */ |
| 855 | static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv) |
| 856 | { |
| 857 | int queue_num; |
| 858 | |
| 859 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 860 | priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num, |
| 861 | priv->hw_cap.tx_mtl_qsize); |
| 862 | priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num); |
| 863 | } |
| 864 | } |
| 865 | |
| 866 | /** |
| 867 | * sxgbe_disable_mtl_engine: MTL disable. |
| 868 | * @priv: driver private structure |
| 869 | * Description: |
| 870 | * It disables the MTL queues by invoking the specific SXGBE callback. |
| 871 | */ |
| 872 | static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv) |
| 873 | { |
| 874 | int queue_num; |
| 875 | |
| 876 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) |
| 877 | priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num); |
| 878 | } |
| 879 | |
| 880 | |
| 881 | /** |
| 882 | * sxgbe_tx_timer: mitigation sw timer for tx. |
| 883 | * @data: data pointer |
| 884 | * Description: |
| 885 | * This is the timer handler to directly invoke the sxgbe_tx_clean. |
| 886 | */ |
| 887 | static void sxgbe_tx_timer(unsigned long data) |
| 888 | { |
| 889 | struct sxgbe_tx_queue *p = (struct sxgbe_tx_queue *)data; |
| 890 | sxgbe_tx_queue_clean(p); |
| 891 | } |
| 892 | |
| 893 | /** |
| 894 | * sxgbe_init_tx_coalesce: init tx mitigation options. |
| 895 | * @priv: driver private structure |
| 896 | * Description: |
| 897 | * This inits the transmit coalesce parameters: i.e. timer rate, |
| 898 | * timer handler and default threshold used for enabling the |
| 899 | * interrupt on completion bit. |
| 900 | */ |
| 901 | static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv) |
| 902 | { |
| 903 | u8 queue_num; |
| 904 | |
| 905 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 906 | struct sxgbe_tx_queue *p = priv->txq[queue_num]; |
| 907 | p->tx_coal_frames = SXGBE_TX_FRAMES; |
| 908 | p->tx_coal_timer = SXGBE_COAL_TX_TIMER; |
| 909 | init_timer(&p->txtimer); |
| 910 | p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer); |
| 911 | p->txtimer.data = (unsigned long)&priv->txq[queue_num]; |
| 912 | p->txtimer.function = sxgbe_tx_timer; |
| 913 | add_timer(&p->txtimer); |
| 914 | } |
| 915 | } |
| 916 | |
| 917 | static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv) |
| 918 | { |
| 919 | u8 queue_num; |
| 920 | |
| 921 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 922 | struct sxgbe_tx_queue *p = priv->txq[queue_num]; |
| 923 | del_timer_sync(&p->txtimer); |
| 924 | } |
| 925 | } |
| 926 | |
| 927 | /** |
| 928 | * sxgbe_open - open entry point of the driver |
| 929 | * @dev : pointer to the device structure. |
| 930 | * Description: |
| 931 | * This function is the open entry point of the driver. |
| 932 | * Return value: |
| 933 | * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| 934 | * file on failure. |
| 935 | */ |
| 936 | static int sxgbe_open(struct net_device *dev) |
| 937 | { |
| 938 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 939 | int ret, queue_num; |
| 940 | |
| 941 | clk_prepare_enable(priv->sxgbe_clk); |
| 942 | |
| 943 | sxgbe_check_ether_addr(priv); |
| 944 | |
| 945 | /* Init the phy */ |
| 946 | ret = sxgbe_init_phy(dev); |
| 947 | if (ret) { |
| 948 | netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n", |
| 949 | __func__, ret); |
| 950 | goto phy_error; |
| 951 | } |
| 952 | |
| 953 | /* Create and initialize the TX/RX descriptors chains. */ |
| 954 | priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE); |
| 955 | priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE); |
| 956 | priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE); |
| 957 | priv->tx_tc = TC_DEFAULT; |
| 958 | priv->rx_tc = TC_DEFAULT; |
| 959 | init_dma_desc_rings(dev); |
| 960 | |
| 961 | /* DMA initialization and SW reset */ |
| 962 | ret = sxgbe_init_dma_engine(priv); |
| 963 | if (ret < 0) { |
| 964 | netdev_err(dev, "%s: DMA initialization failed\n", __func__); |
| 965 | goto init_error; |
| 966 | } |
| 967 | |
| 968 | /* MTL initialization */ |
| 969 | sxgbe_init_mtl_engine(priv); |
| 970 | |
| 971 | /* Copy the MAC addr into the HW */ |
| 972 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
| 973 | |
| 974 | /* Initialize the MAC Core */ |
| 975 | priv->hw->mac->core_init(priv->ioaddr); |
| 976 | |
| 977 | /* Request the IRQ lines */ |
| 978 | ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt, |
| 979 | IRQF_SHARED, dev->name, dev); |
| 980 | if (unlikely(ret < 0)) { |
| 981 | netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n", |
| 982 | __func__, priv->irq, ret); |
| 983 | goto init_error; |
| 984 | } |
| 985 | |
| 986 | /* Request TX DMA irq lines */ |
| 987 | SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { |
| 988 | ret = devm_request_irq(priv->device, |
| 989 | (priv->txq[queue_num])->irq_no, |
| 990 | sxgbe_tx_interrupt, 0, |
| 991 | dev->name, priv->txq[queue_num]); |
| 992 | if (unlikely(ret < 0)) { |
| 993 | netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n", |
| 994 | __func__, priv->irq, ret); |
| 995 | goto init_error; |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | /* Request RX DMA irq lines */ |
| 1000 | SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { |
| 1001 | ret = devm_request_irq(priv->device, |
| 1002 | (priv->rxq[queue_num])->irq_no, |
| 1003 | sxgbe_rx_interrupt, 0, |
| 1004 | dev->name, priv->rxq[queue_num]); |
| 1005 | if (unlikely(ret < 0)) { |
| 1006 | netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n", |
| 1007 | __func__, priv->irq, ret); |
| 1008 | goto init_error; |
| 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | /* Enable the MAC Rx/Tx */ |
| 1013 | priv->hw->mac->enable_tx(priv->ioaddr, true); |
| 1014 | priv->hw->mac->enable_rx(priv->ioaddr, true); |
| 1015 | |
| 1016 | /* Set the HW DMA mode and the COE */ |
| 1017 | sxgbe_mtl_operation_mode(priv); |
| 1018 | |
| 1019 | /* Extra statistics */ |
| 1020 | memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats)); |
| 1021 | |
| 1022 | priv->xstats.tx_threshold = priv->tx_tc; |
| 1023 | priv->xstats.rx_threshold = priv->rx_tc; |
| 1024 | |
| 1025 | /* Start the ball rolling... */ |
| 1026 | netdev_dbg(dev, "DMA RX/TX processes started...\n"); |
| 1027 | priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES); |
| 1028 | priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES); |
| 1029 | |
| 1030 | if (priv->phydev) |
| 1031 | phy_start(priv->phydev); |
| 1032 | |
| 1033 | /* initalise TX coalesce parameters */ |
| 1034 | sxgbe_tx_init_coalesce(priv); |
| 1035 | |
| 1036 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
| 1037 | priv->rx_riwt = SXGBE_MAX_DMA_RIWT; |
| 1038 | priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT); |
| 1039 | } |
| 1040 | |
| 1041 | napi_enable(&priv->napi); |
| 1042 | netif_start_queue(dev); |
| 1043 | |
| 1044 | return 0; |
| 1045 | |
| 1046 | init_error: |
| 1047 | free_dma_desc_resources(priv); |
| 1048 | if (priv->phydev) |
| 1049 | phy_disconnect(priv->phydev); |
| 1050 | phy_error: |
| 1051 | clk_disable_unprepare(priv->sxgbe_clk); |
| 1052 | |
| 1053 | return ret; |
| 1054 | } |
| 1055 | |
| 1056 | /** |
| 1057 | * sxgbe_release - close entry point of the driver |
| 1058 | * @dev : device pointer. |
| 1059 | * Description: |
| 1060 | * This is the stop entry point of the driver. |
| 1061 | */ |
| 1062 | static int sxgbe_release(struct net_device *dev) |
| 1063 | { |
| 1064 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1065 | |
| 1066 | /* Stop and disconnect the PHY */ |
| 1067 | if (priv->phydev) { |
| 1068 | phy_stop(priv->phydev); |
| 1069 | phy_disconnect(priv->phydev); |
| 1070 | priv->phydev = NULL; |
| 1071 | } |
| 1072 | |
| 1073 | netif_tx_stop_all_queues(dev); |
| 1074 | |
| 1075 | napi_disable(&priv->napi); |
| 1076 | |
| 1077 | /* delete TX timers */ |
| 1078 | sxgbe_tx_del_timer(priv); |
| 1079 | |
| 1080 | /* Stop TX/RX DMA and clear the descriptors */ |
| 1081 | priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES); |
| 1082 | priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES); |
| 1083 | |
| 1084 | /* disable MTL queue */ |
| 1085 | sxgbe_disable_mtl_engine(priv); |
| 1086 | |
| 1087 | /* Release and free the Rx/Tx resources */ |
| 1088 | free_dma_desc_resources(priv); |
| 1089 | |
| 1090 | /* Disable the MAC Rx/Tx */ |
| 1091 | priv->hw->mac->enable_tx(priv->ioaddr, false); |
| 1092 | priv->hw->mac->enable_rx(priv->ioaddr, false); |
| 1093 | |
| 1094 | clk_disable_unprepare(priv->sxgbe_clk); |
| 1095 | |
| 1096 | return 0; |
| 1097 | } |
| 1098 | |
| 1099 | /** |
| 1100 | * sxgbe_xmit: Tx entry point of the driver |
| 1101 | * @skb : the socket buffer |
| 1102 | * @dev : device pointer |
| 1103 | * Description : this is the tx entry point of the driver. |
| 1104 | * It programs the chain or the ring and supports oversized frames |
| 1105 | * and SG feature. |
| 1106 | */ |
| 1107 | static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev) |
| 1108 | { |
| 1109 | unsigned int entry, frag_num; |
| 1110 | struct netdev_queue *dev_txq; |
| 1111 | unsigned txq_index = skb_get_queue_mapping(skb); |
| 1112 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1113 | unsigned int tx_rsize = priv->dma_tx_size; |
| 1114 | struct sxgbe_tx_queue *tqueue = priv->txq[txq_index]; |
| 1115 | struct sxgbe_tx_norm_desc *tx_desc, *first_desc; |
| 1116 | int nr_frags = skb_shinfo(skb)->nr_frags; |
| 1117 | int no_pagedlen = skb_headlen(skb); |
| 1118 | int is_jumbo = 0; |
| 1119 | |
| 1120 | /* get the TX queue handle */ |
| 1121 | dev_txq = netdev_get_tx_queue(dev, txq_index); |
| 1122 | |
| 1123 | /* get the spinlock */ |
| 1124 | spin_lock(&tqueue->tx_lock); |
| 1125 | |
| 1126 | if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) { |
| 1127 | if (!netif_tx_queue_stopped(dev_txq)) { |
| 1128 | netif_tx_stop_queue(dev_txq); |
| 1129 | netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n", |
| 1130 | __func__, txq_index); |
| 1131 | } |
| 1132 | /* release the spin lock in case of BUSY */ |
| 1133 | spin_unlock(&tqueue->tx_lock); |
| 1134 | return NETDEV_TX_BUSY; |
| 1135 | } |
| 1136 | |
| 1137 | entry = tqueue->cur_tx % tx_rsize; |
| 1138 | tx_desc = tqueue->dma_tx + entry; |
| 1139 | |
| 1140 | first_desc = tx_desc; |
| 1141 | |
| 1142 | /* save the skb address */ |
| 1143 | tqueue->tx_skbuff[entry] = skb; |
| 1144 | |
| 1145 | if (!is_jumbo) { |
| 1146 | tx_desc->tdes01 = dma_map_single(priv->device, skb->data, |
| 1147 | no_pagedlen, DMA_TO_DEVICE); |
| 1148 | if (dma_mapping_error(priv->device, tx_desc->tdes01)) |
| 1149 | pr_err("%s: TX dma mapping failed!!\n", __func__); |
| 1150 | |
| 1151 | priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen, |
| 1152 | no_pagedlen, 0); |
| 1153 | } |
| 1154 | |
| 1155 | for (frag_num = 0; frag_num < nr_frags; frag_num++) { |
| 1156 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num]; |
| 1157 | int len = skb_frag_size(frag); |
| 1158 | |
| 1159 | entry = (++tqueue->cur_tx) % tx_rsize; |
| 1160 | tx_desc = tqueue->dma_tx + entry; |
| 1161 | tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len, |
| 1162 | DMA_TO_DEVICE); |
| 1163 | |
| 1164 | tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01; |
| 1165 | tqueue->tx_skbuff[entry] = NULL; |
| 1166 | |
| 1167 | /* prepare the descriptor */ |
| 1168 | priv->hw->desc->prepare_tx_desc(tx_desc, 0, len, |
| 1169 | len, 0); |
| 1170 | /* memory barrier to flush descriptor */ |
| 1171 | wmb(); |
| 1172 | |
| 1173 | /* set the owner */ |
| 1174 | priv->hw->desc->set_tx_owner(tx_desc); |
| 1175 | } |
| 1176 | |
| 1177 | /* close the descriptors */ |
| 1178 | priv->hw->desc->close_tx_desc(tx_desc); |
| 1179 | |
| 1180 | /* memory barrier to flush descriptor */ |
| 1181 | wmb(); |
| 1182 | |
| 1183 | tqueue->tx_count_frames += nr_frags + 1; |
| 1184 | if (tqueue->tx_count_frames > tqueue->tx_coal_frames) { |
| 1185 | priv->hw->desc->clear_tx_ic(tx_desc); |
| 1186 | priv->xstats.tx_reset_ic_bit++; |
| 1187 | mod_timer(&tqueue->txtimer, |
| 1188 | SXGBE_COAL_TIMER(tqueue->tx_coal_timer)); |
| 1189 | } else { |
| 1190 | tqueue->tx_count_frames = 0; |
| 1191 | } |
| 1192 | |
| 1193 | /* set owner for first desc */ |
| 1194 | priv->hw->desc->set_tx_owner(first_desc); |
| 1195 | |
| 1196 | /* memory barrier to flush descriptor */ |
| 1197 | wmb(); |
| 1198 | |
| 1199 | tqueue->cur_tx++; |
| 1200 | |
| 1201 | /* display current ring */ |
| 1202 | netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n", |
| 1203 | __func__, tqueue->cur_tx % tx_rsize, |
| 1204 | tqueue->dirty_tx % tx_rsize, entry, |
| 1205 | first_desc, nr_frags); |
| 1206 | |
| 1207 | if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) { |
| 1208 | netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n", |
| 1209 | __func__); |
| 1210 | netif_tx_stop_queue(dev_txq); |
| 1211 | } |
| 1212 | |
| 1213 | dev->stats.tx_bytes += skb->len; |
| 1214 | |
| 1215 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
| 1216 | tqueue->hwts_tx_en)) { |
| 1217 | /* declare that device is doing timestamping */ |
| 1218 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
| 1219 | priv->hw->desc->tx_enable_tstamp(first_desc); |
| 1220 | } |
| 1221 | |
| 1222 | if (!tqueue->hwts_tx_en) |
| 1223 | skb_tx_timestamp(skb); |
| 1224 | |
| 1225 | priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index); |
| 1226 | |
| 1227 | spin_unlock(&tqueue->tx_lock); |
| 1228 | |
| 1229 | return NETDEV_TX_OK; |
| 1230 | } |
| 1231 | |
| 1232 | /** |
| 1233 | * sxgbe_rx_refill: refill used skb preallocated buffers |
| 1234 | * @priv: driver private structure |
| 1235 | * Description : this is to reallocate the skb for the reception process |
| 1236 | * that is based on zero-copy. |
| 1237 | */ |
| 1238 | static void sxgbe_rx_refill(struct sxgbe_priv_data *priv) |
| 1239 | { |
| 1240 | unsigned int rxsize = priv->dma_rx_size; |
| 1241 | int bfsize = priv->dma_buf_sz; |
| 1242 | u8 qnum = priv->cur_rx_qnum; |
| 1243 | |
| 1244 | for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0; |
| 1245 | priv->rxq[qnum]->dirty_rx++) { |
| 1246 | unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize; |
| 1247 | struct sxgbe_rx_norm_desc *p; |
| 1248 | |
| 1249 | p = priv->rxq[qnum]->dma_rx + entry; |
| 1250 | |
| 1251 | if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) { |
| 1252 | struct sk_buff *skb; |
| 1253 | |
| 1254 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
| 1255 | |
| 1256 | if (unlikely(skb == NULL)) |
| 1257 | break; |
| 1258 | |
| 1259 | priv->rxq[qnum]->rx_skbuff[entry] = skb; |
| 1260 | priv->rxq[qnum]->rx_skbuff_dma[entry] = |
| 1261 | dma_map_single(priv->device, skb->data, bfsize, |
| 1262 | DMA_FROM_DEVICE); |
| 1263 | |
| 1264 | p->rdes23.rx_rd_des23.buf2_addr = |
| 1265 | priv->rxq[qnum]->rx_skbuff_dma[entry]; |
| 1266 | } |
| 1267 | |
| 1268 | /* Added memory barrier for RX descriptor modification */ |
| 1269 | wmb(); |
| 1270 | priv->hw->desc->set_rx_owner(p); |
| 1271 | /* Added memory barrier for RX descriptor modification */ |
| 1272 | wmb(); |
| 1273 | } |
| 1274 | } |
| 1275 | |
| 1276 | /** |
| 1277 | * sxgbe_rx: receive the frames from the remote host |
| 1278 | * @priv: driver private structure |
| 1279 | * @limit: napi bugget. |
| 1280 | * Description : this the function called by the napi poll method. |
| 1281 | * It gets all the frames inside the ring. |
| 1282 | */ |
| 1283 | static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit) |
| 1284 | { |
| 1285 | u8 qnum = priv->cur_rx_qnum; |
| 1286 | unsigned int rxsize = priv->dma_rx_size; |
| 1287 | unsigned int entry = priv->rxq[qnum]->cur_rx; |
| 1288 | unsigned int next_entry = 0; |
| 1289 | unsigned int count = 0; |
| 1290 | |
| 1291 | while (count < limit) { |
| 1292 | struct sxgbe_rx_norm_desc *p; |
| 1293 | struct sk_buff *skb; |
| 1294 | int frame_len; |
| 1295 | |
| 1296 | p = priv->rxq[qnum]->dma_rx + entry; |
| 1297 | |
| 1298 | if (priv->hw->desc->get_rx_owner(p)) |
| 1299 | break; |
| 1300 | |
| 1301 | count++; |
| 1302 | |
| 1303 | next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize; |
| 1304 | prefetch(priv->rxq[qnum]->dma_rx + next_entry); |
| 1305 | |
| 1306 | /*TO DO read the status of the incoming frame */ |
| 1307 | |
| 1308 | skb = priv->rxq[qnum]->rx_skbuff[entry]; |
| 1309 | |
| 1310 | if (unlikely(!skb)) |
| 1311 | netdev_err(priv->dev, "rx descriptor is not consistent\n"); |
| 1312 | |
| 1313 | prefetch(skb->data - NET_IP_ALIGN); |
| 1314 | priv->rxq[qnum]->rx_skbuff[entry] = NULL; |
| 1315 | |
| 1316 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
| 1317 | |
| 1318 | skb_put(skb, frame_len); |
| 1319 | |
| 1320 | netif_receive_skb(skb); |
| 1321 | |
| 1322 | entry = next_entry; |
| 1323 | } |
| 1324 | |
| 1325 | sxgbe_rx_refill(priv); |
| 1326 | |
| 1327 | return count; |
| 1328 | } |
| 1329 | |
| 1330 | /** |
| 1331 | * sxgbe_poll - sxgbe poll method (NAPI) |
| 1332 | * @napi : pointer to the napi structure. |
| 1333 | * @budget : maximum number of packets that the current CPU can receive from |
| 1334 | * all interfaces. |
| 1335 | * Description : |
| 1336 | * To look at the incoming frames and clear the tx resources. |
| 1337 | */ |
| 1338 | static int sxgbe_poll(struct napi_struct *napi, int budget) |
| 1339 | { |
| 1340 | struct sxgbe_priv_data *priv = container_of(napi, |
| 1341 | struct sxgbe_priv_data, napi); |
| 1342 | int work_done = 0; |
| 1343 | u8 qnum = priv->cur_rx_qnum; |
| 1344 | |
| 1345 | priv->xstats.napi_poll++; |
| 1346 | /* first, clean the tx queues */ |
| 1347 | sxgbe_tx_all_clean(priv); |
| 1348 | |
| 1349 | work_done = sxgbe_rx(priv, budget); |
| 1350 | if (work_done < budget) { |
| 1351 | napi_complete(napi); |
| 1352 | priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum); |
| 1353 | } |
| 1354 | |
| 1355 | return work_done; |
| 1356 | } |
| 1357 | |
| 1358 | /** |
| 1359 | * sxgbe_tx_timeout |
| 1360 | * @dev : Pointer to net device structure |
| 1361 | * Description: this function is called when a packet transmission fails to |
| 1362 | * complete within a reasonable time. The driver will mark the error in the |
| 1363 | * netdev structure and arrange for the device to be reset to a sane state |
| 1364 | * in order to transmit a new packet. |
| 1365 | */ |
| 1366 | static void sxgbe_tx_timeout(struct net_device *dev) |
| 1367 | { |
| 1368 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1369 | |
| 1370 | sxgbe_reset_all_tx_queues(priv); |
| 1371 | } |
| 1372 | |
| 1373 | /** |
| 1374 | * sxgbe_common_interrupt - main ISR |
| 1375 | * @irq: interrupt number. |
| 1376 | * @dev_id: to pass the net device pointer. |
| 1377 | * Description: this is the main driver interrupt service routine. |
| 1378 | * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI |
| 1379 | * interrupts. |
| 1380 | */ |
| 1381 | static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id) |
| 1382 | { |
| 1383 | return IRQ_HANDLED; |
| 1384 | } |
| 1385 | |
| 1386 | /** |
| 1387 | * sxgbe_tx_interrupt - TX DMA ISR |
| 1388 | * @irq: interrupt number. |
| 1389 | * @dev_id: to pass the net device pointer. |
| 1390 | * Description: this is the tx dma interrupt service routine. |
| 1391 | */ |
| 1392 | static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id) |
| 1393 | { |
| 1394 | int status; |
| 1395 | struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id; |
| 1396 | struct sxgbe_priv_data *priv = txq->priv_ptr; |
| 1397 | |
| 1398 | /* get the channel status */ |
| 1399 | status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no, |
| 1400 | &priv->xstats); |
| 1401 | /* check for normal path */ |
| 1402 | if (likely((status & handle_tx))) |
| 1403 | napi_schedule(&priv->napi); |
| 1404 | |
| 1405 | /* check for unrecoverable error */ |
| 1406 | if (unlikely((status & tx_hard_error))) |
| 1407 | sxgbe_restart_tx_queue(priv, txq->queue_no); |
| 1408 | |
| 1409 | /* check for TC configuration change */ |
| 1410 | if (unlikely((status & tx_bump_tc) && |
| 1411 | (priv->tx_tc != SXGBE_MTL_SFMODE) && |
| 1412 | (priv->tx_tc < 512))) { |
| 1413 | /* step of TX TC is 32 till 128, otherwise 64 */ |
| 1414 | priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64; |
| 1415 | priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, |
| 1416 | txq->queue_no, priv->tx_tc); |
| 1417 | priv->xstats.tx_threshold = priv->tx_tc; |
| 1418 | } |
| 1419 | |
| 1420 | return IRQ_HANDLED; |
| 1421 | } |
| 1422 | |
| 1423 | /** |
| 1424 | * sxgbe_rx_interrupt - RX DMA ISR |
| 1425 | * @irq: interrupt number. |
| 1426 | * @dev_id: to pass the net device pointer. |
| 1427 | * Description: this is the rx dma interrupt service routine. |
| 1428 | */ |
| 1429 | static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id) |
| 1430 | { |
| 1431 | int status; |
| 1432 | struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id; |
| 1433 | struct sxgbe_priv_data *priv = rxq->priv_ptr; |
| 1434 | |
| 1435 | /* get the channel status */ |
| 1436 | status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no, |
| 1437 | &priv->xstats); |
| 1438 | |
| 1439 | if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) { |
| 1440 | priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no); |
| 1441 | __napi_schedule(&priv->napi); |
| 1442 | } |
| 1443 | |
| 1444 | /* check for TC configuration change */ |
| 1445 | if (unlikely((status & rx_bump_tc) && |
| 1446 | (priv->rx_tc != SXGBE_MTL_SFMODE) && |
| 1447 | (priv->rx_tc < 128))) { |
| 1448 | /* step of TC is 32 */ |
| 1449 | priv->rx_tc += 32; |
| 1450 | priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, |
| 1451 | rxq->queue_no, priv->rx_tc); |
| 1452 | priv->xstats.rx_threshold = priv->rx_tc; |
| 1453 | } |
| 1454 | |
| 1455 | return IRQ_HANDLED; |
| 1456 | } |
| 1457 | |
| 1458 | static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi) |
| 1459 | { |
| 1460 | u64 val = readl(ioaddr + reg_lo); |
| 1461 | |
| 1462 | val |= ((u64)readl(ioaddr + reg_hi)) << 32; |
| 1463 | |
| 1464 | return val; |
| 1465 | } |
| 1466 | |
| 1467 | |
| 1468 | /* sxgbe_get_stats64 - entry point to see statistical information of device |
| 1469 | * @dev : device pointer. |
| 1470 | * @stats : pointer to hold all the statistical information of device. |
| 1471 | * Description: |
| 1472 | * This function is a driver entry point whenever ifconfig command gets |
| 1473 | * executed to see device statistics. Statistics are number of |
| 1474 | * bytes sent or received, errors occured etc. |
| 1475 | * Return value: |
| 1476 | * This function returns various statistical information of device. |
| 1477 | */ |
| 1478 | static struct rtnl_link_stats64 *sxgbe_get_stats64(struct net_device *dev, |
| 1479 | struct rtnl_link_stats64 *stats) |
| 1480 | { |
| 1481 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1482 | void __iomem *ioaddr = priv->ioaddr; |
| 1483 | u64 count; |
| 1484 | |
| 1485 | spin_lock(&priv->stats_lock); |
| 1486 | /* Freeze the counter registers before reading value otherwise it may |
| 1487 | * get updated by hardware while we are reading them |
| 1488 | */ |
| 1489 | writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG); |
| 1490 | |
| 1491 | stats->rx_bytes = sxgbe_get_stat64(ioaddr, |
| 1492 | SXGBE_MMC_RXOCTETLO_GCNT_REG, |
| 1493 | SXGBE_MMC_RXOCTETHI_GCNT_REG); |
| 1494 | |
| 1495 | stats->rx_packets = sxgbe_get_stat64(ioaddr, |
| 1496 | SXGBE_MMC_RXFRAMELO_GBCNT_REG, |
| 1497 | SXGBE_MMC_RXFRAMEHI_GBCNT_REG); |
| 1498 | |
| 1499 | stats->multicast = sxgbe_get_stat64(ioaddr, |
| 1500 | SXGBE_MMC_RXMULTILO_GCNT_REG, |
| 1501 | SXGBE_MMC_RXMULTIHI_GCNT_REG); |
| 1502 | |
| 1503 | stats->rx_crc_errors = sxgbe_get_stat64(ioaddr, |
| 1504 | SXGBE_MMC_RXCRCERRLO_REG, |
| 1505 | SXGBE_MMC_RXCRCERRHI_REG); |
| 1506 | |
| 1507 | stats->rx_length_errors = sxgbe_get_stat64(ioaddr, |
| 1508 | SXGBE_MMC_RXLENERRLO_REG, |
| 1509 | SXGBE_MMC_RXLENERRHI_REG); |
| 1510 | |
| 1511 | stats->rx_missed_errors = sxgbe_get_stat64(ioaddr, |
| 1512 | SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG, |
| 1513 | SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG); |
| 1514 | |
| 1515 | stats->tx_bytes = sxgbe_get_stat64(ioaddr, |
| 1516 | SXGBE_MMC_TXOCTETLO_GCNT_REG, |
| 1517 | SXGBE_MMC_TXOCTETHI_GCNT_REG); |
| 1518 | |
| 1519 | count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG, |
| 1520 | SXGBE_MMC_TXFRAMEHI_GBCNT_REG); |
| 1521 | |
| 1522 | stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG, |
| 1523 | SXGBE_MMC_TXFRAMEHI_GCNT_REG); |
| 1524 | stats->tx_errors = count - stats->tx_errors; |
| 1525 | stats->tx_packets = count; |
| 1526 | stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG, |
| 1527 | SXGBE_MMC_TXUFLWHI_GBCNT_REG); |
| 1528 | writel(0, ioaddr + SXGBE_MMC_CTL_REG); |
| 1529 | spin_unlock(&priv->stats_lock); |
| 1530 | |
| 1531 | return stats; |
| 1532 | } |
| 1533 | |
| 1534 | /* sxgbe_set_features - entry point to set offload features of the device. |
| 1535 | * @dev : device pointer. |
| 1536 | * @features : features which are required to be set. |
| 1537 | * Description: |
| 1538 | * This function is a driver entry point and called by Linux kernel whenever |
| 1539 | * any device features are set or reset by user. |
| 1540 | * Return value: |
| 1541 | * This function returns 0 after setting or resetting device features. |
| 1542 | */ |
| 1543 | static int sxgbe_set_features(struct net_device *dev, |
| 1544 | netdev_features_t features) |
| 1545 | { |
| 1546 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1547 | netdev_features_t changed = dev->features ^ features; |
| 1548 | u32 ctrl; |
| 1549 | |
| 1550 | if (changed & NETIF_F_RXCSUM) { |
| 1551 | ctrl = readl(priv->ioaddr + SXGBE_CORE_RX_CONFIG_REG); |
| 1552 | if (features & NETIF_F_RXCSUM) |
| 1553 | ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE; |
| 1554 | else |
| 1555 | ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE; |
| 1556 | writel(ctrl, priv->ioaddr + SXGBE_CORE_RX_CONFIG_REG); |
| 1557 | } |
| 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
| 1562 | /* sxgbe_change_mtu - entry point to change MTU size for the device. |
| 1563 | * @dev : device pointer. |
| 1564 | * @new_mtu : the new MTU size for the device. |
| 1565 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer |
| 1566 | * to drive packet transmission. Ethernet has an MTU of 1500 octets |
| 1567 | * (ETH_DATA_LEN). This value can be changed with ifconfig. |
| 1568 | * Return value: |
| 1569 | * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| 1570 | * file on failure. |
| 1571 | */ |
| 1572 | static int sxgbe_change_mtu(struct net_device *dev, int new_mtu) |
| 1573 | { |
| 1574 | /* RFC 791, page 25, "Every internet module must be able to forward |
| 1575 | * a datagram of 68 octets without further fragmentation." |
| 1576 | */ |
| 1577 | if (new_mtu < MIN_MTU || (new_mtu > MAX_MTU)) { |
| 1578 | netdev_err(dev, "invalid MTU, MTU should be in between %d and %d\n", |
| 1579 | MIN_MTU, MAX_MTU); |
| 1580 | return -EINVAL; |
| 1581 | } |
| 1582 | |
| 1583 | /* Return if the buffer sizes will not change */ |
| 1584 | if (dev->mtu == new_mtu) |
| 1585 | return 0; |
| 1586 | |
| 1587 | dev->mtu = new_mtu; |
| 1588 | |
| 1589 | if (!netif_running(dev)) |
| 1590 | return 0; |
| 1591 | |
| 1592 | /* Recevice ring buffer size is needed to be set based on MTU. If MTU is |
| 1593 | * changed then reinitilisation of the receive ring buffers need to be |
| 1594 | * done. Hence bring interface down and bring interface back up |
| 1595 | */ |
| 1596 | sxgbe_release(dev); |
| 1597 | return sxgbe_open(dev); |
| 1598 | } |
| 1599 | |
| 1600 | static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
| 1601 | unsigned int reg_n) |
| 1602 | { |
| 1603 | unsigned long data; |
| 1604 | |
| 1605 | data = (addr[5] << 8) | addr[4]; |
| 1606 | /* For MAC Addr registers se have to set the Address Enable (AE) |
| 1607 | * bit that has no effect on the High Reg 0 where the bit 31 (MO) |
| 1608 | * is RO. |
| 1609 | */ |
| 1610 | writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n)); |
| 1611 | data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; |
| 1612 | writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n)); |
| 1613 | } |
| 1614 | |
| 1615 | /** |
| 1616 | * sxgbe_set_rx_mode - entry point for setting different receive mode of |
| 1617 | * a device. unicast, multicast addressing |
| 1618 | * @dev : pointer to the device structure |
| 1619 | * Description: |
| 1620 | * This function is a driver entry point which gets called by the kernel |
| 1621 | * whenever different receive mode like unicast, multicast and promiscuous |
| 1622 | * must be enabled/disabled. |
| 1623 | * Return value: |
| 1624 | * void. |
| 1625 | */ |
| 1626 | static void sxgbe_set_rx_mode(struct net_device *dev) |
| 1627 | { |
| 1628 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1629 | void __iomem *ioaddr = (void __iomem *)priv->ioaddr; |
| 1630 | unsigned int value = 0; |
| 1631 | u32 mc_filter[2]; |
| 1632 | struct netdev_hw_addr *ha; |
| 1633 | int reg = 1; |
| 1634 | |
| 1635 | netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n", |
| 1636 | __func__, netdev_mc_count(dev), netdev_uc_count(dev)); |
| 1637 | |
| 1638 | if (dev->flags & IFF_PROMISC) { |
| 1639 | value = SXGBE_FRAME_FILTER_PR; |
| 1640 | |
| 1641 | } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) || |
| 1642 | (dev->flags & IFF_ALLMULTI)) { |
| 1643 | value = SXGBE_FRAME_FILTER_PM; /* pass all multi */ |
| 1644 | writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH); |
| 1645 | writel(0xffffffff, ioaddr + SXGBE_HASH_LOW); |
| 1646 | |
| 1647 | } else if (!netdev_mc_empty(dev)) { |
| 1648 | /* Hash filter for multicast */ |
| 1649 | value = SXGBE_FRAME_FILTER_HMC; |
| 1650 | |
| 1651 | memset(mc_filter, 0, sizeof(mc_filter)); |
| 1652 | netdev_for_each_mc_addr(ha, dev) { |
| 1653 | /* The upper 6 bits of the calculated CRC are used to |
| 1654 | * index the contens of the hash table |
| 1655 | */ |
| 1656 | int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26; |
| 1657 | |
| 1658 | /* The most significant bit determines the register to |
| 1659 | * use (H/L) while the other 5 bits determine the bit |
| 1660 | * within the register. |
| 1661 | */ |
| 1662 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
| 1663 | } |
| 1664 | writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW); |
| 1665 | writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH); |
| 1666 | } |
| 1667 | |
| 1668 | /* Handle multiple unicast addresses (perfect filtering) */ |
| 1669 | if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES) |
| 1670 | /* Switch to promiscuous mode if more than 16 addrs |
| 1671 | * are required |
| 1672 | */ |
| 1673 | value |= SXGBE_FRAME_FILTER_PR; |
| 1674 | else { |
| 1675 | netdev_for_each_uc_addr(ha, dev) { |
| 1676 | sxgbe_set_umac_addr(ioaddr, ha->addr, reg); |
| 1677 | reg++; |
| 1678 | } |
| 1679 | } |
| 1680 | #ifdef FRAME_FILTER_DEBUG |
| 1681 | /* Enable Receive all mode (to debug filtering_fail errors) */ |
| 1682 | value |= SXGBE_FRAME_FILTER_RA; |
| 1683 | #endif |
| 1684 | writel(value, ioaddr + SXGBE_FRAME_FILTER); |
| 1685 | |
| 1686 | netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n", |
| 1687 | readl(ioaddr + SXGBE_FRAME_FILTER), |
| 1688 | readl(ioaddr + SXGBE_HASH_HIGH), |
| 1689 | readl(ioaddr + SXGBE_HASH_LOW)); |
| 1690 | } |
| 1691 | |
| 1692 | /** |
| 1693 | * sxgbe_config - entry point for changing configuration mode passed on by |
| 1694 | * ifconfig |
| 1695 | * @dev : pointer to the device structure |
| 1696 | * @map : pointer to the device mapping structure |
| 1697 | * Description: |
| 1698 | * This function is a driver entry point which gets called by the kernel |
| 1699 | * whenever some device configuration is changed. |
| 1700 | * Return value: |
| 1701 | * This function returns 0 if success and appropriate error otherwise. |
| 1702 | */ |
| 1703 | static int sxgbe_config(struct net_device *dev, struct ifmap *map) |
| 1704 | { |
| 1705 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1706 | |
| 1707 | /* Can't act on a running interface */ |
| 1708 | if (dev->flags & IFF_UP) |
| 1709 | return -EBUSY; |
| 1710 | |
| 1711 | /* Don't allow changing the I/O address */ |
| 1712 | if (map->base_addr != (unsigned long)priv->ioaddr) { |
| 1713 | netdev_warn(dev, "can't change I/O address\n"); |
| 1714 | return -EOPNOTSUPP; |
| 1715 | } |
| 1716 | |
| 1717 | /* Don't allow changing the IRQ */ |
| 1718 | if (map->irq != priv->irq) { |
| 1719 | netdev_warn(dev, "not change IRQ number %d\n", priv->irq); |
| 1720 | return -EOPNOTSUPP; |
| 1721 | } |
| 1722 | |
| 1723 | return 0; |
| 1724 | } |
| 1725 | |
| 1726 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1727 | /** |
| 1728 | * sxgbe_poll_controller - entry point for polling receive by device |
| 1729 | * @dev : pointer to the device structure |
| 1730 | * Description: |
| 1731 | * This function is used by NETCONSOLE and other diagnostic tools |
| 1732 | * to allow network I/O with interrupts disabled. |
| 1733 | * Return value: |
| 1734 | * Void. |
| 1735 | */ |
| 1736 | static void sxgbe_poll_controller(struct net_device *dev) |
| 1737 | { |
| 1738 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1739 | |
| 1740 | disable_irq(priv->irq); |
| 1741 | sxgbe_rx_interrupt(priv->irq, dev); |
| 1742 | enable_irq(priv->irq); |
| 1743 | } |
| 1744 | #endif |
| 1745 | |
| 1746 | /* sxgbe_ioctl - Entry point for the Ioctl |
| 1747 | * @dev: Device pointer. |
| 1748 | * @rq: An IOCTL specefic structure, that can contain a pointer to |
| 1749 | * a proprietary structure used to pass information to the driver. |
| 1750 | * @cmd: IOCTL command |
| 1751 | * Description: |
| 1752 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
| 1753 | */ |
| 1754 | static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
| 1755 | { |
| 1756 | struct sxgbe_priv_data *priv = netdev_priv(dev); |
| 1757 | int ret = -EOPNOTSUPP; |
| 1758 | |
| 1759 | if (!netif_running(dev)) |
| 1760 | return -EINVAL; |
| 1761 | |
| 1762 | switch (cmd) { |
| 1763 | case SIOCGMIIPHY: |
| 1764 | case SIOCGMIIREG: |
| 1765 | case SIOCSMIIREG: |
| 1766 | if (!priv->phydev) |
| 1767 | return -EINVAL; |
| 1768 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); |
| 1769 | break; |
| 1770 | default: |
| 1771 | break; |
| 1772 | } |
| 1773 | |
| 1774 | return ret; |
| 1775 | } |
| 1776 | |
| 1777 | static const struct net_device_ops sxgbe_netdev_ops = { |
| 1778 | .ndo_open = sxgbe_open, |
| 1779 | .ndo_start_xmit = sxgbe_xmit, |
| 1780 | .ndo_stop = sxgbe_release, |
| 1781 | .ndo_get_stats64 = sxgbe_get_stats64, |
| 1782 | .ndo_change_mtu = sxgbe_change_mtu, |
| 1783 | .ndo_set_features = sxgbe_set_features, |
| 1784 | .ndo_set_rx_mode = sxgbe_set_rx_mode, |
| 1785 | .ndo_tx_timeout = sxgbe_tx_timeout, |
| 1786 | .ndo_do_ioctl = sxgbe_ioctl, |
| 1787 | .ndo_set_config = sxgbe_config, |
| 1788 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1789 | .ndo_poll_controller = sxgbe_poll_controller, |
| 1790 | #endif |
| 1791 | .ndo_set_mac_address = eth_mac_addr, |
| 1792 | }; |
| 1793 | |
| 1794 | /* Get the hardware ops */ |
| 1795 | void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr) |
| 1796 | { |
| 1797 | ops_ptr->mac = sxgbe_get_core_ops(); |
| 1798 | ops_ptr->desc = sxgbe_get_desc_ops(); |
| 1799 | ops_ptr->dma = sxgbe_get_dma_ops(); |
| 1800 | ops_ptr->mtl = sxgbe_get_mtl_ops(); |
| 1801 | |
| 1802 | /* set the MDIO communication Address/Data regisers */ |
| 1803 | ops_ptr->mii.addr = SXGBE_MDIO_SCMD_ADD_REG; |
| 1804 | ops_ptr->mii.data = SXGBE_MDIO_SCMD_DATA_REG; |
| 1805 | |
| 1806 | /* Assigning the default link settings |
| 1807 | * no SXGBE defined default values to be set in registers, |
| 1808 | * so assigning as 0 for port and duplex |
| 1809 | */ |
| 1810 | ops_ptr->link.port = 0; |
| 1811 | ops_ptr->link.duplex = 0; |
| 1812 | ops_ptr->link.speed = SXGBE_SPEED_10G; |
| 1813 | } |
| 1814 | |
| 1815 | /** |
| 1816 | * sxgbe_hw_init - Init the GMAC device |
| 1817 | * @priv: driver private structure |
| 1818 | * Description: this function checks the HW capability |
| 1819 | * (if supported) and sets the driver's features. |
| 1820 | */ |
| 1821 | static void sxgbe_hw_init(struct sxgbe_priv_data * const priv) |
| 1822 | { |
| 1823 | u32 ctrl_ids; |
| 1824 | |
| 1825 | priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL); |
| 1826 | |
| 1827 | /* get the hardware ops */ |
| 1828 | sxgbe_get_ops(priv->hw); |
| 1829 | |
| 1830 | /* get the controller id */ |
| 1831 | ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr); |
| 1832 | priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16; |
| 1833 | priv->hw->ctrl_id = (ctrl_ids & 0x000000ff); |
| 1834 | pr_info("user ID: 0x%x, Controller ID: 0x%x\n", |
| 1835 | priv->hw->ctrl_uid, priv->hw->ctrl_id); |
| 1836 | |
| 1837 | /* get the H/W features */ |
| 1838 | if (!sxgbe_get_hw_features(priv)) |
| 1839 | pr_info("Hardware features not found\n"); |
| 1840 | |
| 1841 | if (priv->hw_cap.tx_csum_offload) |
| 1842 | pr_info("TX Checksum offload supported\n"); |
| 1843 | |
| 1844 | if (priv->hw_cap.rx_csum_offload) |
| 1845 | pr_info("RX Checksum offload supported\n"); |
| 1846 | } |
| 1847 | |
| 1848 | /** |
| 1849 | * sxgbe_drv_probe |
| 1850 | * @device: device pointer |
| 1851 | * @plat_dat: platform data pointer |
| 1852 | * @addr: iobase memory address |
| 1853 | * Description: this is the main probe function used to |
| 1854 | * call the alloc_etherdev, allocate the priv structure. |
| 1855 | */ |
| 1856 | struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device, |
| 1857 | struct sxgbe_plat_data *plat_dat, |
| 1858 | void __iomem *addr) |
| 1859 | { |
| 1860 | struct sxgbe_priv_data *priv; |
| 1861 | struct net_device *ndev; |
| 1862 | int ret; |
| 1863 | |
| 1864 | ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data), |
| 1865 | SXGBE_TX_QUEUES, SXGBE_RX_QUEUES); |
| 1866 | if (!ndev) |
| 1867 | return NULL; |
| 1868 | |
| 1869 | SET_NETDEV_DEV(ndev, device); |
| 1870 | |
| 1871 | priv = netdev_priv(ndev); |
| 1872 | priv->device = device; |
| 1873 | priv->dev = ndev; |
| 1874 | |
| 1875 | sxgbe_set_ethtool_ops(ndev); |
| 1876 | priv->plat = plat_dat; |
| 1877 | priv->ioaddr = addr; |
| 1878 | |
| 1879 | /* Init MAC and get the capabilities */ |
| 1880 | sxgbe_hw_init(priv); |
| 1881 | |
| 1882 | /* allocate memory resources for Descriptor rings */ |
| 1883 | ret = txring_mem_alloc(priv); |
| 1884 | if (ret) |
| 1885 | goto error_free_netdev; |
| 1886 | |
| 1887 | ret = rxring_mem_alloc(priv); |
| 1888 | if (ret) |
| 1889 | goto error_free_netdev; |
| 1890 | |
| 1891 | ndev->netdev_ops = &sxgbe_netdev_ops; |
| 1892 | |
| 1893 | ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM; |
| 1894 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
| 1895 | ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO); |
| 1896 | |
| 1897 | /* assign filtering support */ |
| 1898 | ndev->priv_flags |= IFF_UNICAST_FLT; |
| 1899 | |
| 1900 | priv->msg_enable = netif_msg_init(debug, default_msg_level); |
| 1901 | |
| 1902 | /* Rx Watchdog is available, enable depend on platform data */ |
| 1903 | if (!priv->plat->riwt_off) { |
| 1904 | priv->use_riwt = 1; |
| 1905 | pr_info("Enable RX Mitigation via HW Watchdog Timer\n"); |
| 1906 | } |
| 1907 | |
| 1908 | netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64); |
| 1909 | |
| 1910 | spin_lock_init(&priv->stats_lock); |
| 1911 | |
| 1912 | priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME); |
| 1913 | if (IS_ERR(priv->sxgbe_clk)) { |
| 1914 | netdev_warn(ndev, "%s: warning: cannot get CSR clock\n", |
| 1915 | __func__); |
| 1916 | goto error_clk_get; |
| 1917 | } |
| 1918 | |
| 1919 | /* If a specific clk_csr value is passed from the platform |
| 1920 | * this means that the CSR Clock Range selection cannot be |
| 1921 | * changed at run-time and it is fixed. Viceversa the driver'll try to |
| 1922 | * set the MDC clock dynamically according to the csr actual |
| 1923 | * clock input. |
| 1924 | */ |
| 1925 | if (!priv->plat->clk_csr) |
| 1926 | sxgbe_clk_csr_set(priv); |
| 1927 | else |
| 1928 | priv->clk_csr = priv->plat->clk_csr; |
| 1929 | |
| 1930 | /* MDIO bus Registration */ |
| 1931 | ret = sxgbe_mdio_register(ndev); |
| 1932 | if (ret < 0) { |
| 1933 | netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n", |
| 1934 | __func__, priv->plat->bus_id); |
| 1935 | goto error_mdio_register; |
| 1936 | } |
| 1937 | |
| 1938 | ret = register_netdev(ndev); |
| 1939 | if (ret) { |
| 1940 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
| 1941 | goto error_netdev_register; |
| 1942 | } |
| 1943 | |
| 1944 | sxgbe_check_ether_addr(priv); |
| 1945 | |
| 1946 | return priv; |
| 1947 | |
| 1948 | error_mdio_register: |
| 1949 | clk_put(priv->sxgbe_clk); |
| 1950 | error_clk_get: |
| 1951 | error_netdev_register: |
| 1952 | netif_napi_del(&priv->napi); |
| 1953 | error_free_netdev: |
| 1954 | free_netdev(ndev); |
| 1955 | |
| 1956 | return NULL; |
| 1957 | } |
| 1958 | |
| 1959 | /** |
| 1960 | * sxgbe_drv_remove |
| 1961 | * @ndev: net device pointer |
| 1962 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
| 1963 | * changes the link status, releases the DMA descriptor rings. |
| 1964 | */ |
| 1965 | int sxgbe_drv_remove(struct net_device *ndev) |
| 1966 | { |
| 1967 | struct sxgbe_priv_data *priv = netdev_priv(ndev); |
| 1968 | |
| 1969 | netdev_info(ndev, "%s: removing driver\n", __func__); |
| 1970 | |
| 1971 | priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES); |
| 1972 | priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES); |
| 1973 | |
| 1974 | priv->hw->mac->enable_tx(priv->ioaddr, false); |
| 1975 | priv->hw->mac->enable_rx(priv->ioaddr, false); |
| 1976 | |
| 1977 | netif_napi_del(&priv->napi); |
| 1978 | |
| 1979 | sxgbe_mdio_unregister(ndev); |
| 1980 | |
| 1981 | unregister_netdev(ndev); |
| 1982 | |
| 1983 | free_netdev(ndev); |
| 1984 | |
| 1985 | return 0; |
| 1986 | } |
| 1987 | |
| 1988 | #ifdef CONFIG_PM |
| 1989 | int sxgbe_suspend(struct net_device *ndev) |
| 1990 | { |
| 1991 | return 0; |
| 1992 | } |
| 1993 | |
| 1994 | int sxgbe_resume(struct net_device *ndev) |
| 1995 | { |
| 1996 | return 0; |
| 1997 | } |
| 1998 | |
| 1999 | int sxgbe_freeze(struct net_device *ndev) |
| 2000 | { |
| 2001 | return -ENOSYS; |
| 2002 | } |
| 2003 | |
| 2004 | int sxgbe_restore(struct net_device *ndev) |
| 2005 | { |
| 2006 | return -ENOSYS; |
| 2007 | } |
| 2008 | #endif /* CONFIG_PM */ |
| 2009 | |
| 2010 | /* Driver is configured as Platform driver */ |
| 2011 | static int __init sxgbe_init(void) |
| 2012 | { |
| 2013 | int ret; |
| 2014 | |
| 2015 | ret = sxgbe_register_platform(); |
| 2016 | if (ret) |
| 2017 | goto err; |
| 2018 | return 0; |
| 2019 | err: |
| 2020 | pr_err("driver registration failed\n"); |
| 2021 | return ret; |
| 2022 | } |
| 2023 | |
| 2024 | static void __exit sxgbe_exit(void) |
| 2025 | { |
| 2026 | sxgbe_unregister_platform(); |
| 2027 | } |
| 2028 | |
| 2029 | module_init(sxgbe_init); |
| 2030 | module_exit(sxgbe_exit); |
| 2031 | |
| 2032 | #ifndef MODULE |
| 2033 | static int __init sxgbe_cmdline_opt(char *str) |
| 2034 | { |
| 2035 | return 0; |
| 2036 | } |
| 2037 | |
| 2038 | __setup("sxgbeeth=", sxgbe_cmdline_opt); |
| 2039 | #endif /* MODULE */ |
| 2040 | |
| 2041 | |
| 2042 | |
| 2043 | MODULE_DESCRIPTION("SAMSUNG 10G/2.5G/1G Ethernet PLATFORM driver"); |
| 2044 | |
| 2045 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
| 2046 | |
| 2047 | MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>"); |
| 2048 | MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>"); |
| 2049 | MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>"); |
| 2050 | MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>"); |
| 2051 | |
| 2052 | MODULE_LICENSE("GPL"); |