blob: 6d003114eeabbdce4cf75a6c020657fc99b162d6 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_FALCON_HWDEFS_H
12#define EFX_FALCON_HWDEFS_H
13
14/*
15 * Falcon hardware value definitions.
16 * Falcon is the internal codename for the SFC4000 controller that is
17 * present in SFE400X evaluation boards
18 */
19
20/**************************************************************************
21 *
22 * Falcon registers
23 *
24 **************************************************************************
25 */
26
27/* Address region register */
28#define ADR_REGION_REG_KER 0x00
29#define ADR_REGION0_LBN 0
30#define ADR_REGION0_WIDTH 18
31#define ADR_REGION1_LBN 32
32#define ADR_REGION1_WIDTH 18
33#define ADR_REGION2_LBN 64
34#define ADR_REGION2_WIDTH 18
35#define ADR_REGION3_LBN 96
36#define ADR_REGION3_WIDTH 18
37
38/* Interrupt enable register */
39#define INT_EN_REG_KER 0x0010
40#define KER_INT_KER_LBN 3
41#define KER_INT_KER_WIDTH 1
42#define DRV_INT_EN_KER_LBN 0
43#define DRV_INT_EN_KER_WIDTH 1
44
45/* Interrupt status address register */
46#define INT_ADR_REG_KER 0x0030
47#define NORM_INT_VEC_DIS_KER_LBN 64
48#define NORM_INT_VEC_DIS_KER_WIDTH 1
49#define INT_ADR_KER_LBN 0
50#define INT_ADR_KER_WIDTH EFX_DMA_TYPE_WIDTH(64) /* not 46 for this one */
51
52/* Interrupt status register (B0 only) */
53#define INT_ISR0_B0 0x90
54#define INT_ISR1_B0 0xA0
55
56/* Interrupt acknowledge register (A0/A1 only) */
57#define INT_ACK_REG_KER_A1 0x0050
58#define INT_ACK_DUMMY_DATA_LBN 0
59#define INT_ACK_DUMMY_DATA_WIDTH 32
60
61/* Interrupt acknowledge work-around register (A0/A1 only )*/
62#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
63
64/* SPI host command register */
65#define EE_SPI_HCMD_REG_KER 0x0100
66#define EE_SPI_HCMD_CMD_EN_LBN 31
67#define EE_SPI_HCMD_CMD_EN_WIDTH 1
68#define EE_WR_TIMER_ACTIVE_LBN 28
69#define EE_WR_TIMER_ACTIVE_WIDTH 1
70#define EE_SPI_HCMD_SF_SEL_LBN 24
71#define EE_SPI_HCMD_SF_SEL_WIDTH 1
72#define EE_SPI_EEPROM 0
73#define EE_SPI_FLASH 1
74#define EE_SPI_HCMD_DABCNT_LBN 16
75#define EE_SPI_HCMD_DABCNT_WIDTH 5
76#define EE_SPI_HCMD_READ_LBN 15
77#define EE_SPI_HCMD_READ_WIDTH 1
78#define EE_SPI_READ 1
79#define EE_SPI_WRITE 0
80#define EE_SPI_HCMD_DUBCNT_LBN 12
81#define EE_SPI_HCMD_DUBCNT_WIDTH 2
82#define EE_SPI_HCMD_ADBCNT_LBN 8
83#define EE_SPI_HCMD_ADBCNT_WIDTH 2
84#define EE_SPI_HCMD_ENC_LBN 0
85#define EE_SPI_HCMD_ENC_WIDTH 8
86
87/* SPI host address register */
88#define EE_SPI_HADR_REG_KER 0x0110
89#define EE_SPI_HADR_ADR_LBN 0
90#define EE_SPI_HADR_ADR_WIDTH 24
91
92/* SPI host data register */
93#define EE_SPI_HDATA_REG_KER 0x0120
94
95/* PCIE CORE ACCESS REG */
96#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68
97#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70
98#define PCIE_CORE_ADDR_ACK_RPL_TIMER 0x700
99#define PCIE_CORE_ADDR_ACK_FREQ 0x70C
100
101/* NIC status register */
102#define NIC_STAT_REG 0x0200
103#define ONCHIP_SRAM_LBN 16
104#define ONCHIP_SRAM_WIDTH 1
105#define SF_PRST_LBN 9
106#define SF_PRST_WIDTH 1
107#define EE_PRST_LBN 8
108#define EE_PRST_WIDTH 1
109/* See pic_mode_t for decoding of this field */
110/* These bit definitions are extrapolated from the list of numerical
111 * values for STRAP_PINS.
112 */
113#define STRAP_10G_LBN 2
114#define STRAP_10G_WIDTH 1
115#define STRAP_PCIE_LBN 0
116#define STRAP_PCIE_WIDTH 1
117
118/* GPIO control register */
119#define GPIO_CTL_REG_KER 0x0210
120#define GPIO_OUTPUTS_LBN (16)
121#define GPIO_OUTPUTS_WIDTH (4)
122#define GPIO_INPUTS_LBN (8)
123#define GPIO_DIRECTION_LBN (24)
124#define GPIO_DIRECTION_WIDTH (4)
125#define GPIO_DIRECTION_OUT (1)
126#define GPIO_SRAM_SLEEP (1 << 1)
127
128#define GPIO3_OEN_LBN (GPIO_DIRECTION_LBN + 3)
129#define GPIO3_OEN_WIDTH 1
130#define GPIO2_OEN_LBN (GPIO_DIRECTION_LBN + 2)
131#define GPIO2_OEN_WIDTH 1
132#define GPIO1_OEN_LBN (GPIO_DIRECTION_LBN + 1)
133#define GPIO1_OEN_WIDTH 1
134#define GPIO0_OEN_LBN (GPIO_DIRECTION_LBN + 0)
135#define GPIO0_OEN_WIDTH 1
136
137#define GPIO3_OUT_LBN (GPIO_OUTPUTS_LBN + 3)
138#define GPIO3_OUT_WIDTH 1
139#define GPIO2_OUT_LBN (GPIO_OUTPUTS_LBN + 2)
140#define GPIO2_OUT_WIDTH 1
141#define GPIO1_OUT_LBN (GPIO_OUTPUTS_LBN + 1)
142#define GPIO1_OUT_WIDTH 1
143#define GPIO0_OUT_LBN (GPIO_OUTPUTS_LBN + 0)
144#define GPIO0_OUT_WIDTH 1
145
146#define GPIO3_IN_LBN (GPIO_INPUTS_LBN + 3)
147#define GPIO3_IN_WIDTH 1
148#define GPIO2_IN_WIDTH 1
149#define GPIO1_IN_WIDTH 1
150#define GPIO0_IN_LBN (GPIO_INPUTS_LBN + 0)
151#define GPIO0_IN_WIDTH 1
152
153/* Global control register */
154#define GLB_CTL_REG_KER 0x0220
155#define EXT_PHY_RST_CTL_LBN 63
156#define EXT_PHY_RST_CTL_WIDTH 1
157#define PCIE_SD_RST_CTL_LBN 61
158#define PCIE_SD_RST_CTL_WIDTH 1
159
160#define PCIE_NSTCK_RST_CTL_LBN 58
161#define PCIE_NSTCK_RST_CTL_WIDTH 1
162#define PCIE_CORE_RST_CTL_LBN 57
163#define PCIE_CORE_RST_CTL_WIDTH 1
164#define EE_RST_CTL_LBN 49
165#define EE_RST_CTL_WIDTH 1
166#define RST_XGRX_LBN 24
167#define RST_XGRX_WIDTH 1
168#define RST_XGTX_LBN 23
169#define RST_XGTX_WIDTH 1
170#define RST_EM_LBN 22
171#define RST_EM_WIDTH 1
172#define EXT_PHY_RST_DUR_LBN 1
173#define EXT_PHY_RST_DUR_WIDTH 3
174#define SWRST_LBN 0
175#define SWRST_WIDTH 1
176#define INCLUDE_IN_RESET 0
177#define EXCLUDE_FROM_RESET 1
178
179/* Fatal interrupt register */
180#define FATAL_INTR_REG_KER 0x0230
181#define RBUF_OWN_INT_KER_EN_LBN 39
182#define RBUF_OWN_INT_KER_EN_WIDTH 1
183#define TBUF_OWN_INT_KER_EN_LBN 38
184#define TBUF_OWN_INT_KER_EN_WIDTH 1
185#define ILL_ADR_INT_KER_EN_LBN 33
186#define ILL_ADR_INT_KER_EN_WIDTH 1
187#define MEM_PERR_INT_KER_LBN 8
188#define MEM_PERR_INT_KER_WIDTH 1
189#define INT_KER_ERROR_LBN 0
190#define INT_KER_ERROR_WIDTH 12
191
192#define DP_CTRL_REG 0x250
193#define FLS_EVQ_ID_LBN 0
194#define FLS_EVQ_ID_WIDTH 11
195
196#define MEM_STAT_REG_KER 0x260
197
198/* Debug probe register */
199#define DEBUG_BLK_SEL_MISC 7
200#define DEBUG_BLK_SEL_SERDES 6
201#define DEBUG_BLK_SEL_EM 5
202#define DEBUG_BLK_SEL_SR 4
203#define DEBUG_BLK_SEL_EV 3
204#define DEBUG_BLK_SEL_RX 2
205#define DEBUG_BLK_SEL_TX 1
206#define DEBUG_BLK_SEL_BIU 0
207
208/* FPGA build version */
209#define ALTERA_BUILD_REG_KER 0x0300
210#define VER_ALL_LBN 0
211#define VER_ALL_WIDTH 32
212
213/* Spare EEPROM bits register (flash 0x390) */
214#define SPARE_REG_KER 0x310
215#define MEM_PERR_EN_TX_DATA_LBN 72
216#define MEM_PERR_EN_TX_DATA_WIDTH 2
217
218/* Timer table for kernel access */
219#define TIMER_CMD_REG_KER 0x420
220#define TIMER_MODE_LBN 12
221#define TIMER_MODE_WIDTH 2
222#define TIMER_MODE_DIS 0
223#define TIMER_MODE_INT_HLDOFF 2
224#define TIMER_VAL_LBN 0
225#define TIMER_VAL_WIDTH 12
226
227/* Driver generated event register */
228#define DRV_EV_REG_KER 0x440
229#define DRV_EV_QID_LBN 64
230#define DRV_EV_QID_WIDTH 12
231#define DRV_EV_DATA_LBN 0
232#define DRV_EV_DATA_WIDTH 64
233
234/* Buffer table configuration register */
235#define BUF_TBL_CFG_REG_KER 0x600
236#define BUF_TBL_MODE_LBN 3
237#define BUF_TBL_MODE_WIDTH 1
238#define BUF_TBL_MODE_HALF 0
239#define BUF_TBL_MODE_FULL 1
240
241/* SRAM receive descriptor cache configuration register */
242#define SRM_RX_DC_CFG_REG_KER 0x610
243#define SRM_RX_DC_BASE_ADR_LBN 0
244#define SRM_RX_DC_BASE_ADR_WIDTH 21
245
246/* SRAM transmit descriptor cache configuration register */
247#define SRM_TX_DC_CFG_REG_KER 0x620
248#define SRM_TX_DC_BASE_ADR_LBN 0
249#define SRM_TX_DC_BASE_ADR_WIDTH 21
250
251/* SRAM configuration register */
252#define SRM_CFG_REG_KER 0x630
253#define SRAM_OOB_BT_INIT_EN_LBN 3
254#define SRAM_OOB_BT_INIT_EN_WIDTH 1
255#define SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
256#define SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
257#define SRM_NB_BSZ_1BANKS_2M 0
258#define SRM_NB_BSZ_1BANKS_4M 1
259#define SRM_NB_BSZ_1BANKS_8M 2
260#define SRM_NB_BSZ_DEFAULT 3 /* char driver will set the default */
261#define SRM_NB_BSZ_2BANKS_4M 4
262#define SRM_NB_BSZ_2BANKS_8M 5
263#define SRM_NB_BSZ_2BANKS_16M 6
264#define SRM_NB_BSZ_RESERVED 7
265
266/* Special buffer table update register */
267#define BUF_TBL_UPD_REG_KER 0x0650
268#define BUF_UPD_CMD_LBN 63
269#define BUF_UPD_CMD_WIDTH 1
270#define BUF_CLR_CMD_LBN 62
271#define BUF_CLR_CMD_WIDTH 1
272#define BUF_CLR_END_ID_LBN 32
273#define BUF_CLR_END_ID_WIDTH 20
274#define BUF_CLR_START_ID_LBN 0
275#define BUF_CLR_START_ID_WIDTH 20
276
277/* Receive configuration register */
278#define RX_CFG_REG_KER 0x800
279
280/* B0 */
281#define RX_INGR_EN_B0_LBN 47
282#define RX_INGR_EN_B0_WIDTH 1
283#define RX_DESC_PUSH_EN_B0_LBN 43
284#define RX_DESC_PUSH_EN_B0_WIDTH 1
285#define RX_XON_TX_TH_B0_LBN 33
286#define RX_XON_TX_TH_B0_WIDTH 5
287#define RX_XOFF_TX_TH_B0_LBN 28
288#define RX_XOFF_TX_TH_B0_WIDTH 5
289#define RX_USR_BUF_SIZE_B0_LBN 19
290#define RX_USR_BUF_SIZE_B0_WIDTH 9
291#define RX_XON_MAC_TH_B0_LBN 10
292#define RX_XON_MAC_TH_B0_WIDTH 9
293#define RX_XOFF_MAC_TH_B0_LBN 1
294#define RX_XOFF_MAC_TH_B0_WIDTH 9
295#define RX_XOFF_MAC_EN_B0_LBN 0
296#define RX_XOFF_MAC_EN_B0_WIDTH 1
297
298/* A1 */
299#define RX_DESC_PUSH_EN_A1_LBN 35
300#define RX_DESC_PUSH_EN_A1_WIDTH 1
301#define RX_XON_TX_TH_A1_LBN 25
302#define RX_XON_TX_TH_A1_WIDTH 5
303#define RX_XOFF_TX_TH_A1_LBN 20
304#define RX_XOFF_TX_TH_A1_WIDTH 5
305#define RX_USR_BUF_SIZE_A1_LBN 11
306#define RX_USR_BUF_SIZE_A1_WIDTH 9
307#define RX_XON_MAC_TH_A1_LBN 6
308#define RX_XON_MAC_TH_A1_WIDTH 5
309#define RX_XOFF_MAC_TH_A1_LBN 1
310#define RX_XOFF_MAC_TH_A1_WIDTH 5
311#define RX_XOFF_MAC_EN_A1_LBN 0
312#define RX_XOFF_MAC_EN_A1_WIDTH 1
313
314/* Receive filter control register */
315#define RX_FILTER_CTL_REG 0x810
316#define UDP_FULL_SRCH_LIMIT_LBN 32
317#define UDP_FULL_SRCH_LIMIT_WIDTH 8
318#define NUM_KER_LBN 24
319#define NUM_KER_WIDTH 2
320#define UDP_WILD_SRCH_LIMIT_LBN 16
321#define UDP_WILD_SRCH_LIMIT_WIDTH 8
322#define TCP_WILD_SRCH_LIMIT_LBN 8
323#define TCP_WILD_SRCH_LIMIT_WIDTH 8
324#define TCP_FULL_SRCH_LIMIT_LBN 0
325#define TCP_FULL_SRCH_LIMIT_WIDTH 8
326
327/* RX queue flush register */
328#define RX_FLUSH_DESCQ_REG_KER 0x0820
329#define RX_FLUSH_DESCQ_CMD_LBN 24
330#define RX_FLUSH_DESCQ_CMD_WIDTH 1
331#define RX_FLUSH_DESCQ_LBN 0
332#define RX_FLUSH_DESCQ_WIDTH 12
333
334/* Receive descriptor update register */
335#define RX_DESC_UPD_REG_KER_DWORD (0x830 + 12)
336#define RX_DESC_WPTR_DWORD_LBN 0
337#define RX_DESC_WPTR_DWORD_WIDTH 12
338
339/* Receive descriptor cache configuration register */
340#define RX_DC_CFG_REG_KER 0x840
341#define RX_DC_SIZE_LBN 0
342#define RX_DC_SIZE_WIDTH 2
343
344#define RX_DC_PF_WM_REG_KER 0x850
345#define RX_DC_PF_LWM_LBN 0
346#define RX_DC_PF_LWM_WIDTH 6
347
348/* RX no descriptor drop counter */
349#define RX_NODESC_DROP_REG_KER 0x880
350#define RX_NODESC_DROP_CNT_LBN 0
351#define RX_NODESC_DROP_CNT_WIDTH 16
352
353/* RX black magic register */
354#define RX_SELF_RST_REG_KER 0x890
355#define RX_ISCSI_DIS_LBN 17
356#define RX_ISCSI_DIS_WIDTH 1
357#define RX_NODESC_WAIT_DIS_LBN 9
358#define RX_NODESC_WAIT_DIS_WIDTH 1
359#define RX_RECOVERY_EN_LBN 8
360#define RX_RECOVERY_EN_WIDTH 1
361
362/* TX queue flush register */
363#define TX_FLUSH_DESCQ_REG_KER 0x0a00
364#define TX_FLUSH_DESCQ_CMD_LBN 12
365#define TX_FLUSH_DESCQ_CMD_WIDTH 1
366#define TX_FLUSH_DESCQ_LBN 0
367#define TX_FLUSH_DESCQ_WIDTH 12
368
369/* Transmit descriptor update register */
370#define TX_DESC_UPD_REG_KER_DWORD (0xa10 + 12)
371#define TX_DESC_WPTR_DWORD_LBN 0
372#define TX_DESC_WPTR_DWORD_WIDTH 12
373
374/* Transmit descriptor cache configuration register */
375#define TX_DC_CFG_REG_KER 0xa20
376#define TX_DC_SIZE_LBN 0
377#define TX_DC_SIZE_WIDTH 2
378
379/* Transmit checksum configuration register (A0/A1 only) */
380#define TX_CHKSM_CFG_REG_KER_A1 0xa30
381
382/* Transmit configuration register */
383#define TX_CFG_REG_KER 0xa50
384#define TX_NO_EOP_DISC_EN_LBN 5
385#define TX_NO_EOP_DISC_EN_WIDTH 1
386
387/* Transmit configuration register 2 */
388#define TX_CFG2_REG_KER 0xa80
389#define TX_CSR_PUSH_EN_LBN 89
390#define TX_CSR_PUSH_EN_WIDTH 1
391#define TX_RX_SPACER_LBN 64
392#define TX_RX_SPACER_WIDTH 8
393#define TX_SW_EV_EN_LBN 59
394#define TX_SW_EV_EN_WIDTH 1
395#define TX_RX_SPACER_EN_LBN 57
396#define TX_RX_SPACER_EN_WIDTH 1
397#define TX_PREF_THRESHOLD_LBN 19
398#define TX_PREF_THRESHOLD_WIDTH 2
399#define TX_ONE_PKT_PER_Q_LBN 18
400#define TX_ONE_PKT_PER_Q_WIDTH 1
401#define TX_DIS_NON_IP_EV_LBN 17
402#define TX_DIS_NON_IP_EV_WIDTH 1
403#define TX_FLUSH_MIN_LEN_EN_B0_LBN 7
404#define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1
405
406/* PHY management transmit data register */
407#define MD_TXD_REG_KER 0xc00
408#define MD_TXD_LBN 0
409#define MD_TXD_WIDTH 16
410
411/* PHY management receive data register */
412#define MD_RXD_REG_KER 0xc10
413#define MD_RXD_LBN 0
414#define MD_RXD_WIDTH 16
415
416/* PHY management configuration & status register */
417#define MD_CS_REG_KER 0xc20
418#define MD_GC_LBN 4
419#define MD_GC_WIDTH 1
420#define MD_RIC_LBN 2
421#define MD_RIC_WIDTH 1
422#define MD_RDC_LBN 1
423#define MD_RDC_WIDTH 1
424#define MD_WRC_LBN 0
425#define MD_WRC_WIDTH 1
426
427/* PHY management PHY address register */
428#define MD_PHY_ADR_REG_KER 0xc30
429#define MD_PHY_ADR_LBN 0
430#define MD_PHY_ADR_WIDTH 16
431
432/* PHY management ID register */
433#define MD_ID_REG_KER 0xc40
434#define MD_PRT_ADR_LBN 11
435#define MD_PRT_ADR_WIDTH 5
436#define MD_DEV_ADR_LBN 6
437#define MD_DEV_ADR_WIDTH 5
438/* Used for writing both at once */
439#define MD_PRT_DEV_ADR_LBN 6
440#define MD_PRT_DEV_ADR_WIDTH 10
441
442/* PHY management status & mask register (DWORD read only) */
443#define MD_STAT_REG_KER 0xc50
444#define MD_BSERR_LBN 2
445#define MD_BSERR_WIDTH 1
446#define MD_LNFL_LBN 1
447#define MD_LNFL_WIDTH 1
448#define MD_BSY_LBN 0
449#define MD_BSY_WIDTH 1
450
451/* Port 0 and 1 MAC stats registers */
452#define MAC0_STAT_DMA_REG_KER 0xc60
453#define MAC_STAT_DMA_CMD_LBN 48
454#define MAC_STAT_DMA_CMD_WIDTH 1
455#define MAC_STAT_DMA_ADR_LBN 0
456#define MAC_STAT_DMA_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
457
458/* Port 0 and 1 MAC control registers */
459#define MAC0_CTRL_REG_KER 0xc80
460#define MAC_XOFF_VAL_LBN 16
461#define MAC_XOFF_VAL_WIDTH 16
462#define TXFIFO_DRAIN_EN_B0_LBN 7
463#define TXFIFO_DRAIN_EN_B0_WIDTH 1
464#define MAC_BCAD_ACPT_LBN 4
465#define MAC_BCAD_ACPT_WIDTH 1
466#define MAC_UC_PROM_LBN 3
467#define MAC_UC_PROM_WIDTH 1
468#define MAC_LINK_STATUS_LBN 2
469#define MAC_LINK_STATUS_WIDTH 1
470#define MAC_SPEED_LBN 0
471#define MAC_SPEED_WIDTH 2
472
473/* 10G XAUI XGXS default values */
474#define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
475#define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
476#define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */
477
478/* Multicast address hash table */
479#define MAC_MCAST_HASH_REG0_KER 0xca0
480#define MAC_MCAST_HASH_REG1_KER 0xcb0
481
482/* GMAC registers */
483#define FALCON_GMAC_REGBANK 0xe00
484#define FALCON_GMAC_REGBANK_SIZE 0x200
485#define FALCON_GMAC_REG_SIZE 0x10
486
487/* XMAC registers */
488#define FALCON_XMAC_REGBANK 0x1200
489#define FALCON_XMAC_REGBANK_SIZE 0x200
490#define FALCON_XMAC_REG_SIZE 0x10
491
492/* XGMAC address register low */
493#define XM_ADR_LO_REG_MAC 0x00
494#define XM_ADR_3_LBN 24
495#define XM_ADR_3_WIDTH 8
496#define XM_ADR_2_LBN 16
497#define XM_ADR_2_WIDTH 8
498#define XM_ADR_1_LBN 8
499#define XM_ADR_1_WIDTH 8
500#define XM_ADR_0_LBN 0
501#define XM_ADR_0_WIDTH 8
502
503/* XGMAC address register high */
504#define XM_ADR_HI_REG_MAC 0x01
505#define XM_ADR_5_LBN 8
506#define XM_ADR_5_WIDTH 8
507#define XM_ADR_4_LBN 0
508#define XM_ADR_4_WIDTH 8
509
510/* XGMAC global configuration */
511#define XM_GLB_CFG_REG_MAC 0x02
512#define XM_RX_STAT_EN_LBN 11
513#define XM_RX_STAT_EN_WIDTH 1
514#define XM_TX_STAT_EN_LBN 10
515#define XM_TX_STAT_EN_WIDTH 1
516#define XM_RX_JUMBO_MODE_LBN 6
517#define XM_RX_JUMBO_MODE_WIDTH 1
518#define XM_INTCLR_MODE_LBN 3
519#define XM_INTCLR_MODE_WIDTH 1
520#define XM_CORE_RST_LBN 0
521#define XM_CORE_RST_WIDTH 1
522
523/* XGMAC transmit configuration */
524#define XM_TX_CFG_REG_MAC 0x03
525#define XM_IPG_LBN 16
526#define XM_IPG_WIDTH 4
527#define XM_FCNTL_LBN 10
528#define XM_FCNTL_WIDTH 1
529#define XM_TXCRC_LBN 8
530#define XM_TXCRC_WIDTH 1
531#define XM_AUTO_PAD_LBN 5
532#define XM_AUTO_PAD_WIDTH 1
533#define XM_TX_PRMBL_LBN 2
534#define XM_TX_PRMBL_WIDTH 1
535#define XM_TXEN_LBN 1
536#define XM_TXEN_WIDTH 1
537
538/* XGMAC receive configuration */
539#define XM_RX_CFG_REG_MAC 0x04
540#define XM_PASS_CRC_ERR_LBN 25
541#define XM_PASS_CRC_ERR_WIDTH 1
542#define XM_ACPT_ALL_MCAST_LBN 11
543#define XM_ACPT_ALL_MCAST_WIDTH 1
544#define XM_ACPT_ALL_UCAST_LBN 9
545#define XM_ACPT_ALL_UCAST_WIDTH 1
546#define XM_AUTO_DEPAD_LBN 8
547#define XM_AUTO_DEPAD_WIDTH 1
548#define XM_RXEN_LBN 1
549#define XM_RXEN_WIDTH 1
550
551/* XGMAC management interrupt mask register */
552#define XM_MGT_INT_MSK_REG_MAC_B0 0x5
553#define XM_MSK_PRMBLE_ERR_LBN 2
554#define XM_MSK_PRMBLE_ERR_WIDTH 1
555#define XM_MSK_RMTFLT_LBN 1
556#define XM_MSK_RMTFLT_WIDTH 1
557#define XM_MSK_LCLFLT_LBN 0
558#define XM_MSK_LCLFLT_WIDTH 1
559
560/* XGMAC flow control register */
561#define XM_FC_REG_MAC 0x7
562#define XM_PAUSE_TIME_LBN 16
563#define XM_PAUSE_TIME_WIDTH 16
564#define XM_DIS_FCNTL_LBN 0
565#define XM_DIS_FCNTL_WIDTH 1
566
567/* XGMAC pause time count register */
568#define XM_PAUSE_TIME_REG_MAC 0x9
569
570/* XGMAC transmit parameter register */
571#define XM_TX_PARAM_REG_MAC 0x0d
572#define XM_TX_JUMBO_MODE_LBN 31
573#define XM_TX_JUMBO_MODE_WIDTH 1
574#define XM_MAX_TX_FRM_SIZE_LBN 16
575#define XM_MAX_TX_FRM_SIZE_WIDTH 14
576
577/* XGMAC receive parameter register */
578#define XM_RX_PARAM_REG_MAC 0x0e
579#define XM_MAX_RX_FRM_SIZE_LBN 0
580#define XM_MAX_RX_FRM_SIZE_WIDTH 14
581
582/* XGMAC management interrupt status register */
583#define XM_MGT_INT_REG_MAC_B0 0x0f
584#define XM_PRMBLE_ERR 2
585#define XM_PRMBLE_WIDTH 1
586#define XM_RMTFLT_LBN 1
587#define XM_RMTFLT_WIDTH 1
588#define XM_LCLFLT_LBN 0
589#define XM_LCLFLT_WIDTH 1
590
591/* XGXS/XAUI powerdown/reset register */
592#define XX_PWR_RST_REG_MAC 0x10
593
594#define XX_PWRDND_EN_LBN 15
595#define XX_PWRDND_EN_WIDTH 1
596#define XX_PWRDNC_EN_LBN 14
597#define XX_PWRDNC_EN_WIDTH 1
598#define XX_PWRDNB_EN_LBN 13
599#define XX_PWRDNB_EN_WIDTH 1
600#define XX_PWRDNA_EN_LBN 12
601#define XX_PWRDNA_EN_WIDTH 1
602#define XX_RSTPLLCD_EN_LBN 9
603#define XX_RSTPLLCD_EN_WIDTH 1
604#define XX_RSTPLLAB_EN_LBN 8
605#define XX_RSTPLLAB_EN_WIDTH 1
606#define XX_RESETD_EN_LBN 7
607#define XX_RESETD_EN_WIDTH 1
608#define XX_RESETC_EN_LBN 6
609#define XX_RESETC_EN_WIDTH 1
610#define XX_RESETB_EN_LBN 5
611#define XX_RESETB_EN_WIDTH 1
612#define XX_RESETA_EN_LBN 4
613#define XX_RESETA_EN_WIDTH 1
614#define XX_RSTXGXSRX_EN_LBN 2
615#define XX_RSTXGXSRX_EN_WIDTH 1
616#define XX_RSTXGXSTX_EN_LBN 1
617#define XX_RSTXGXSTX_EN_WIDTH 1
618#define XX_RST_XX_EN_LBN 0
619#define XX_RST_XX_EN_WIDTH 1
620
621/* XGXS/XAUI powerdown/reset control register */
622#define XX_SD_CTL_REG_MAC 0x11
623#define XX_HIDRVD_LBN 15
624#define XX_HIDRVD_WIDTH 1
625#define XX_LODRVD_LBN 14
626#define XX_LODRVD_WIDTH 1
627#define XX_HIDRVC_LBN 13
628#define XX_HIDRVC_WIDTH 1
629#define XX_LODRVC_LBN 12
630#define XX_LODRVC_WIDTH 1
631#define XX_HIDRVB_LBN 11
632#define XX_HIDRVB_WIDTH 1
633#define XX_LODRVB_LBN 10
634#define XX_LODRVB_WIDTH 1
635#define XX_HIDRVA_LBN 9
636#define XX_HIDRVA_WIDTH 1
637#define XX_LODRVA_LBN 8
638#define XX_LODRVA_WIDTH 1
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100639#define XX_LPBKD_LBN 3
640#define XX_LPBKD_WIDTH 1
641#define XX_LPBKC_LBN 2
642#define XX_LPBKC_WIDTH 1
643#define XX_LPBKB_LBN 1
644#define XX_LPBKB_WIDTH 1
645#define XX_LPBKA_LBN 0
646#define XX_LPBKA_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +0100647
648#define XX_TXDRV_CTL_REG_MAC 0x12
649#define XX_DEQD_LBN 28
650#define XX_DEQD_WIDTH 4
651#define XX_DEQC_LBN 24
652#define XX_DEQC_WIDTH 4
653#define XX_DEQB_LBN 20
654#define XX_DEQB_WIDTH 4
655#define XX_DEQA_LBN 16
656#define XX_DEQA_WIDTH 4
657#define XX_DTXD_LBN 12
658#define XX_DTXD_WIDTH 4
659#define XX_DTXC_LBN 8
660#define XX_DTXC_WIDTH 4
661#define XX_DTXB_LBN 4
662#define XX_DTXB_WIDTH 4
663#define XX_DTXA_LBN 0
664#define XX_DTXA_WIDTH 4
665
666/* XAUI XGXS core status register */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100667#define XX_CORE_STAT_REG_MAC 0x16
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100668#define XX_FORCE_SIG_LBN 24
669#define XX_FORCE_SIG_WIDTH 8
670#define XX_FORCE_SIG_DECODE_FORCED 0xff
671#define XX_XGXS_LB_EN_LBN 23
672#define XX_XGXS_LB_EN_WIDTH 1
673#define XX_XGMII_LB_EN_LBN 22
674#define XX_XGMII_LB_EN_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +0100675#define XX_ALIGN_DONE_LBN 20
676#define XX_ALIGN_DONE_WIDTH 1
677#define XX_SYNC_STAT_LBN 16
678#define XX_SYNC_STAT_WIDTH 4
679#define XX_SYNC_STAT_DECODE_SYNCED 0xf
680#define XX_COMMA_DET_LBN 12
681#define XX_COMMA_DET_WIDTH 4
682#define XX_COMMA_DET_DECODE_DETECTED 0xf
683#define XX_COMMA_DET_RESET 0xf
684#define XX_CHARERR_LBN 4
685#define XX_CHARERR_WIDTH 4
686#define XX_CHARERR_RESET 0xf
687#define XX_DISPERR_LBN 0
688#define XX_DISPERR_WIDTH 4
689#define XX_DISPERR_RESET 0xf
690
691/* Receive filter table */
692#define RX_FILTER_TBL0 0xF00000
693
694/* Receive descriptor pointer table */
695#define RX_DESC_PTR_TBL_KER_A1 0x11800
696#define RX_DESC_PTR_TBL_KER_B0 0xF40000
697#define RX_DESC_PTR_TBL_KER_P0 0x900
698#define RX_ISCSI_DDIG_EN_LBN 88
699#define RX_ISCSI_DDIG_EN_WIDTH 1
700#define RX_ISCSI_HDIG_EN_LBN 87
701#define RX_ISCSI_HDIG_EN_WIDTH 1
702#define RX_DESCQ_BUF_BASE_ID_LBN 36
703#define RX_DESCQ_BUF_BASE_ID_WIDTH 20
704#define RX_DESCQ_EVQ_ID_LBN 24
705#define RX_DESCQ_EVQ_ID_WIDTH 12
706#define RX_DESCQ_OWNER_ID_LBN 10
707#define RX_DESCQ_OWNER_ID_WIDTH 14
708#define RX_DESCQ_LABEL_LBN 5
709#define RX_DESCQ_LABEL_WIDTH 5
710#define RX_DESCQ_SIZE_LBN 3
711#define RX_DESCQ_SIZE_WIDTH 2
712#define RX_DESCQ_SIZE_4K 3
713#define RX_DESCQ_SIZE_2K 2
714#define RX_DESCQ_SIZE_1K 1
715#define RX_DESCQ_SIZE_512 0
716#define RX_DESCQ_TYPE_LBN 2
717#define RX_DESCQ_TYPE_WIDTH 1
718#define RX_DESCQ_JUMBO_LBN 1
719#define RX_DESCQ_JUMBO_WIDTH 1
720#define RX_DESCQ_EN_LBN 0
721#define RX_DESCQ_EN_WIDTH 1
722
723/* Transmit descriptor pointer table */
724#define TX_DESC_PTR_TBL_KER_A1 0x11900
725#define TX_DESC_PTR_TBL_KER_B0 0xF50000
726#define TX_DESC_PTR_TBL_KER_P0 0xa40
727#define TX_NON_IP_DROP_DIS_B0_LBN 91
728#define TX_NON_IP_DROP_DIS_B0_WIDTH 1
729#define TX_IP_CHKSM_DIS_B0_LBN 90
730#define TX_IP_CHKSM_DIS_B0_WIDTH 1
731#define TX_TCP_CHKSM_DIS_B0_LBN 89
732#define TX_TCP_CHKSM_DIS_B0_WIDTH 1
733#define TX_DESCQ_EN_LBN 88
734#define TX_DESCQ_EN_WIDTH 1
735#define TX_ISCSI_DDIG_EN_LBN 87
736#define TX_ISCSI_DDIG_EN_WIDTH 1
737#define TX_ISCSI_HDIG_EN_LBN 86
738#define TX_ISCSI_HDIG_EN_WIDTH 1
739#define TX_DESCQ_BUF_BASE_ID_LBN 36
740#define TX_DESCQ_BUF_BASE_ID_WIDTH 20
741#define TX_DESCQ_EVQ_ID_LBN 24
742#define TX_DESCQ_EVQ_ID_WIDTH 12
743#define TX_DESCQ_OWNER_ID_LBN 10
744#define TX_DESCQ_OWNER_ID_WIDTH 14
745#define TX_DESCQ_LABEL_LBN 5
746#define TX_DESCQ_LABEL_WIDTH 5
747#define TX_DESCQ_SIZE_LBN 3
748#define TX_DESCQ_SIZE_WIDTH 2
749#define TX_DESCQ_SIZE_4K 3
750#define TX_DESCQ_SIZE_2K 2
751#define TX_DESCQ_SIZE_1K 1
752#define TX_DESCQ_SIZE_512 0
753#define TX_DESCQ_TYPE_LBN 1
754#define TX_DESCQ_TYPE_WIDTH 2
755
756/* Event queue pointer */
757#define EVQ_PTR_TBL_KER_A1 0x11a00
758#define EVQ_PTR_TBL_KER_B0 0xf60000
759#define EVQ_PTR_TBL_KER_P0 0x500
760#define EVQ_EN_LBN 23
761#define EVQ_EN_WIDTH 1
762#define EVQ_SIZE_LBN 20
763#define EVQ_SIZE_WIDTH 3
764#define EVQ_SIZE_32K 6
765#define EVQ_SIZE_16K 5
766#define EVQ_SIZE_8K 4
767#define EVQ_SIZE_4K 3
768#define EVQ_SIZE_2K 2
769#define EVQ_SIZE_1K 1
770#define EVQ_SIZE_512 0
771#define EVQ_BUF_BASE_ID_LBN 0
772#define EVQ_BUF_BASE_ID_WIDTH 20
773
774/* Event queue read pointer */
775#define EVQ_RPTR_REG_KER_A1 0x11b00
776#define EVQ_RPTR_REG_KER_B0 0xfa0000
777#define EVQ_RPTR_REG_KER_DWORD (EVQ_RPTR_REG_KER + 0)
778#define EVQ_RPTR_DWORD_LBN 0
779#define EVQ_RPTR_DWORD_WIDTH 14
780
781/* RSS indirection table */
782#define RX_RSS_INDIR_TBL_B0 0xFB0000
783#define RX_RSS_INDIR_ENT_B0_LBN 0
784#define RX_RSS_INDIR_ENT_B0_WIDTH 6
785
786/* Special buffer descriptors (full-mode) */
787#define BUF_FULL_TBL_KER_A1 0x8000
788#define BUF_FULL_TBL_KER_B0 0x800000
789#define IP_DAT_BUF_SIZE_LBN 50
790#define IP_DAT_BUF_SIZE_WIDTH 1
791#define IP_DAT_BUF_SIZE_8K 1
792#define IP_DAT_BUF_SIZE_4K 0
793#define BUF_ADR_REGION_LBN 48
794#define BUF_ADR_REGION_WIDTH 2
795#define BUF_ADR_FBUF_LBN 14
796#define BUF_ADR_FBUF_WIDTH 34
797#define BUF_OWNER_ID_FBUF_LBN 0
798#define BUF_OWNER_ID_FBUF_WIDTH 14
799
800/* Transmit descriptor */
801#define TX_KER_PORT_LBN 63
802#define TX_KER_PORT_WIDTH 1
803#define TX_KER_CONT_LBN 62
804#define TX_KER_CONT_WIDTH 1
805#define TX_KER_BYTE_CNT_LBN 48
806#define TX_KER_BYTE_CNT_WIDTH 14
807#define TX_KER_BUF_REGION_LBN 46
808#define TX_KER_BUF_REGION_WIDTH 2
809#define TX_KER_BUF_REGION0_DECODE 0
810#define TX_KER_BUF_REGION1_DECODE 1
811#define TX_KER_BUF_REGION2_DECODE 2
812#define TX_KER_BUF_REGION3_DECODE 3
813#define TX_KER_BUF_ADR_LBN 0
814#define TX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
815
816/* Receive descriptor */
817#define RX_KER_BUF_SIZE_LBN 48
818#define RX_KER_BUF_SIZE_WIDTH 14
819#define RX_KER_BUF_REGION_LBN 46
820#define RX_KER_BUF_REGION_WIDTH 2
821#define RX_KER_BUF_REGION0_DECODE 0
822#define RX_KER_BUF_REGION1_DECODE 1
823#define RX_KER_BUF_REGION2_DECODE 2
824#define RX_KER_BUF_REGION3_DECODE 3
825#define RX_KER_BUF_ADR_LBN 0
826#define RX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
827
828/**************************************************************************
829 *
830 * Falcon events
831 *
832 **************************************************************************
833 */
834
835/* Event queue entries */
836#define EV_CODE_LBN 60
837#define EV_CODE_WIDTH 4
838#define RX_IP_EV_DECODE 0
839#define TX_IP_EV_DECODE 2
840#define DRIVER_EV_DECODE 5
841#define GLOBAL_EV_DECODE 6
842#define DRV_GEN_EV_DECODE 7
843#define WHOLE_EVENT_LBN 0
844#define WHOLE_EVENT_WIDTH 64
845
846/* Receive events */
847#define RX_EV_PKT_OK_LBN 56
848#define RX_EV_PKT_OK_WIDTH 1
849#define RX_EV_PAUSE_FRM_ERR_LBN 55
850#define RX_EV_PAUSE_FRM_ERR_WIDTH 1
851#define RX_EV_BUF_OWNER_ID_ERR_LBN 54
852#define RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
853#define RX_EV_IF_FRAG_ERR_LBN 53
854#define RX_EV_IF_FRAG_ERR_WIDTH 1
855#define RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
856#define RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
857#define RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
858#define RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
859#define RX_EV_ETH_CRC_ERR_LBN 50
860#define RX_EV_ETH_CRC_ERR_WIDTH 1
861#define RX_EV_FRM_TRUNC_LBN 49
862#define RX_EV_FRM_TRUNC_WIDTH 1
863#define RX_EV_DRIB_NIB_LBN 48
864#define RX_EV_DRIB_NIB_WIDTH 1
865#define RX_EV_TOBE_DISC_LBN 47
866#define RX_EV_TOBE_DISC_WIDTH 1
867#define RX_EV_PKT_TYPE_LBN 44
868#define RX_EV_PKT_TYPE_WIDTH 3
869#define RX_EV_PKT_TYPE_ETH_DECODE 0
870#define RX_EV_PKT_TYPE_LLC_DECODE 1
871#define RX_EV_PKT_TYPE_JUMBO_DECODE 2
872#define RX_EV_PKT_TYPE_VLAN_DECODE 3
873#define RX_EV_PKT_TYPE_VLAN_LLC_DECODE 4
874#define RX_EV_PKT_TYPE_VLAN_JUMBO_DECODE 5
875#define RX_EV_HDR_TYPE_LBN 42
876#define RX_EV_HDR_TYPE_WIDTH 2
877#define RX_EV_HDR_TYPE_TCP_IPV4_DECODE 0
878#define RX_EV_HDR_TYPE_UDP_IPV4_DECODE 1
879#define RX_EV_HDR_TYPE_OTHER_IP_DECODE 2
880#define RX_EV_HDR_TYPE_NON_IP_DECODE 3
881#define RX_EV_HDR_TYPE_HAS_CHECKSUMS(hdr_type) \
882 ((hdr_type) <= RX_EV_HDR_TYPE_UDP_IPV4_DECODE)
883#define RX_EV_MCAST_HASH_MATCH_LBN 40
884#define RX_EV_MCAST_HASH_MATCH_WIDTH 1
885#define RX_EV_MCAST_PKT_LBN 39
886#define RX_EV_MCAST_PKT_WIDTH 1
887#define RX_EV_Q_LABEL_LBN 32
888#define RX_EV_Q_LABEL_WIDTH 5
889#define RX_EV_JUMBO_CONT_LBN 31
890#define RX_EV_JUMBO_CONT_WIDTH 1
891#define RX_EV_BYTE_CNT_LBN 16
892#define RX_EV_BYTE_CNT_WIDTH 14
893#define RX_EV_SOP_LBN 15
894#define RX_EV_SOP_WIDTH 1
895#define RX_EV_DESC_PTR_LBN 0
896#define RX_EV_DESC_PTR_WIDTH 12
897
898/* Transmit events */
899#define TX_EV_PKT_ERR_LBN 38
900#define TX_EV_PKT_ERR_WIDTH 1
901#define TX_EV_Q_LABEL_LBN 32
902#define TX_EV_Q_LABEL_WIDTH 5
903#define TX_EV_WQ_FF_FULL_LBN 15
904#define TX_EV_WQ_FF_FULL_WIDTH 1
905#define TX_EV_COMP_LBN 12
906#define TX_EV_COMP_WIDTH 1
907#define TX_EV_DESC_PTR_LBN 0
908#define TX_EV_DESC_PTR_WIDTH 12
909
910/* Driver events */
911#define DRIVER_EV_SUB_CODE_LBN 56
912#define DRIVER_EV_SUB_CODE_WIDTH 4
913#define DRIVER_EV_SUB_DATA_LBN 0
914#define DRIVER_EV_SUB_DATA_WIDTH 14
915#define TX_DESCQ_FLS_DONE_EV_DECODE 0
916#define RX_DESCQ_FLS_DONE_EV_DECODE 1
917#define EVQ_INIT_DONE_EV_DECODE 2
918#define EVQ_NOT_EN_EV_DECODE 3
919#define RX_DESCQ_FLSFF_OVFL_EV_DECODE 4
920#define SRM_UPD_DONE_EV_DECODE 5
921#define WAKE_UP_EV_DECODE 6
922#define TX_PKT_NON_TCP_UDP_DECODE 9
923#define TIMER_EV_DECODE 10
924#define RX_RECOVERY_EV_DECODE 11
925#define RX_DSC_ERROR_EV_DECODE 14
926#define TX_DSC_ERROR_EV_DECODE 15
927#define DRIVER_EV_TX_DESCQ_ID_LBN 0
928#define DRIVER_EV_TX_DESCQ_ID_WIDTH 12
929#define DRIVER_EV_RX_FLUSH_FAIL_LBN 12
930#define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
931#define DRIVER_EV_RX_DESCQ_ID_LBN 0
932#define DRIVER_EV_RX_DESCQ_ID_WIDTH 12
933#define SRM_CLR_EV_DECODE 0
934#define SRM_UPD_EV_DECODE 1
935#define SRM_ILLCLR_EV_DECODE 2
936
937/* Global events */
938#define RX_RECOVERY_B0_LBN 12
939#define RX_RECOVERY_B0_WIDTH 1
940#define XG_MNT_INTR_B0_LBN 11
941#define XG_MNT_INTR_B0_WIDTH 1
942#define RX_RECOVERY_A1_LBN 11
943#define RX_RECOVERY_A1_WIDTH 1
944#define XG_PHY_INTR_LBN 9
945#define XG_PHY_INTR_WIDTH 1
946#define G_PHY1_INTR_LBN 8
947#define G_PHY1_INTR_WIDTH 1
948#define G_PHY0_INTR_LBN 7
949#define G_PHY0_INTR_WIDTH 1
950
951/* Driver-generated test events */
952#define EVQ_MAGIC_LBN 0
953#define EVQ_MAGIC_WIDTH 32
954
955/**************************************************************************
956 *
957 * Falcon MAC stats
958 *
959 **************************************************************************
960 *
961 */
962#define GRxGoodOct_offset 0x0
963#define GRxBadOct_offset 0x8
964#define GRxMissPkt_offset 0x10
965#define GRxFalseCRS_offset 0x14
966#define GRxPausePkt_offset 0x18
967#define GRxBadPkt_offset 0x1C
968#define GRxUcastPkt_offset 0x20
969#define GRxMcastPkt_offset 0x24
970#define GRxBcastPkt_offset 0x28
971#define GRxGoodLt64Pkt_offset 0x2C
972#define GRxBadLt64Pkt_offset 0x30
973#define GRx64Pkt_offset 0x34
974#define GRx65to127Pkt_offset 0x38
975#define GRx128to255Pkt_offset 0x3C
976#define GRx256to511Pkt_offset 0x40
977#define GRx512to1023Pkt_offset 0x44
978#define GRx1024to15xxPkt_offset 0x48
979#define GRx15xxtoJumboPkt_offset 0x4C
980#define GRxGtJumboPkt_offset 0x50
981#define GRxFcsErr64to15xxPkt_offset 0x54
982#define GRxFcsErr15xxtoJumboPkt_offset 0x58
983#define GRxFcsErrGtJumboPkt_offset 0x5C
984#define GTxGoodBadOct_offset 0x80
985#define GTxGoodOct_offset 0x88
986#define GTxSglColPkt_offset 0x90
987#define GTxMultColPkt_offset 0x94
988#define GTxExColPkt_offset 0x98
989#define GTxDefPkt_offset 0x9C
990#define GTxLateCol_offset 0xA0
991#define GTxExDefPkt_offset 0xA4
992#define GTxPausePkt_offset 0xA8
993#define GTxBadPkt_offset 0xAC
994#define GTxUcastPkt_offset 0xB0
995#define GTxMcastPkt_offset 0xB4
996#define GTxBcastPkt_offset 0xB8
997#define GTxLt64Pkt_offset 0xBC
998#define GTx64Pkt_offset 0xC0
999#define GTx65to127Pkt_offset 0xC4
1000#define GTx128to255Pkt_offset 0xC8
1001#define GTx256to511Pkt_offset 0xCC
1002#define GTx512to1023Pkt_offset 0xD0
1003#define GTx1024to15xxPkt_offset 0xD4
1004#define GTx15xxtoJumboPkt_offset 0xD8
1005#define GTxGtJumboPkt_offset 0xDC
1006#define GTxNonTcpUdpPkt_offset 0xE0
1007#define GTxMacSrcErrPkt_offset 0xE4
1008#define GTxIpSrcErrPkt_offset 0xE8
1009#define GDmaDone_offset 0xEC
1010
1011#define XgRxOctets_offset 0x0
1012#define XgRxOctets_WIDTH 48
1013#define XgRxOctetsOK_offset 0x8
1014#define XgRxOctetsOK_WIDTH 48
1015#define XgRxPkts_offset 0x10
1016#define XgRxPkts_WIDTH 32
1017#define XgRxPktsOK_offset 0x14
1018#define XgRxPktsOK_WIDTH 32
1019#define XgRxBroadcastPkts_offset 0x18
1020#define XgRxBroadcastPkts_WIDTH 32
1021#define XgRxMulticastPkts_offset 0x1C
1022#define XgRxMulticastPkts_WIDTH 32
1023#define XgRxUnicastPkts_offset 0x20
1024#define XgRxUnicastPkts_WIDTH 32
1025#define XgRxUndersizePkts_offset 0x24
1026#define XgRxUndersizePkts_WIDTH 32
1027#define XgRxOversizePkts_offset 0x28
1028#define XgRxOversizePkts_WIDTH 32
1029#define XgRxJabberPkts_offset 0x2C
1030#define XgRxJabberPkts_WIDTH 32
1031#define XgRxUndersizeFCSerrorPkts_offset 0x30
1032#define XgRxUndersizeFCSerrorPkts_WIDTH 32
1033#define XgRxDropEvents_offset 0x34
1034#define XgRxDropEvents_WIDTH 32
1035#define XgRxFCSerrorPkts_offset 0x38
1036#define XgRxFCSerrorPkts_WIDTH 32
1037#define XgRxAlignError_offset 0x3C
1038#define XgRxAlignError_WIDTH 32
1039#define XgRxSymbolError_offset 0x40
1040#define XgRxSymbolError_WIDTH 32
1041#define XgRxInternalMACError_offset 0x44
1042#define XgRxInternalMACError_WIDTH 32
1043#define XgRxControlPkts_offset 0x48
1044#define XgRxControlPkts_WIDTH 32
1045#define XgRxPausePkts_offset 0x4C
1046#define XgRxPausePkts_WIDTH 32
1047#define XgRxPkts64Octets_offset 0x50
1048#define XgRxPkts64Octets_WIDTH 32
1049#define XgRxPkts65to127Octets_offset 0x54
1050#define XgRxPkts65to127Octets_WIDTH 32
1051#define XgRxPkts128to255Octets_offset 0x58
1052#define XgRxPkts128to255Octets_WIDTH 32
1053#define XgRxPkts256to511Octets_offset 0x5C
1054#define XgRxPkts256to511Octets_WIDTH 32
1055#define XgRxPkts512to1023Octets_offset 0x60
1056#define XgRxPkts512to1023Octets_WIDTH 32
1057#define XgRxPkts1024to15xxOctets_offset 0x64
1058#define XgRxPkts1024to15xxOctets_WIDTH 32
1059#define XgRxPkts15xxtoMaxOctets_offset 0x68
1060#define XgRxPkts15xxtoMaxOctets_WIDTH 32
1061#define XgRxLengthError_offset 0x6C
1062#define XgRxLengthError_WIDTH 32
1063#define XgTxPkts_offset 0x80
1064#define XgTxPkts_WIDTH 32
1065#define XgTxOctets_offset 0x88
1066#define XgTxOctets_WIDTH 48
1067#define XgTxMulticastPkts_offset 0x90
1068#define XgTxMulticastPkts_WIDTH 32
1069#define XgTxBroadcastPkts_offset 0x94
1070#define XgTxBroadcastPkts_WIDTH 32
1071#define XgTxUnicastPkts_offset 0x98
1072#define XgTxUnicastPkts_WIDTH 32
1073#define XgTxControlPkts_offset 0x9C
1074#define XgTxControlPkts_WIDTH 32
1075#define XgTxPausePkts_offset 0xA0
1076#define XgTxPausePkts_WIDTH 32
1077#define XgTxPkts64Octets_offset 0xA4
1078#define XgTxPkts64Octets_WIDTH 32
1079#define XgTxPkts65to127Octets_offset 0xA8
1080#define XgTxPkts65to127Octets_WIDTH 32
1081#define XgTxPkts128to255Octets_offset 0xAC
1082#define XgTxPkts128to255Octets_WIDTH 32
1083#define XgTxPkts256to511Octets_offset 0xB0
1084#define XgTxPkts256to511Octets_WIDTH 32
1085#define XgTxPkts512to1023Octets_offset 0xB4
1086#define XgTxPkts512to1023Octets_WIDTH 32
1087#define XgTxPkts1024to15xxOctets_offset 0xB8
1088#define XgTxPkts1024to15xxOctets_WIDTH 32
1089#define XgTxPkts1519toMaxOctets_offset 0xBC
1090#define XgTxPkts1519toMaxOctets_WIDTH 32
1091#define XgTxUndersizePkts_offset 0xC0
1092#define XgTxUndersizePkts_WIDTH 32
1093#define XgTxOversizePkts_offset 0xC4
1094#define XgTxOversizePkts_WIDTH 32
1095#define XgTxNonTcpUdpPkt_offset 0xC8
1096#define XgTxNonTcpUdpPkt_WIDTH 16
1097#define XgTxMacSrcErrPkt_offset 0xCC
1098#define XgTxMacSrcErrPkt_WIDTH 16
1099#define XgTxIpSrcErrPkt_offset 0xD0
1100#define XgTxIpSrcErrPkt_WIDTH 16
1101#define XgDmaDone_offset 0xD4
1102
1103#define FALCON_STATS_NOT_DONE 0x00000000
1104#define FALCON_STATS_DONE 0xffffffff
1105
1106/* Interrupt status register bits */
1107#define FATAL_INT_LBN 64
1108#define FATAL_INT_WIDTH 1
1109#define INT_EVQS_LBN 40
1110#define INT_EVQS_WIDTH 4
1111
1112/**************************************************************************
1113 *
1114 * Falcon non-volatile configuration
1115 *
1116 **************************************************************************
1117 */
1118
1119/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
1120struct falcon_nvconfig_board_v2 {
1121 __le16 nports;
1122 u8 port0_phy_addr;
1123 u8 port0_phy_type;
1124 u8 port1_phy_addr;
1125 u8 port1_phy_type;
1126 __le16 asic_sub_revision;
1127 __le16 board_revision;
Ben Hutchings24c28ed2008-05-16 21:19:21 +01001128} __packed;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001129
1130#define NVCONFIG_BASE 0x300
1131#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
1132struct falcon_nvconfig {
1133 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
1134 u8 mac_address[2][8]; /* 0x310 */
1135 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
1136 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
1137 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
1138 efx_oword_t hw_init_reg; /* 0x350 */
1139 efx_oword_t nic_stat_reg; /* 0x360 */
1140 efx_oword_t glb_ctl_reg; /* 0x370 */
1141 efx_oword_t srm_cfg_reg; /* 0x380 */
1142 efx_oword_t spare_reg; /* 0x390 */
1143 __le16 board_magic_num; /* 0x3A0 */
1144 __le16 board_struct_ver;
1145 __le16 board_checksum;
1146 struct falcon_nvconfig_board_v2 board_v2;
Ben Hutchings24c28ed2008-05-16 21:19:21 +01001147} __packed;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001148
1149#endif /* EFX_FALCON_HWDEFS_H */