Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 1 | #ifndef _INC_COMET_H_ |
| 2 | #define _INC_COMET_H_ |
| 3 | |
| 4 | /*----------------------------------------------------------------------------- |
| 5 | * comet.h - |
| 6 | * |
| 7 | * Copyright (C) 2005 SBE, Inc. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * For further information, contact via email: support@sbei.com |
| 20 | * SBE, Inc. San Ramon, California U.S.A. |
| 21 | *----------------------------------------------------------------------------- |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 22 | */ |
| 23 | |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 24 | #include <linux/types.h> |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 25 | |
| 26 | #define VINT32 volatile u_int32_t |
| 27 | |
Sima Baymani | af25944 | 2013-11-05 21:22:56 +0100 | [diff] [blame] | 28 | struct s_comet_reg { |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 29 | VINT32 gbl_cfg; /* 00 Global Cfg */ |
| 30 | VINT32 clkmon; /* 01 Clk Monitor */ |
| 31 | VINT32 rx_opt; /* 02 RX Options */ |
| 32 | VINT32 rx_line_cfg; /* 03 RX Line Interface Cfg */ |
| 33 | VINT32 tx_line_cfg; /* 04 TX Line Interface Cfg */ |
| 34 | VINT32 tx_frpass; /* 05 TX Framing & Bypass Options */ |
| 35 | VINT32 tx_time; /* 06 TX Timing Options */ |
| 36 | VINT32 intr_1; /* 07 Intr Source #1 */ |
| 37 | VINT32 intr_2; /* 08 Intr Source #2 */ |
| 38 | VINT32 intr_3; /* 09 Intr Source #3 */ |
| 39 | VINT32 mdiag; /* 0A Master Diagnostics */ |
| 40 | VINT32 mtest; /* 0B Master Test */ |
| 41 | VINT32 adiag; /* 0C Analog Diagnostics */ |
| 42 | VINT32 rev_id; /* 0D Rev/Chip Id/Global PMON Update */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 43 | #define pmon rev_id |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 44 | VINT32 reset; /* 0E Reset */ |
| 45 | VINT32 prgd_phctl; /* 0F PRGD Positioning/Ctl & HDLC Ctl */ |
| 46 | VINT32 cdrc_cfg; /* 10 CDRC Cfg */ |
| 47 | VINT32 cdrc_ien; /* 11 CDRC Intr Enable */ |
| 48 | VINT32 cdrc_ists; /* 12 CDRC Intr Sts */ |
| 49 | VINT32 cdrc_alos; /* 13 CDRC Alternate Loss of Signal */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 50 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 51 | VINT32 rjat_ists; /* 14 RJAT Intr Sts */ |
| 52 | VINT32 rjat_n1clk; /* 15 RJAT Reference Clk Divisor (N1) Ctl */ |
| 53 | VINT32 rjat_n2clk; /* 16 RJAT Output Clk Divisor (N2) Ctl */ |
| 54 | VINT32 rjat_cfg; /* 17 RJAT Cfg */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 55 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 56 | VINT32 tjat_ists; /* 18 TJAT Intr Sts */ |
| 57 | VINT32 tjat_n1clk; /* 19 TJAT Reference Clk Divisor (N1) Ctl */ |
| 58 | VINT32 tjat_n2clk; /* 1A TJAT Output Clk Divisor (N2) Ctl */ |
| 59 | VINT32 tjat_cfg; /* 1B TJAT Cfg */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 60 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 61 | VINT32 rx_elst_cfg; /* 1C RX-ELST Cfg */ |
| 62 | VINT32 rx_elst_ists; /* 1D RX-ELST Intr Sts */ |
| 63 | VINT32 rx_elst_idle; /* 1E RX-ELST Idle Code */ |
| 64 | VINT32 _rx_elst_res1f; /* 1F RX-ELST Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 65 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 66 | VINT32 tx_elst_cfg; /* 20 TX-ELST Cfg */ |
| 67 | VINT32 tx_elst_ists; /* 21 TX-ELST Intr Sts */ |
| 68 | VINT32 _tx_elst_res22; /* 22 TX-ELST Reserved */ |
| 69 | VINT32 _tx_elst_res23; /* 23 TX-ELST Reserved */ |
| 70 | VINT32 __res24; /* 24 Reserved */ |
| 71 | VINT32 __res25; /* 25 Reserved */ |
| 72 | VINT32 __res26; /* 26 Reserved */ |
| 73 | VINT32 __res27; /* 27 Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 74 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 75 | VINT32 rxce1_ctl; /* 28 RXCE RX Data Link 1 Ctl */ |
| 76 | VINT32 rxce1_bits; /* 29 RXCE RX Data Link 1 Bit Select */ |
| 77 | VINT32 rxce2_ctl; /* 2A RXCE RX Data Link 2 Ctl */ |
| 78 | VINT32 rxce2_bits; /* 2B RXCE RX Data Link 2 Bit Select */ |
| 79 | VINT32 rxce3_ctl; /* 2C RXCE RX Data Link 3 Ctl */ |
| 80 | VINT32 rxce3_bits; /* 2D RXCE RX Data Link 3 Bit Select */ |
| 81 | VINT32 _rxce_res2E; /* 2E RXCE Reserved */ |
| 82 | VINT32 _rxce_res2F; /* 2F RXCE Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 83 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 84 | VINT32 brif_cfg; /* 30 BRIF RX Backplane Cfg */ |
| 85 | VINT32 brif_fpcfg; /* 31 BRIF RX Backplane Frame Pulse Cfg */ |
| 86 | VINT32 brif_pfcfg; /* 32 BRIF RX Backplane Parity/F-Bit Cfg */ |
| 87 | VINT32 brif_tsoff; /* 33 BRIF RX Backplane Time Slot Offset */ |
| 88 | VINT32 brif_boff; /* 34 BRIF RX Backplane Bit Offset */ |
| 89 | VINT32 _brif_res35; /* 35 BRIF RX Backplane Reserved */ |
| 90 | VINT32 _brif_res36; /* 36 BRIF RX Backplane Reserved */ |
| 91 | VINT32 _brif_res37; /* 37 BRIF RX Backplane Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 92 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 93 | VINT32 txci1_ctl; /* 38 TXCI TX Data Link 1 Ctl */ |
| 94 | VINT32 txci1_bits; /* 39 TXCI TX Data Link 2 Bit Select */ |
| 95 | VINT32 txci2_ctl; /* 3A TXCI TX Data Link 1 Ctl */ |
| 96 | VINT32 txci2_bits; /* 3B TXCI TX Data Link 2 Bit Select */ |
| 97 | VINT32 txci3_ctl; /* 3C TXCI TX Data Link 1 Ctl */ |
| 98 | VINT32 txci3_bits; /* 3D TXCI TX Data Link 2 Bit Select */ |
| 99 | VINT32 _txci_res3E; /* 3E TXCI Reserved */ |
| 100 | VINT32 _txci_res3F; /* 3F TXCI Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 101 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 102 | VINT32 btif_cfg; /* 40 BTIF TX Backplane Cfg */ |
| 103 | VINT32 btif_fpcfg; /* 41 BTIF TX Backplane Frame Pulse Cfg */ |
| 104 | VINT32 btif_pcfgsts; /* 42 BTIF TX Backplane Parity Cfg & Sts */ |
| 105 | VINT32 btif_tsoff; /* 43 BTIF TX Backplane Time Slot Offset */ |
| 106 | VINT32 btif_boff; /* 44 BTIF TX Backplane Bit Offset */ |
| 107 | VINT32 _btif_res45; /* 45 BTIF TX Backplane Reserved */ |
| 108 | VINT32 _btif_res46; /* 46 BTIF TX Backplane Reserved */ |
| 109 | VINT32 _btif_res47; /* 47 BTIF TX Backplane Reserved */ |
| 110 | VINT32 t1_frmr_cfg; /* 48 T1 FRMR Cfg */ |
| 111 | VINT32 t1_frmr_ien; /* 49 T1 FRMR Intr Enable */ |
| 112 | VINT32 t1_frmr_ists; /* 4A T1 FRMR Intr Sts */ |
| 113 | VINT32 __res_4B; /* 4B Reserved */ |
| 114 | VINT32 ibcd_cfg; /* 4C IBCD Cfg */ |
| 115 | VINT32 ibcd_ies; /* 4D IBCD Intr Enable/Sts */ |
| 116 | VINT32 ibcd_act; /* 4E IBCD Activate Code */ |
| 117 | VINT32 ibcd_deact; /* 4F IBCD Deactivate Code */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 118 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 119 | VINT32 sigx_cfg; /* 50 SIGX Cfg/Change of Signaling State */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 120 | VINT32 sigx_acc_cos; /* 51 SIGX |
| 121 | * uP Access Sts/Change of Signaling State */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 122 | VINT32 sigx_iac_cos; /* 52 SIGX Channel Indirect |
| 123 | * Addr/Ctl/Change of Signaling State */ |
| 124 | VINT32 sigx_idb_cos; /* 53 SIGX Channel Indirect Data |
| 125 | * Buffer/Change of Signaling State */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 126 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 127 | VINT32 t1_xbas_cfg; /* 54 T1 XBAS Cfg */ |
| 128 | VINT32 t1_xbas_altx; /* 55 T1 XBAS Alarm TX */ |
| 129 | VINT32 t1_xibc_ctl; /* 56 T1 XIBC Ctl */ |
| 130 | VINT32 t1_xibc_lbcode; /* 57 T1 XIBC Loopback Code */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 131 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 132 | VINT32 pmon_ies; /* 58 PMON Intr Enable/Sts */ |
| 133 | VINT32 pmon_fberr; /* 59 PMON Framing Bit Err Cnt */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 134 | VINT32 pmon_feb_lsb; /* 5A PMON |
| 135 | * OFF/COFA/Far End Block Err Cnt (LSB) */ |
| 136 | VINT32 pmon_feb_msb; /* 5B PMON |
| 137 | * OFF/COFA/Far End Block Err Cnt (MSB) */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 138 | VINT32 pmon_bed_lsb; /* 5C PMON Bit/Err/CRCE Cnt (LSB) */ |
| 139 | VINT32 pmon_bed_msb; /* 5D PMON Bit/Err/CRCE Cnt (MSB) */ |
| 140 | VINT32 pmon_lvc_lsb; /* 5E PMON LVC Cnt (LSB) */ |
| 141 | VINT32 pmon_lvc_msb; /* 5F PMON LVC Cnt (MSB) */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 142 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 143 | VINT32 t1_almi_cfg; /* 60 T1 ALMI Cfg */ |
| 144 | VINT32 t1_almi_ien; /* 61 T1 ALMI Intr Enable */ |
| 145 | VINT32 t1_almi_ists; /* 62 T1 ALMI Intr Sts */ |
| 146 | VINT32 t1_almi_detsts; /* 63 T1 ALMI Alarm Detection Sts */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 147 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 148 | VINT32 _t1_pdvd_res64; /* 64 T1 PDVD Reserved */ |
| 149 | VINT32 t1_pdvd_ies; /* 65 T1 PDVD Intr Enable/Sts */ |
| 150 | VINT32 _t1_xboc_res66; /* 66 T1 XBOC Reserved */ |
| 151 | VINT32 t1_xboc_code; /* 67 T1 XBOC Code */ |
| 152 | VINT32 _t1_xpde_res68; /* 68 T1 XPDE Reserved */ |
| 153 | VINT32 t1_xpde_ies; /* 69 T1 XPDE Intr Enable/Sts */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 154 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 155 | VINT32 t1_rboc_ena; /* 6A T1 RBOC Enable */ |
| 156 | VINT32 t1_rboc_sts; /* 6B T1 RBOC Code Sts */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 157 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 158 | VINT32 t1_tpsc_cfg; /* 6C TPSC Cfg */ |
| 159 | VINT32 t1_tpsc_sts; /* 6D TPSC uP Access Sts */ |
| 160 | VINT32 t1_tpsc_ciaddr; /* 6E TPSC Channel Indirect |
| 161 | * Addr/Ctl */ |
| 162 | VINT32 t1_tpsc_cidata; /* 6F TPSC Channel Indirect Data |
| 163 | * Buffer */ |
| 164 | VINT32 t1_rpsc_cfg; /* 70 RPSC Cfg */ |
| 165 | VINT32 t1_rpsc_sts; /* 71 RPSC uP Access Sts */ |
| 166 | VINT32 t1_rpsc_ciaddr; /* 72 RPSC Channel Indirect |
| 167 | * Addr/Ctl */ |
| 168 | VINT32 t1_rpsc_cidata; /* 73 RPSC Channel Indirect Data |
| 169 | * Buffer */ |
| 170 | VINT32 __res74; /* 74 Reserved */ |
| 171 | VINT32 __res75; /* 75 Reserved */ |
| 172 | VINT32 __res76; /* 76 Reserved */ |
| 173 | VINT32 __res77; /* 77 Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 174 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 175 | VINT32 t1_aprm_cfg; /* 78 T1 APRM Cfg/Ctl */ |
| 176 | VINT32 t1_aprm_load; /* 79 T1 APRM Manual Load */ |
| 177 | VINT32 t1_aprm_ists; /* 7A T1 APRM Intr Sts */ |
| 178 | VINT32 t1_aprm_1sec_2; /* 7B T1 APRM One Second Content Octet 2 */ |
| 179 | VINT32 t1_aprm_1sec_3; /* 7C T1 APRM One Second Content Octet 3 */ |
| 180 | VINT32 t1_aprm_1sec_4; /* 7D T1 APRM One Second Content Octet 4 */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 181 | VINT32 t1_aprm_1sec_5; /* 7E T1 APRM |
| 182 | * One Second Content MSB (Octect 5) */ |
| 183 | VINT32 t1_aprm_1sec_6; /* 7F T1 APRM |
| 184 | * One Second Content MSB (Octect 6) */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 185 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 186 | VINT32 e1_tran_cfg; /* 80 E1 TRAN Cfg */ |
| 187 | VINT32 e1_tran_txalarm; /* 81 E1 TRAN TX Alarm/Diagnostic Ctl */ |
| 188 | VINT32 e1_tran_intctl; /* 82 E1 TRAN International Ctl */ |
| 189 | VINT32 e1_tran_extrab; /* 83 E1 TRAN Extra Bits Ctl */ |
| 190 | VINT32 e1_tran_ien; /* 84 E1 TRAN Intr Enable */ |
| 191 | VINT32 e1_tran_ists; /* 85 E1 TRAN Intr Sts */ |
| 192 | VINT32 e1_tran_nats; /* 86 E1 TRAN National Bit Codeword |
| 193 | * Select */ |
| 194 | VINT32 e1_tran_nat; /* 87 E1 TRAN National Bit Codeword */ |
| 195 | VINT32 __res88; /* 88 Reserved */ |
| 196 | VINT32 __res89; /* 89 Reserved */ |
| 197 | VINT32 __res8A; /* 8A Reserved */ |
| 198 | VINT32 __res8B; /* 8B Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 199 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 200 | VINT32 _t1_frmr_res8C; /* 8C T1 FRMR Reserved */ |
| 201 | VINT32 _t1_frmr_res8D; /* 8D T1 FRMR Reserved */ |
| 202 | VINT32 __res8E; /* 8E Reserved */ |
| 203 | VINT32 __res8F; /* 8F Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 204 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 205 | VINT32 e1_frmr_aopts; /* 90 E1 FRMR Frame Alignment Options */ |
| 206 | VINT32 e1_frmr_mopts; /* 91 E1 FRMR Maintenance Mode Options */ |
| 207 | VINT32 e1_frmr_ien; /* 92 E1 FRMR Framing Sts Intr Enable */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 208 | VINT32 e1_frmr_mien; /* 93 E1 FRMR |
| 209 | * Maintenance/Alarm Sts Intr Enable */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 210 | VINT32 e1_frmr_ists; /* 94 E1 FRMR Framing Sts Intr Indication */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 211 | VINT32 e1_frmr_mists; /* 95 E1 FRMR |
| 212 | * Maintenance/Alarm Sts Indication Enable */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 213 | VINT32 e1_frmr_sts; /* 96 E1 FRMR Framing Sts */ |
| 214 | VINT32 e1_frmr_masts; /* 97 E1 FRMR Maintenance/Alarm Sts */ |
| 215 | VINT32 e1_frmr_nat_bits; /* 98 E1 FRMR International/National Bits */ |
| 216 | VINT32 e1_frmr_crc_lsb; /* 99 E1 FRMR CRC Err Cnt - LSB */ |
| 217 | VINT32 e1_frmr_crc_msb; /* 9A E1 FRMR CRC Err Cnt - MSB */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 218 | VINT32 e1_frmr_nat_ien; /* 9B E1 FRMR |
| 219 | * National Bit Codeword Intr Enables */ |
| 220 | VINT32 e1_frmr_nat_ists; /* 9C E1 FRMR |
| 221 | * National Bit Codeword Intr/Sts */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 222 | VINT32 e1_frmr_nat; /* 9D E1 FRMR National Bit Codewords */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 223 | VINT32 e1_frmr_fp_ien; /* 9E E1 FRMR |
| 224 | * Frame Pulse/Alarm Intr Enables */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 225 | VINT32 e1_frmr_fp_ists; /* 9F E1 FRMR Frame Pulse/Alarm Intr/Sts */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 226 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 227 | VINT32 __resA0; /* A0 Reserved */ |
| 228 | VINT32 __resA1; /* A1 Reserved */ |
| 229 | VINT32 __resA2; /* A2 Reserved */ |
| 230 | VINT32 __resA3; /* A3 Reserved */ |
| 231 | VINT32 __resA4; /* A4 Reserved */ |
| 232 | VINT32 __resA5; /* A5 Reserved */ |
| 233 | VINT32 __resA6; /* A6 Reserved */ |
| 234 | VINT32 __resA7; /* A7 Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 235 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 236 | VINT32 tdpr1_cfg; /* A8 TDPR #1 Cfg */ |
| 237 | VINT32 tdpr1_utl; /* A9 TDPR #1 Upper TX Threshold */ |
| 238 | VINT32 tdpr1_ltl; /* AA TDPR #1 Lower TX Threshold */ |
| 239 | VINT32 tdpr1_ien; /* AB TDPR #1 Intr Enable */ |
| 240 | VINT32 tdpr1_ists; /* AC TDPR #1 Intr Sts/UDR Clear */ |
| 241 | VINT32 tdpr1_data; /* AD TDPR #1 TX Data */ |
| 242 | VINT32 __resAE; /* AE Reserved */ |
| 243 | VINT32 __resAF; /* AF Reserved */ |
| 244 | VINT32 tdpr2_cfg; /* B0 TDPR #2 Cfg */ |
| 245 | VINT32 tdpr2_utl; /* B1 TDPR #2 Upper TX Threshold */ |
| 246 | VINT32 tdpr2_ltl; /* B2 TDPR #2 Lower TX Threshold */ |
| 247 | VINT32 tdpr2_ien; /* B3 TDPR #2 Intr Enable */ |
| 248 | VINT32 tdpr2_ists; /* B4 TDPR #2 Intr Sts/UDR Clear */ |
| 249 | VINT32 tdpr2_data; /* B5 TDPR #2 TX Data */ |
| 250 | VINT32 __resB6; /* B6 Reserved */ |
| 251 | VINT32 __resB7; /* B7 Reserved1 */ |
| 252 | VINT32 tdpr3_cfg; /* B8 TDPR #3 Cfg */ |
| 253 | VINT32 tdpr3_utl; /* B9 TDPR #3 Upper TX Threshold */ |
| 254 | VINT32 tdpr3_ltl; /* BA TDPR #3 Lower TX Threshold */ |
| 255 | VINT32 tdpr3_ien; /* BB TDPR #3 Intr Enable */ |
| 256 | VINT32 tdpr3_ists; /* BC TDPR #3 Intr Sts/UDR Clear */ |
| 257 | VINT32 tdpr3_data; /* BD TDPR #3 TX Data */ |
| 258 | VINT32 __resBE; /* BE Reserved */ |
| 259 | VINT32 __resBF; /* BF Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 260 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 261 | VINT32 rdlc1_cfg; /* C0 RDLC #1 Cfg */ |
| 262 | VINT32 rdlc1_intctl; /* C1 RDLC #1 Intr Ctl */ |
| 263 | VINT32 rdlc1_sts; /* C2 RDLC #1 Sts */ |
| 264 | VINT32 rdlc1_data; /* C3 RDLC #1 Data */ |
| 265 | VINT32 rdlc1_paddr; /* C4 RDLC #1 Primary Addr Match */ |
| 266 | VINT32 rdlc1_saddr; /* C5 RDLC #1 Secondary Addr Match */ |
| 267 | VINT32 __resC6; /* C6 Reserved */ |
| 268 | VINT32 __resC7; /* C7 Reserved */ |
| 269 | VINT32 rdlc2_cfg; /* C8 RDLC #2 Cfg */ |
| 270 | VINT32 rdlc2_intctl; /* C9 RDLC #2 Intr Ctl */ |
| 271 | VINT32 rdlc2_sts; /* CA RDLC #2 Sts */ |
| 272 | VINT32 rdlc2_data; /* CB RDLC #2 Data */ |
| 273 | VINT32 rdlc2_paddr; /* CC RDLC #2 Primary Addr Match */ |
| 274 | VINT32 rdlc2_saddr; /* CD RDLC #2 Secondary Addr Match */ |
| 275 | VINT32 __resCE; /* CE Reserved */ |
| 276 | VINT32 __resCF; /* CF Reserved */ |
| 277 | VINT32 rdlc3_cfg; /* D0 RDLC #3 Cfg */ |
| 278 | VINT32 rdlc3_intctl; /* D1 RDLC #3 Intr Ctl */ |
| 279 | VINT32 rdlc3_sts; /* D2 RDLC #3 Sts */ |
| 280 | VINT32 rdlc3_data; /* D3 RDLC #3 Data */ |
| 281 | VINT32 rdlc3_paddr; /* D4 RDLC #3 Primary Addr Match */ |
| 282 | VINT32 rdlc3_saddr; /* D5 RDLC #3 Secondary Addr Match */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 283 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 284 | VINT32 csu_cfg; /* D6 CSU Cfg */ |
| 285 | VINT32 _csu_resD7; /* D7 CSU Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 286 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 287 | VINT32 rlps_idata3; /* D8 RLPS Indirect Data, 24-31 */ |
| 288 | VINT32 rlps_idata2; /* D9 RLPS Indirect Data, 16-23 */ |
| 289 | VINT32 rlps_idata1; /* DA RLPS Indirect Data, 8-15 */ |
| 290 | VINT32 rlps_idata0; /* DB RLPS Indirect Data, 0-7 */ |
| 291 | VINT32 rlps_eqvr; /* DC RLPS Equalizer Voltage Reference |
| 292 | * (E1 missing) */ |
| 293 | VINT32 _rlps_resDD; /* DD RLPS Reserved */ |
| 294 | VINT32 _rlps_resDE; /* DE RLPS Reserved */ |
| 295 | VINT32 _rlps_resDF; /* DF RLPS Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 296 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 297 | VINT32 prgd_ctl; /* E0 PRGD Ctl */ |
| 298 | VINT32 prgd_ies; /* E1 PRGD Intr Enable/Sts */ |
| 299 | VINT32 prgd_shift_len; /* E2 PRGD Shift Length */ |
| 300 | VINT32 prgd_tap; /* E3 PRGD Tap */ |
| 301 | VINT32 prgd_errin; /* E4 PRGD Err Insertion */ |
| 302 | VINT32 _prgd_resE5; /* E5 PRGD Reserved */ |
| 303 | VINT32 _prgd_resE6; /* E6 PRGD Reserved */ |
| 304 | VINT32 _prgd_resE7; /* E7 PRGD Reserved */ |
| 305 | VINT32 prgd_patin1; /* E8 PRGD Pattern Insertion #1 */ |
| 306 | VINT32 prgd_patin2; /* E9 PRGD Pattern Insertion #2 */ |
| 307 | VINT32 prgd_patin3; /* EA PRGD Pattern Insertion #3 */ |
| 308 | VINT32 prgd_patin4; /* EB PRGD Pattern Insertion #4 */ |
| 309 | VINT32 prgd_patdet1; /* EC PRGD Pattern Detector #1 */ |
| 310 | VINT32 prgd_patdet2; /* ED PRGD Pattern Detector #2 */ |
| 311 | VINT32 prgd_patdet3; /* EE PRGD Pattern Detector #3 */ |
| 312 | VINT32 prgd_patdet4; /* EF PRGD Pattern Detector #4 */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 313 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 314 | VINT32 xlpg_cfg; /* F0 XLPG Line Driver Cfg */ |
| 315 | VINT32 xlpg_ctlsts; /* F1 XLPG Ctl/Sts */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 316 | VINT32 xlpg_pwave_addr; /* F2 XLPG |
| 317 | * Pulse Waveform Storage Write Addr */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 318 | VINT32 xlpg_pwave_data; /* F3 XLPG Pulse Waveform Storage Data */ |
| 319 | VINT32 xlpg_atest_pctl; /* F4 XLPG Analog Test Positive Ctl */ |
| 320 | VINT32 xlpg_atest_nctl; /* F5 XLPG Analog Test Negative Ctl */ |
| 321 | VINT32 xlpg_fdata_sel; /* F6 XLPG Fuse Data Select */ |
| 322 | VINT32 _xlpg_resF7; /* F7 XLPG Reserved */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 323 | |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 324 | VINT32 rlps_cfgsts; /* F8 RLPS Cfg & Sts */ |
Sima Baymani | 353808b | 2013-11-05 21:22:12 +0100 | [diff] [blame] | 325 | VINT32 rlps_alos_thresh; /* F9 RLPS |
| 326 | * ALOS Detection/Clearance Threshold */ |
Sima Baymani | 89c05d2 | 2013-11-05 21:21:38 +0100 | [diff] [blame] | 327 | VINT32 rlps_alos_dper; /* FA RLPS ALOS Detection Period */ |
| 328 | VINT32 rlps_alos_cper; /* FB RLPS ALOS Clearance Period */ |
| 329 | VINT32 rlps_eq_iaddr; /* FC RLPS Equalization Indirect Addr */ |
| 330 | VINT32 rlps_eq_rwsel; /* FD RLPS Equalization Read/WriteB Select */ |
| 331 | VINT32 rlps_eq_ctlsts; /* FE RLPS Equalizer Loop Sts & Ctl */ |
| 332 | VINT32 rlps_eq_cfg; /* FF RLPS Equalizer Cfg */ |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 333 | }; |
| 334 | |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 335 | /* 00AH: MDIAG Register bit definitions */ |
| 336 | #define COMET_MDIAG_ID5 0x40 |
| 337 | #define COMET_MDIAG_LBMASK 0x3F |
| 338 | #define COMET_MDIAG_PAYLB 0x20 |
| 339 | #define COMET_MDIAG_LINELB 0x10 |
| 340 | #define COMET_MDIAG_RAIS 0x08 |
| 341 | #define COMET_MDIAG_DDLB 0x04 |
| 342 | #define COMET_MDIAG_TXMFP 0x02 |
| 343 | #define COMET_MDIAG_TXLOS 0x01 |
| 344 | #define COMET_MDIAG_LBOFF 0x00 |
| 345 | |
| 346 | #undef VINT32 |
| 347 | |
| 348 | #ifdef __KERNEL__ |
| 349 | extern void |
Sima Baymani | 987e8be | 2013-11-05 21:49:16 +0100 | [diff] [blame] | 350 | init_comet(void *, struct s_comet_reg *, u_int32_t, int, u_int8_t); |
Bob Beers | 50ee11f | 2010-03-04 08:40:46 -0500 | [diff] [blame] | 351 | #endif |
| 352 | |
| 353 | #endif /* _INC_COMET_H_ */ |