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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
Thomas Gleixner67c5fc52008-01-30 13:30:15 +01003
Ingo Molnare2780a62009-02-17 13:52:29 +01004#include <linux/cpumask.h>
Thomas Gleixner67c5fc52008-01-30 13:30:15 +01005#include <linux/delay.h>
Ingo Molnare2780a62009-02-17 13:52:29 +01006#include <linux/pm.h>
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01007
8#include <asm/alternative.h>
Suresh Siddha13c88fb52008-07-10 11:16:52 -07009#include <asm/cpufeature.h>
Ingo Molnare2780a62009-02-17 13:52:29 +010010#include <asm/processor.h>
11#include <asm/apicdef.h>
12#include <asm/atomic.h>
13#include <asm/fixmap.h>
14#include <asm/mpspec.h>
15#include <asm/system.h>
Suresh Siddha13c88fb52008-07-10 11:16:52 -070016#include <asm/msr.h>
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010017
18#define ARCH_APICTIMER_STOPS_ON_C3 1
19
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010020/*
21 * Debugging macros
22 */
23#define APIC_QUIET 0
24#define APIC_VERBOSE 1
25#define APIC_DEBUG 2
26
27/*
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
32 */
33#define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
35 printk(s, ##a); \
36 } while (0)
37
38
Ingo Molnar160d8da2009-02-11 11:27:39 +010039#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010040extern void generic_apic_probe(void);
Ingo Molnar160d8da2009-02-11 11:27:39 +010041#else
42static inline void generic_apic_probe(void)
43{
44}
45#endif
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010046
47#ifdef CONFIG_X86_LOCAL_APIC
48
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +010049extern unsigned int apic_verbosity;
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010050extern int local_apic_timer_c2_ok;
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010051
Yinghai Lu3c999f12008-06-20 16:11:20 -070052extern int disable_apic;
Ingo Molnar0939e4f2009-01-28 17:16:25 +010053
54#ifdef CONFIG_SMP
55extern void __inquire_remote_apic(int apicid);
56#else /* CONFIG_SMP */
57static inline void __inquire_remote_apic(int apicid)
58{
59}
60#endif /* CONFIG_SMP */
61
62static inline void default_inquire_remote_apic(int apicid)
63{
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
66}
67
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010068/*
69 * Basic functions accessing APICs.
70 */
71#ifdef CONFIG_PARAVIRT
72#include <asm/paravirt.h>
Thomas Gleixner96a388d2007-10-11 11:20:03 +020073#else
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010074#define setup_boot_clock setup_boot_APIC_clock
75#define setup_secondary_clock setup_secondary_APIC_clock
Thomas Gleixner96a388d2007-10-11 11:20:03 +020076#endif
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010077
Yinghai Lu129d8bc2009-02-25 21:20:50 -080078#ifdef CONFIG_X86_VSMP
Ravikiran G Thirumalaiaa7d8e25e2008-03-20 00:41:16 -070079extern int is_vsmp_box(void);
Yinghai Lu129d8bc2009-02-25 21:20:50 -080080#else
81static inline int is_vsmp_box(void)
82{
83 return 0;
84}
85#endif
Jaswinder Singh2b97df02008-07-23 17:13:14 +053086extern void xapic_wait_icr_idle(void);
87extern u32 safe_xapic_wait_icr_idle(void);
Jaswinder Singh2b97df02008-07-23 17:13:14 +053088extern void xapic_icr_write(u32, u32);
89extern int setup_profiling_timer(unsigned int);
Ravikiran G Thirumalaiaa7d8e25e2008-03-20 00:41:16 -070090
Suresh Siddha1b374e42008-07-10 11:16:49 -070091static inline void native_apic_mem_write(u32 reg, u32 v)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010092{
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +010093 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010094
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +010095 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
96 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
97 ASM_OUTPUT2("0" (v), "m" (*addr)));
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010098}
99
Suresh Siddha1b374e42008-07-10 11:16:49 -0700100static inline u32 native_apic_mem_read(u32 reg)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100101{
102 return *((volatile u32 *)(APIC_BASE + reg));
103}
104
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800105extern void native_apic_wait_icr_idle(void);
106extern u32 native_safe_apic_wait_icr_idle(void);
107extern void native_apic_icr_write(u32 low, u32 id);
108extern u64 native_apic_icr_read(void);
109
110#ifdef CONFIG_X86_X2APIC
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700111static inline void native_apic_msr_write(u32 reg, u32 v)
112{
113 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
114 reg == APIC_LVR)
115 return;
116
117 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
118}
119
120static inline u32 native_apic_msr_read(u32 reg)
121{
122 u32 low, high;
123
124 if (reg == APIC_DFR)
125 return -1;
126
127 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
128 return low;
129}
130
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800131static inline void native_x2apic_wait_icr_idle(void)
132{
133 /* no need to wait for icr idle in x2apic */
134 return;
135}
136
137static inline u32 native_safe_x2apic_wait_icr_idle(void)
138{
139 /* no need to wait for icr idle in x2apic */
140 return 0;
141}
142
143static inline void native_x2apic_icr_write(u32 low, u32 id)
144{
145 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
146}
147
148static inline u64 native_x2apic_icr_read(void)
149{
150 unsigned long val;
151
152 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
153 return val;
154}
155
Suresh Siddhaef1f87a2009-02-21 14:23:21 -0800156extern int x2apic, x2apic_phys;
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700157extern void check_x2apic(void);
158extern void enable_x2apic(void);
159extern void enable_IR_x2apic(void);
160extern void x2apic_icr_write(u32 low, u32 id);
Yinghai Lua11b5ab2008-09-03 16:58:31 -0700161static inline int x2apic_enabled(void)
162{
163 int msr, msr2;
164
165 if (!cpu_has_x2apic)
166 return 0;
167
168 rdmsr(MSR_IA32_APICBASE, msr, msr2);
169 if (msr & X2APIC_ENABLE)
170 return 1;
171 return 0;
172}
173#else
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800174static inline void check_x2apic(void)
175{
176}
177static inline void enable_x2apic(void)
178{
179}
180static inline void enable_IR_x2apic(void)
181{
182}
183static inline int x2apic_enabled(void)
184{
185 return 0;
186}
Yinghai Luc535b6a2008-07-11 18:41:54 -0700187#endif
Suresh Siddha1b374e42008-07-10 11:16:49 -0700188
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100189extern int get_physical_broadcast(void);
190
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800191#ifdef CONFIG_X86_X2APIC
Suresh Siddha89027d32008-07-10 11:16:56 -0700192static inline void ack_x2APIC_irq(void)
193{
194 /* Docs say use 0 for future compatibility */
195 native_apic_msr_write(APIC_EOI, 0);
196}
197#endif
198
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100199extern int lapic_get_maxlvt(void);
200extern void clear_local_APIC(void);
201extern void connect_bsp_APIC(void);
202extern void disconnect_bsp_APIC(int virt_wire_setup);
203extern void disable_local_APIC(void);
204extern void lapic_shutdown(void);
205extern int verify_local_APIC(void);
206extern void cache_APIC_registers(void);
207extern void sync_Arb_IDs(void);
208extern void init_bsp_APIC(void);
209extern void setup_local_APIC(void);
Andi Kleen739f33b2008-01-30 13:30:40 +0100210extern void end_local_APIC_setup(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100211extern void init_apic_mappings(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100212extern void setup_boot_APIC_clock(void);
213extern void setup_secondary_APIC_clock(void);
214extern int APIC_init_uniprocessor(void);
Jan Beuliche9427102008-01-30 13:31:24 +0100215extern void enable_NMI_through_LVT0(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100216
217/*
218 * On 32bit this is mach-xxx local
219 */
220#ifdef CONFIG_X86_64
Yinghai Lu8643f9d2008-02-19 03:21:06 -0800221extern void early_init_lapic_mapping(void);
Alok Kataria8fbbc4b2008-07-01 11:43:34 -0700222extern int apic_is_clustered_box(void);
223#else
224static inline int apic_is_clustered_box(void)
225{
226 return 0;
227}
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100228#endif
229
Robert Richter7b83dae2008-01-30 13:30:40 +0100230extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
231extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100232
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100233
234#else /* !CONFIG_X86_LOCAL_APIC */
235static inline void lapic_shutdown(void) { }
236#define local_apic_timer_c2_ok 1
Yinghai Luf3294a32008-06-27 01:41:56 -0700237static inline void init_apic_mappings(void) { }
Ivan Vecerad3ec5ca2008-11-11 14:33:44 +0100238static inline void disable_local_APIC(void) { }
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100239
240#endif /* !CONFIG_X86_LOCAL_APIC */
241
Ingo Molnar1f75ed02009-01-28 17:36:56 +0100242#ifdef CONFIG_X86_64
243#define SET_APIC_ID(x) (apic->set_apic_id(x))
244#else
245
Ingo Molnar1f75ed02009-01-28 17:36:56 +0100246#endif
247
Ingo Molnare2780a62009-02-17 13:52:29 +0100248/*
249 * Copyright 2004 James Cleverdon, IBM.
250 * Subject to the GNU Public License, v.2
251 *
252 * Generic APIC sub-arch data struct.
253 *
254 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
255 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
256 * James Cleverdon.
257 */
Ingo Molnarbe163a12009-02-17 16:28:46 +0100258struct apic {
Ingo Molnare2780a62009-02-17 13:52:29 +0100259 char *name;
260
261 int (*probe)(void);
262 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
263 int (*apic_id_registered)(void);
264
265 u32 irq_delivery_mode;
266 u32 irq_dest_mode;
267
268 const struct cpumask *(*target_cpus)(void);
269
270 int disable_esr;
271
272 int dest_logical;
273 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
274 unsigned long (*check_apicid_present)(int apicid);
275
276 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
277 void (*init_apic_ldr)(void);
278
279 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
280
281 void (*setup_apic_routing)(void);
282 int (*multi_timer_check)(int apic, int irq);
283 int (*apicid_to_node)(int logical_apicid);
284 int (*cpu_to_logical_apicid)(int cpu);
285 int (*cpu_present_to_apicid)(int mps_cpu);
286 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
287 void (*setup_portio_remap)(void);
288 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
289 void (*enable_apic_mode)(void);
290 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
291
292 /*
Ingo Molnarbe163a12009-02-17 16:28:46 +0100293 * When one of the next two hooks returns 1 the apic
Ingo Molnare2780a62009-02-17 13:52:29 +0100294 * is switched to this. Essentially they are additional
295 * probe functions:
296 */
297 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
298
299 unsigned int (*get_apic_id)(unsigned long x);
300 unsigned long (*set_apic_id)(unsigned int id);
301 unsigned long apic_id_mask;
302
303 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
304 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
305 const struct cpumask *andmask);
306
307 /* ipi */
308 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
309 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
310 int vector);
311 void (*send_IPI_allbutself)(int vector);
312 void (*send_IPI_all)(int vector);
313 void (*send_IPI_self)(int vector);
314
315 /* wakeup_secondary_cpu */
Ingo Molnar1f5bcab2009-02-26 13:51:40 +0100316 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
Ingo Molnare2780a62009-02-17 13:52:29 +0100317
318 int trampoline_phys_low;
319 int trampoline_phys_high;
320
321 void (*wait_for_init_deassert)(atomic_t *deassert);
322 void (*smp_callin_clear_local_apic)(void);
Ingo Molnare2780a62009-02-17 13:52:29 +0100323 void (*inquire_remote_apic)(int apicid);
324
325 /* apic ops */
326 u32 (*read)(u32 reg);
327 void (*write)(u32 reg, u32 v);
328 u64 (*icr_read)(void);
329 void (*icr_write)(u32 low, u32 high);
330 void (*wait_icr_idle)(void);
331 u32 (*safe_wait_icr_idle)(void);
332};
333
Ingo Molnar0917c012009-02-26 12:47:40 +0100334/*
335 * Pointer to the local APIC driver in use on this system (there's
336 * always just one such driver in use - the kernel decides via an
337 * early probing process which one it picks - and then sticks to it):
338 */
Ingo Molnarbe163a12009-02-17 16:28:46 +0100339extern struct apic *apic;
Ingo Molnar0917c012009-02-26 12:47:40 +0100340
341/*
342 * APIC functionality to boot other CPUs - only used on SMP:
343 */
344#ifdef CONFIG_SMP
Yinghai Lu2b6163b2009-02-25 20:50:49 -0800345extern atomic_t init_deasserted;
346extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
Ingo Molnar0917c012009-02-26 12:47:40 +0100347#endif
Ingo Molnare2780a62009-02-17 13:52:29 +0100348
349static inline u32 apic_read(u32 reg)
350{
351 return apic->read(reg);
352}
353
354static inline void apic_write(u32 reg, u32 val)
355{
356 apic->write(reg, val);
357}
358
359static inline u64 apic_icr_read(void)
360{
361 return apic->icr_read();
362}
363
364static inline void apic_icr_write(u32 low, u32 high)
365{
366 apic->icr_write(low, high);
367}
368
369static inline void apic_wait_icr_idle(void)
370{
371 apic->wait_icr_idle();
372}
373
374static inline u32 safe_apic_wait_icr_idle(void)
375{
376 return apic->safe_wait_icr_idle();
377}
378
379
380static inline void ack_APIC_irq(void)
381{
382 /*
383 * ack_APIC_irq() actually gets compiled as a single instruction
384 * ... yummie.
385 */
386
387 /* Docs say use 0 for future compatibility */
388 apic_write(APIC_EOI, 0);
389}
390
391static inline unsigned default_get_apic_id(unsigned long x)
392{
393 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
394
395 if (APIC_XAPIC(ver))
396 return (x >> 24) & 0xFF;
397 else
398 return (x >> 24) & 0x0F;
399}
400
401/*
402 * Warm reset vector default position:
403 */
404#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
405#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
406
Yinghai Lu2b6163b2009-02-25 20:50:49 -0800407#ifdef CONFIG_X86_64
Ingo Molnarbe163a12009-02-17 16:28:46 +0100408extern struct apic apic_flat;
409extern struct apic apic_physflat;
410extern struct apic apic_x2apic_cluster;
411extern struct apic apic_x2apic_phys;
Ingo Molnare2780a62009-02-17 13:52:29 +0100412extern int default_acpi_madt_oem_check(char *, char *);
413
414extern void apic_send_IPI_self(int vector);
415
Ingo Molnarbe163a12009-02-17 16:28:46 +0100416extern struct apic apic_x2apic_uv_x;
Ingo Molnare2780a62009-02-17 13:52:29 +0100417DECLARE_PER_CPU(int, x2apic_extra_bits);
418
419extern int default_cpu_present_to_apicid(int mps_cpu);
420extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
421#endif
422
423static inline void default_wait_for_init_deassert(atomic_t *deassert)
424{
425 while (!atomic_read(deassert))
426 cpu_relax();
427 return;
428}
429
430extern void generic_bigsmp_probe(void);
431
432
433#ifdef CONFIG_X86_LOCAL_APIC
434
435#include <asm/smp.h>
436
437#define APIC_DFR_VALUE (APIC_DFR_FLAT)
438
439static inline const struct cpumask *default_target_cpus(void)
440{
441#ifdef CONFIG_SMP
442 return cpu_online_mask;
443#else
444 return cpumask_of(0);
445#endif
446}
447
448DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
449
450
451static inline unsigned int read_apic_id(void)
452{
453 unsigned int reg;
454
455 reg = apic_read(APIC_ID);
456
457 return apic->get_apic_id(reg);
458}
459
460extern void default_setup_apic_routing(void);
461
462#ifdef CONFIG_X86_32
463/*
464 * Set up the logical destination ID.
465 *
466 * Intel recommends to set DFR, LDR and TPR before enabling
467 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
468 * document number 292116). So here it goes...
469 */
470extern void default_init_apic_ldr(void);
471
472static inline int default_apic_id_registered(void)
473{
474 return physid_isset(read_apic_id(), phys_cpu_present_map);
475}
476
477static inline unsigned int
478default_cpu_mask_to_apicid(const struct cpumask *cpumask)
479{
480 return cpumask_bits(cpumask)[0];
481}
482
483static inline unsigned int
484default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
485 const struct cpumask *andmask)
486{
487 unsigned long mask1 = cpumask_bits(cpumask)[0];
488 unsigned long mask2 = cpumask_bits(andmask)[0];
489 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
490
491 return (unsigned int)(mask1 & mask2 & mask3);
492}
493
494static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
495{
496 return cpuid_apic >> index_msb;
497}
498
499extern int default_apicid_to_node(int logical_apicid);
500
501#endif
502
503static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
504{
505 return physid_isset(apicid, bitmap);
506}
507
508static inline unsigned long default_check_apicid_present(int bit)
509{
510 return physid_isset(bit, phys_cpu_present_map);
511}
512
513static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
514{
515 return phys_map;
516}
517
518/* Mapping from cpu number to logical apicid */
519static inline int default_cpu_to_logical_apicid(int cpu)
520{
521 return 1 << cpu;
522}
523
524static inline int __default_cpu_present_to_apicid(int mps_cpu)
525{
526 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
527 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
528 else
529 return BAD_APICID;
530}
531
532static inline int
533__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
534{
535 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
536}
537
538#ifdef CONFIG_X86_32
539static inline int default_cpu_present_to_apicid(int mps_cpu)
540{
541 return __default_cpu_present_to_apicid(mps_cpu);
542}
543
544static inline int
545default_check_phys_apicid_present(int boot_cpu_physical_apicid)
546{
547 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
548}
549#else
550extern int default_cpu_present_to_apicid(int mps_cpu);
551extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
552#endif
553
554static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
555{
556 return physid_mask_of_physid(phys_apicid);
557}
558
559#endif /* CONFIG_X86_LOCAL_APIC */
560
Ingo Molnar2f205bc2009-02-17 14:45:30 +0100561#ifdef CONFIG_X86_32
562extern u8 cpu_2_logical_apicid[NR_CPUS];
563#endif
564
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700565#endif /* _ASM_X86_APIC_H */