Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * S3C24XX IRQ handling |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 3 | * |
Ben Dooks | e02f866 | 2009-11-13 22:54:13 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2004 Simtec Electronics |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 5 | * Ben Dooks <ben@simtec.co.uk> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 6 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <linux/init.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 20 | #include <linux/slab.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 21 | #include <linux/module.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 22 | #include <linux/io.h> |
| 23 | #include <linux/err.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/ioport.h> |
Kay Sievers | edbaa60 | 2011-12-21 16:26:03 -0800 | [diff] [blame] | 26 | #include <linux/device.h> |
Heiko Stuebner | de11c58 | 2011-06-02 12:57:41 +0200 | [diff] [blame] | 27 | #include <linux/syscore_ops.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 28 | #include <linux/irqdomain.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 29 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 30 | #include <asm/mach/irq.h> |
| 31 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 32 | #include <mach/regs-irq.h> |
| 33 | #include <mach/regs-gpio.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 34 | |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 35 | #include <plat/cpu.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 36 | #include <plat/regs-irqtype.h> |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 37 | #include <plat/pm.h> |
| 38 | #include <plat/irq.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 39 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 40 | #define S3C_IRQTYPE_NONE 0 |
| 41 | #define S3C_IRQTYPE_EINT 1 |
| 42 | #define S3C_IRQTYPE_EDGE 2 |
| 43 | #define S3C_IRQTYPE_LEVEL 3 |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 44 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 45 | struct s3c_irq_data { |
| 46 | unsigned int type; |
| 47 | unsigned long parent_irq; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 48 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 49 | /* data gets filled during init */ |
| 50 | struct s3c_irq_intc *intc; |
| 51 | unsigned long sub_bits; |
| 52 | struct s3c_irq_intc *sub_intc; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 53 | }; |
| 54 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 55 | /* |
| 56 | * Sructure holding the controller data |
| 57 | * @reg_pending register holding pending irqs |
| 58 | * @reg_intpnd special register intpnd in main intc |
| 59 | * @reg_mask mask register |
| 60 | * @domain irq_domain of the controller |
| 61 | * @parent parent controller for ext and sub irqs |
| 62 | * @irqs irq-data, always s3c_irq_data[32] |
| 63 | */ |
| 64 | struct s3c_irq_intc { |
| 65 | void __iomem *reg_pending; |
| 66 | void __iomem *reg_intpnd; |
| 67 | void __iomem *reg_mask; |
| 68 | struct irq_domain *domain; |
| 69 | struct s3c_irq_intc *parent; |
| 70 | struct s3c_irq_data *irqs; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 71 | }; |
| 72 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 73 | static void s3c_irq_mask(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 74 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 75 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 76 | struct s3c_irq_intc *parent_intc = intc->parent; |
| 77 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; |
| 78 | struct s3c_irq_data *parent_data; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 79 | unsigned long mask; |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 80 | unsigned int irqno; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 81 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 82 | mask = __raw_readl(intc->reg_mask); |
| 83 | mask |= (1UL << data->hwirq); |
| 84 | __raw_writel(mask, intc->reg_mask); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 85 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 86 | if (parent_intc && irq_data->parent_irq) { |
| 87 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 88 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 89 | /* check to see if we need to mask the parent IRQ */ |
| 90 | if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { |
| 91 | irqno = irq_find_mapping(parent_intc->domain, |
| 92 | irq_data->parent_irq); |
| 93 | s3c_irq_mask(irq_get_irq_data(irqno)); |
| 94 | } |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 95 | } |
| 96 | } |
| 97 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 98 | static void s3c_irq_unmask(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 99 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 100 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 101 | struct s3c_irq_intc *parent_intc = intc->parent; |
| 102 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 103 | unsigned long mask; |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 104 | unsigned int irqno; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 105 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 106 | mask = __raw_readl(intc->reg_mask); |
| 107 | mask &= ~(1UL << data->hwirq); |
| 108 | __raw_writel(mask, intc->reg_mask); |
| 109 | |
| 110 | if (parent_intc && irq_data->parent_irq) { |
| 111 | irqno = irq_find_mapping(parent_intc->domain, |
| 112 | irq_data->parent_irq); |
| 113 | s3c_irq_unmask(irq_get_irq_data(irqno)); |
| 114 | } |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 115 | } |
| 116 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 117 | static inline void s3c_irq_ack(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 118 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 119 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 120 | unsigned long bitval = 1UL << data->hwirq; |
| 121 | |
| 122 | __raw_writel(bitval, intc->reg_pending); |
| 123 | if (intc->reg_intpnd) |
| 124 | __raw_writel(bitval, intc->reg_intpnd); |
| 125 | } |
| 126 | |
| 127 | static int s3c_irqext_type_set(void __iomem *gpcon_reg, |
| 128 | void __iomem *extint_reg, |
| 129 | unsigned long gpcon_offset, |
| 130 | unsigned long extint_offset, |
| 131 | unsigned int type) |
| 132 | { |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 133 | unsigned long newvalue = 0, value; |
| 134 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 135 | /* Set the GPIO to external interrupt mode */ |
| 136 | value = __raw_readl(gpcon_reg); |
| 137 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
| 138 | __raw_writel(value, gpcon_reg); |
| 139 | |
| 140 | /* Set the external interrupt to pointed trigger type */ |
| 141 | switch (type) |
| 142 | { |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 143 | case IRQ_TYPE_NONE: |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 144 | pr_warn("No edge setting!\n"); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 145 | break; |
| 146 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 147 | case IRQ_TYPE_EDGE_RISING: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 148 | newvalue = S3C2410_EXTINT_RISEEDGE; |
| 149 | break; |
| 150 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 151 | case IRQ_TYPE_EDGE_FALLING: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 152 | newvalue = S3C2410_EXTINT_FALLEDGE; |
| 153 | break; |
| 154 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 155 | case IRQ_TYPE_EDGE_BOTH: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 156 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
| 157 | break; |
| 158 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 159 | case IRQ_TYPE_LEVEL_LOW: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 160 | newvalue = S3C2410_EXTINT_LOWLEV; |
| 161 | break; |
| 162 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 163 | case IRQ_TYPE_LEVEL_HIGH: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 164 | newvalue = S3C2410_EXTINT_HILEV; |
| 165 | break; |
| 166 | |
| 167 | default: |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 168 | pr_err("No such irq type %d", type); |
| 169 | return -EINVAL; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | value = __raw_readl(extint_reg); |
| 173 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
| 174 | __raw_writel(value, extint_reg); |
| 175 | |
| 176 | return 0; |
| 177 | } |
| 178 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 179 | /* FIXME: make static when it's out of plat-samsung/irq.h */ |
| 180 | int s3c_irqext_type(struct irq_data *data, unsigned int type) |
| 181 | { |
| 182 | void __iomem *extint_reg; |
| 183 | void __iomem *gpcon_reg; |
| 184 | unsigned long gpcon_offset, extint_offset; |
| 185 | |
| 186 | if ((data->hwirq >= 4) && (data->hwirq <= 7)) { |
| 187 | gpcon_reg = S3C2410_GPFCON; |
| 188 | extint_reg = S3C24XX_EXTINT0; |
| 189 | gpcon_offset = (data->hwirq) * 2; |
| 190 | extint_offset = (data->hwirq) * 4; |
| 191 | } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { |
| 192 | gpcon_reg = S3C2410_GPGCON; |
| 193 | extint_reg = S3C24XX_EXTINT1; |
| 194 | gpcon_offset = (data->hwirq - 8) * 2; |
| 195 | extint_offset = (data->hwirq - 8) * 4; |
| 196 | } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { |
| 197 | gpcon_reg = S3C2410_GPGCON; |
| 198 | extint_reg = S3C24XX_EXTINT2; |
| 199 | gpcon_offset = (data->hwirq - 8) * 2; |
| 200 | extint_offset = (data->hwirq - 16) * 4; |
| 201 | } else { |
| 202 | return -EINVAL; |
| 203 | } |
| 204 | |
| 205 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
| 206 | extint_offset, type); |
| 207 | } |
| 208 | |
| 209 | static int s3c_irqext0_type(struct irq_data *data, unsigned int type) |
| 210 | { |
| 211 | void __iomem *extint_reg; |
| 212 | void __iomem *gpcon_reg; |
| 213 | unsigned long gpcon_offset, extint_offset; |
| 214 | |
| 215 | if ((data->hwirq >= 0) && (data->hwirq <= 3)) { |
| 216 | gpcon_reg = S3C2410_GPFCON; |
| 217 | extint_reg = S3C24XX_EXTINT0; |
| 218 | gpcon_offset = (data->hwirq) * 2; |
| 219 | extint_offset = (data->hwirq) * 4; |
| 220 | } else { |
| 221 | return -EINVAL; |
| 222 | } |
| 223 | |
| 224 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
| 225 | extint_offset, type); |
| 226 | } |
| 227 | |
| 228 | struct irq_chip s3c_irq_chip = { |
| 229 | .name = "s3c", |
| 230 | .irq_ack = s3c_irq_ack, |
| 231 | .irq_mask = s3c_irq_mask, |
| 232 | .irq_unmask = s3c_irq_unmask, |
| 233 | .irq_set_wake = s3c_irq_wake |
| 234 | }; |
| 235 | |
| 236 | struct irq_chip s3c_irq_level_chip = { |
| 237 | .name = "s3c-level", |
| 238 | .irq_mask = s3c_irq_mask, |
| 239 | .irq_unmask = s3c_irq_unmask, |
| 240 | .irq_ack = s3c_irq_ack, |
| 241 | }; |
| 242 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 243 | static struct irq_chip s3c_irqext_chip = { |
| 244 | .name = "s3c-ext", |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 245 | .irq_mask = s3c_irq_mask, |
| 246 | .irq_unmask = s3c_irq_unmask, |
| 247 | .irq_ack = s3c_irq_ack, |
Lennert Buytenhek | 57436c2d | 2011-01-03 19:15:54 +0900 | [diff] [blame] | 248 | .irq_set_type = s3c_irqext_type, |
Mark Brown | f5aeffb | 2010-12-02 14:35:38 +0900 | [diff] [blame] | 249 | .irq_set_wake = s3c_irqext_wake |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 250 | }; |
| 251 | |
| 252 | static struct irq_chip s3c_irq_eint0t4 = { |
| 253 | .name = "s3c-ext0", |
Lennert Buytenhek | 57436c2d | 2011-01-03 19:15:54 +0900 | [diff] [blame] | 254 | .irq_ack = s3c_irq_ack, |
| 255 | .irq_mask = s3c_irq_mask, |
| 256 | .irq_unmask = s3c_irq_unmask, |
| 257 | .irq_set_wake = s3c_irq_wake, |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 258 | .irq_set_type = s3c_irqext0_type, |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 259 | }; |
| 260 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 261 | static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 262 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 263 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 264 | struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; |
| 265 | struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; |
| 266 | struct s3c_irq_intc *sub_intc = irq_data->sub_intc; |
| 267 | unsigned long src; |
| 268 | unsigned long msk; |
| 269 | unsigned int n; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 270 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 271 | chained_irq_enter(chip, desc); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 272 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 273 | src = __raw_readl(sub_intc->reg_pending); |
| 274 | msk = __raw_readl(sub_intc->reg_mask); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 275 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 276 | src &= ~msk; |
| 277 | src &= irq_data->sub_bits; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 278 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 279 | while (src) { |
| 280 | n = __ffs(src); |
| 281 | src &= ~(1 << n); |
| 282 | generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 283 | } |
| 284 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 285 | chained_irq_exit(chip, desc); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 286 | } |
| 287 | |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 288 | #ifdef CONFIG_FIQ |
| 289 | /** |
| 290 | * s3c24xx_set_fiq - set the FIQ routing |
| 291 | * @irq: IRQ number to route to FIQ on processor. |
| 292 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. |
| 293 | * |
| 294 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If |
| 295 | * @on is true, the @irq is checked to see if it can be routed and the |
| 296 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ |
| 297 | * routing is cleared, regardless of which @irq is specified. |
| 298 | */ |
| 299 | int s3c24xx_set_fiq(unsigned int irq, bool on) |
| 300 | { |
| 301 | u32 intmod; |
| 302 | unsigned offs; |
| 303 | |
| 304 | if (on) { |
| 305 | offs = irq - FIQ_START; |
| 306 | if (offs > 31) |
| 307 | return -EINVAL; |
| 308 | |
| 309 | intmod = 1 << offs; |
| 310 | } else { |
| 311 | intmod = 0; |
| 312 | } |
| 313 | |
| 314 | __raw_writel(intmod, S3C2410_INTMOD); |
| 315 | return 0; |
| 316 | } |
Ben Dooks | 0f13c82 | 2009-12-07 14:51:38 +0000 | [diff] [blame] | 317 | |
| 318 | EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 319 | #endif |
| 320 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 321 | static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, |
| 322 | irq_hw_number_t hw) |
| 323 | { |
| 324 | struct s3c_irq_intc *intc = h->host_data; |
| 325 | struct s3c_irq_data *irq_data = &intc->irqs[hw]; |
| 326 | struct s3c_irq_intc *parent_intc; |
| 327 | struct s3c_irq_data *parent_irq_data; |
| 328 | unsigned int irqno; |
| 329 | |
| 330 | if (!intc) { |
| 331 | pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); |
| 332 | return -EINVAL; |
| 333 | } |
| 334 | |
| 335 | if (!irq_data) { |
| 336 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); |
| 337 | return -EINVAL; |
| 338 | } |
| 339 | |
| 340 | /* attach controller pointer to irq_data */ |
| 341 | irq_data->intc = intc; |
| 342 | |
| 343 | /* set handler and flags */ |
| 344 | switch (irq_data->type) { |
| 345 | case S3C_IRQTYPE_NONE: |
| 346 | return 0; |
| 347 | case S3C_IRQTYPE_EINT: |
| 348 | if (irq_data->parent_irq) |
| 349 | irq_set_chip_and_handler(virq, &s3c_irqext_chip, |
| 350 | handle_edge_irq); |
| 351 | else |
| 352 | irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, |
| 353 | handle_edge_irq); |
| 354 | break; |
| 355 | case S3C_IRQTYPE_EDGE: |
| 356 | if (irq_data->parent_irq) |
| 357 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
| 358 | handle_edge_irq); |
| 359 | else |
| 360 | irq_set_chip_and_handler(virq, &s3c_irq_chip, |
| 361 | handle_edge_irq); |
| 362 | break; |
| 363 | case S3C_IRQTYPE_LEVEL: |
| 364 | if (irq_data->parent_irq) |
| 365 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
| 366 | handle_level_irq); |
| 367 | else |
| 368 | irq_set_chip_and_handler(virq, &s3c_irq_chip, |
| 369 | handle_level_irq); |
| 370 | break; |
| 371 | default: |
| 372 | pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); |
| 373 | return -EINVAL; |
| 374 | } |
| 375 | set_irq_flags(virq, IRQF_VALID); |
| 376 | |
| 377 | if (irq_data->parent_irq) { |
| 378 | parent_intc = intc->parent; |
| 379 | if (!parent_intc) { |
| 380 | pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", |
| 381 | hw); |
| 382 | goto err; |
| 383 | } |
| 384 | |
| 385 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; |
| 386 | if (!irq_data) { |
| 387 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", |
| 388 | hw); |
| 389 | goto err; |
| 390 | } |
| 391 | |
| 392 | parent_irq_data->sub_intc = intc; |
| 393 | parent_irq_data->sub_bits |= (1UL << hw); |
| 394 | |
| 395 | /* attach the demuxer to the parent irq */ |
| 396 | irqno = irq_find_mapping(parent_intc->domain, |
| 397 | irq_data->parent_irq); |
| 398 | if (!irqno) { |
| 399 | pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", |
| 400 | irq_data->parent_irq); |
| 401 | goto err; |
| 402 | } |
| 403 | irq_set_chained_handler(irqno, s3c_irq_demux); |
| 404 | } |
| 405 | |
| 406 | return 0; |
| 407 | |
| 408 | err: |
| 409 | set_irq_flags(virq, 0); |
| 410 | |
| 411 | /* the only error can result from bad mapping data*/ |
| 412 | return -EINVAL; |
| 413 | } |
| 414 | |
| 415 | static struct irq_domain_ops s3c24xx_irq_ops = { |
| 416 | .map = s3c24xx_irq_map, |
| 417 | .xlate = irq_domain_xlate_twocell, |
| 418 | }; |
| 419 | |
| 420 | static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) |
| 421 | { |
| 422 | void __iomem *reg_source; |
| 423 | unsigned long pend; |
| 424 | unsigned long last; |
| 425 | int i; |
| 426 | |
| 427 | /* if intpnd is set, read the next pending irq from there */ |
| 428 | reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; |
| 429 | |
| 430 | last = 0; |
| 431 | for (i = 0; i < 4; i++) { |
| 432 | pend = __raw_readl(reg_source); |
| 433 | |
| 434 | if (pend == 0 || pend == last) |
| 435 | break; |
| 436 | |
| 437 | __raw_writel(pend, intc->reg_pending); |
| 438 | if (intc->reg_intpnd) |
| 439 | __raw_writel(pend, intc->reg_intpnd); |
| 440 | |
| 441 | pr_info("irq: clearing pending status %08x\n", (int)pend); |
| 442 | last = pend; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, |
| 447 | struct s3c_irq_data *irq_data, |
| 448 | struct s3c_irq_intc *parent, |
| 449 | unsigned long address) |
| 450 | { |
| 451 | struct s3c_irq_intc *intc; |
| 452 | void __iomem *base = (void *)0xf6000000; /* static mapping */ |
| 453 | int irq_num; |
| 454 | int irq_start; |
| 455 | int irq_offset; |
| 456 | int ret; |
| 457 | |
| 458 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); |
| 459 | if (!intc) |
| 460 | return ERR_PTR(-ENOMEM); |
| 461 | |
| 462 | intc->irqs = irq_data; |
| 463 | |
| 464 | if (parent) |
| 465 | intc->parent = parent; |
| 466 | |
| 467 | /* select the correct data for the controller. |
| 468 | * Need to hard code the irq num start and offset |
| 469 | * to preserve the static mapping for now |
| 470 | */ |
| 471 | switch (address) { |
| 472 | case 0x4a000000: |
| 473 | pr_debug("irq: found main intc\n"); |
| 474 | intc->reg_pending = base; |
| 475 | intc->reg_mask = base + 0x08; |
| 476 | intc->reg_intpnd = base + 0x10; |
| 477 | irq_num = 32; |
| 478 | irq_start = S3C2410_IRQ(0); |
| 479 | irq_offset = 0; |
| 480 | break; |
| 481 | case 0x4a000018: |
| 482 | pr_debug("irq: found subintc\n"); |
| 483 | intc->reg_pending = base + 0x18; |
| 484 | intc->reg_mask = base + 0x1c; |
| 485 | irq_num = 29; |
| 486 | irq_start = S3C2410_IRQSUB(0); |
| 487 | irq_offset = 0; |
| 488 | break; |
| 489 | case 0x4a000040: |
| 490 | pr_debug("irq: found intc2\n"); |
| 491 | intc->reg_pending = base + 0x40; |
| 492 | intc->reg_mask = base + 0x48; |
| 493 | intc->reg_intpnd = base + 0x50; |
| 494 | irq_num = 8; |
| 495 | irq_start = S3C2416_IRQ(0); |
| 496 | irq_offset = 0; |
| 497 | break; |
| 498 | case 0x560000a4: |
| 499 | pr_debug("irq: found eintc\n"); |
| 500 | base = (void *)0xfd000000; |
| 501 | |
| 502 | intc->reg_mask = base + 0xa4; |
| 503 | intc->reg_pending = base + 0x08; |
| 504 | irq_num = 20; |
| 505 | irq_start = S3C2410_IRQ(32); |
| 506 | irq_offset = 4; |
| 507 | break; |
| 508 | default: |
| 509 | pr_err("irq: unsupported controller address\n"); |
| 510 | ret = -EINVAL; |
| 511 | goto err; |
| 512 | } |
| 513 | |
| 514 | /* now that all the data is complete, init the irq-domain */ |
| 515 | s3c24xx_clear_intc(intc); |
| 516 | intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, |
| 517 | irq_offset, &s3c24xx_irq_ops, |
| 518 | intc); |
| 519 | if (!intc->domain) { |
| 520 | pr_err("irq: could not create irq-domain\n"); |
| 521 | ret = -EINVAL; |
| 522 | goto err; |
| 523 | } |
| 524 | |
| 525 | return intc; |
| 526 | |
| 527 | err: |
| 528 | kfree(intc); |
| 529 | return ERR_PTR(ret); |
| 530 | } |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 531 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 532 | /* s3c24xx_init_irq |
| 533 | * |
| 534 | * Initialise S3C2410 IRQ system |
| 535 | */ |
| 536 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 537 | static struct s3c_irq_data init_base[32] = { |
| 538 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 539 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 540 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 541 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 542 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 543 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 544 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 545 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 546 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 547 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ |
| 548 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 549 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 550 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 551 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 552 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 553 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 554 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ |
| 555 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ |
| 556 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ |
| 557 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ |
| 558 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ |
| 559 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ |
| 560 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 561 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 562 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 563 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 564 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 565 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 566 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 567 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ |
| 568 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 569 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
| 570 | }; |
| 571 | |
| 572 | static struct s3c_irq_data init_eint[32] = { |
| 573 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 574 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 575 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 576 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 577 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ |
| 578 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ |
| 579 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ |
| 580 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ |
| 581 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ |
| 582 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ |
| 583 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ |
| 584 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ |
| 585 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ |
| 586 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ |
| 587 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ |
| 588 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ |
| 589 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ |
| 590 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ |
| 591 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ |
| 592 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ |
| 593 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ |
| 594 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ |
| 595 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ |
| 596 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ |
| 597 | }; |
| 598 | |
| 599 | static struct s3c_irq_data init_subint[32] = { |
| 600 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 601 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 602 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 603 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 604 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 605 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 606 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 607 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 608 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 609 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 610 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 611 | }; |
| 612 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 613 | void __init s3c24xx_init_irq(void) |
| 614 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 615 | struct s3c_irq_intc *main_intc; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 616 | |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 617 | #ifdef CONFIG_FIQ |
Shawn Guo | bc89663 | 2012-06-28 14:42:08 +0800 | [diff] [blame] | 618 | init_FIQ(FIQ_START); |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 619 | #endif |
| 620 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 621 | main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); |
| 622 | if (IS_ERR(main_intc)) { |
| 623 | pr_err("irq: could not create main interrupt controller\n"); |
| 624 | return; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 625 | } |
| 626 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame^] | 627 | s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); |
| 628 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 629 | } |
Heiko Stuebner | de11c58 | 2011-06-02 12:57:41 +0200 | [diff] [blame] | 630 | |
| 631 | struct syscore_ops s3c24xx_irq_syscore_ops = { |
| 632 | .suspend = s3c24xx_irq_suspend, |
| 633 | .resume = s3c24xx_irq_resume, |
| 634 | }; |