Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 19 | #include <plat/i2c.h> |
| 20 | #include <plat/omap24xx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 21 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 22 | #include "omap_hwmod_common_data.h" |
| 23 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 24 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 25 | #include "prm-regbits-24xx.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 26 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 27 | /* |
| 28 | * OMAP2420 hardware module integration data |
| 29 | * |
| 30 | * ALl of the data in this section should be autogeneratable from the |
| 31 | * TI hardware database or other technical documentation. Data that |
| 32 | * is driver-specific or driver-kernel integration-specific belongs |
| 33 | * elsewhere. |
| 34 | */ |
| 35 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 36 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 37 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 38 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 39 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 40 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 41 | |
| 42 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 43 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 44 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 45 | .slave = &omap2420_l4_core_hwmod, |
| 46 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 47 | }; |
| 48 | |
| 49 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 50 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 51 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 52 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 53 | .user = OCP_USER_MPU, |
| 54 | }; |
| 55 | |
| 56 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 57 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 58 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 62 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 63 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 67 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 68 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 69 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 70 | .masters = omap2420_l3_main_masters, |
| 71 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 72 | .slaves = omap2420_l3_main_slaves, |
| 73 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 74 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 75 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 79 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 80 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 81 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 82 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 83 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 84 | |
| 85 | /* L4_CORE -> L4_WKUP interface */ |
| 86 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 87 | .master = &omap2420_l4_core_hwmod, |
| 88 | .slave = &omap2420_l4_wkup_hwmod, |
| 89 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 90 | }; |
| 91 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 92 | /* L4 CORE -> UART1 interface */ |
| 93 | static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { |
| 94 | { |
| 95 | .pa_start = OMAP2_UART1_BASE, |
| 96 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 97 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 102 | .master = &omap2420_l4_core_hwmod, |
| 103 | .slave = &omap2420_uart1_hwmod, |
| 104 | .clk = "uart1_ick", |
| 105 | .addr = omap2420_uart1_addr_space, |
| 106 | .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), |
| 107 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 108 | }; |
| 109 | |
| 110 | /* L4 CORE -> UART2 interface */ |
| 111 | static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { |
| 112 | { |
| 113 | .pa_start = OMAP2_UART2_BASE, |
| 114 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 115 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 116 | }, |
| 117 | }; |
| 118 | |
| 119 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 120 | .master = &omap2420_l4_core_hwmod, |
| 121 | .slave = &omap2420_uart2_hwmod, |
| 122 | .clk = "uart2_ick", |
| 123 | .addr = omap2420_uart2_addr_space, |
| 124 | .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), |
| 125 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 126 | }; |
| 127 | |
| 128 | /* L4 PER -> UART3 interface */ |
| 129 | static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { |
| 130 | { |
| 131 | .pa_start = OMAP2_UART3_BASE, |
| 132 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 133 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 134 | }, |
| 135 | }; |
| 136 | |
| 137 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 138 | .master = &omap2420_l4_core_hwmod, |
| 139 | .slave = &omap2420_uart3_hwmod, |
| 140 | .clk = "uart3_ick", |
| 141 | .addr = omap2420_uart3_addr_space, |
| 142 | .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), |
| 143 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 144 | }; |
| 145 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 146 | /* I2C IP block address space length (in bytes) */ |
| 147 | #define OMAP2_I2C_AS_LEN 128 |
| 148 | |
| 149 | /* L4 CORE -> I2C1 interface */ |
| 150 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { |
| 151 | { |
| 152 | .pa_start = 0x48070000, |
| 153 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 154 | .flags = ADDR_TYPE_RT, |
| 155 | }, |
| 156 | }; |
| 157 | |
| 158 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 159 | .master = &omap2420_l4_core_hwmod, |
| 160 | .slave = &omap2420_i2c1_hwmod, |
| 161 | .clk = "i2c1_ick", |
| 162 | .addr = omap2420_i2c1_addr_space, |
| 163 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), |
| 164 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 165 | }; |
| 166 | |
| 167 | /* L4 CORE -> I2C2 interface */ |
| 168 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { |
| 169 | { |
| 170 | .pa_start = 0x48072000, |
| 171 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 172 | .flags = ADDR_TYPE_RT, |
| 173 | }, |
| 174 | }; |
| 175 | |
| 176 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 177 | .master = &omap2420_l4_core_hwmod, |
| 178 | .slave = &omap2420_i2c2_hwmod, |
| 179 | .clk = "i2c2_ick", |
| 180 | .addr = omap2420_i2c2_addr_space, |
| 181 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), |
| 182 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 183 | }; |
| 184 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 185 | /* Slave interfaces on the L4_CORE interconnect */ |
| 186 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 187 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 188 | }; |
| 189 | |
| 190 | /* Master interfaces on the L4_CORE interconnect */ |
| 191 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 192 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 193 | &omap2_l4_core__uart1, |
| 194 | &omap2_l4_core__uart2, |
| 195 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 196 | &omap2420_l4_core__i2c1, |
| 197 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | /* L4 CORE */ |
| 201 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 202 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 203 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 204 | .masters = omap2420_l4_core_masters, |
| 205 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 206 | .slaves = omap2420_l4_core_slaves, |
| 207 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 209 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 213 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 214 | &omap2420_l4_core__l4_wkup, |
| 215 | }; |
| 216 | |
| 217 | /* Master interfaces on the L4_WKUP interconnect */ |
| 218 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 219 | }; |
| 220 | |
| 221 | /* L4 WKUP */ |
| 222 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 223 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 224 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 225 | .masters = omap2420_l4_wkup_masters, |
| 226 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 227 | .slaves = omap2420_l4_wkup_slaves, |
| 228 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 229 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 230 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | /* Master interfaces on the MPU device */ |
| 234 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 235 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | /* MPU */ |
| 239 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 240 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 241 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 242 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 243 | .masters = omap2420_mpu_masters, |
| 244 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 246 | }; |
| 247 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 248 | /* |
| 249 | * IVA1 interface data |
| 250 | */ |
| 251 | |
| 252 | /* IVA <- L3 interface */ |
| 253 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 254 | .master = &omap2420_l3_main_hwmod, |
| 255 | .slave = &omap2420_iva_hwmod, |
| 256 | .clk = "iva1_ifck", |
| 257 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 258 | }; |
| 259 | |
| 260 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 261 | &omap2420_l3__iva, |
| 262 | }; |
| 263 | |
| 264 | /* |
| 265 | * IVA2 (IVA2) |
| 266 | */ |
| 267 | |
| 268 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 269 | .name = "iva", |
| 270 | .class = &iva_hwmod_class, |
| 271 | .masters = omap2420_iva_masters, |
| 272 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 273 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 274 | }; |
| 275 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 276 | /* l4_wkup -> wd_timer2 */ |
| 277 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 278 | { |
| 279 | .pa_start = 0x48022000, |
| 280 | .pa_end = 0x4802207f, |
| 281 | .flags = ADDR_TYPE_RT |
| 282 | }, |
| 283 | }; |
| 284 | |
| 285 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 286 | .master = &omap2420_l4_wkup_hwmod, |
| 287 | .slave = &omap2420_wd_timer2_hwmod, |
| 288 | .clk = "mpu_wdt_ick", |
| 289 | .addr = omap2420_wd_timer2_addrs, |
| 290 | .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), |
| 291 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 292 | }; |
| 293 | |
| 294 | /* |
| 295 | * 'wd_timer' class |
| 296 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 297 | * overflow condition |
| 298 | */ |
| 299 | |
| 300 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 301 | .rev_offs = 0x0000, |
| 302 | .sysc_offs = 0x0010, |
| 303 | .syss_offs = 0x0014, |
| 304 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 305 | SYSC_HAS_AUTOIDLE), |
| 306 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 307 | }; |
| 308 | |
| 309 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
| 310 | .name = "wd_timer", |
| 311 | .sysc = &omap2420_wd_timer_sysc, |
| 312 | }; |
| 313 | |
| 314 | /* wd_timer2 */ |
| 315 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 316 | &omap2420_l4_wkup__wd_timer2, |
| 317 | }; |
| 318 | |
| 319 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 320 | .name = "wd_timer2", |
| 321 | .class = &omap2420_wd_timer_hwmod_class, |
| 322 | .main_clk = "mpu_wdt_fck", |
| 323 | .prcm = { |
| 324 | .omap2 = { |
| 325 | .prcm_reg_id = 1, |
| 326 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 327 | .module_offs = WKUP_MOD, |
| 328 | .idlest_reg_id = 1, |
| 329 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 330 | }, |
| 331 | }, |
| 332 | .slaves = omap2420_wd_timer2_slaves, |
| 333 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 334 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 335 | }; |
| 336 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 337 | /* UART */ |
| 338 | |
| 339 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 340 | .rev_offs = 0x50, |
| 341 | .sysc_offs = 0x54, |
| 342 | .syss_offs = 0x58, |
| 343 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 344 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 345 | SYSC_HAS_AUTOIDLE), |
| 346 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 347 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 348 | }; |
| 349 | |
| 350 | static struct omap_hwmod_class uart_class = { |
| 351 | .name = "uart", |
| 352 | .sysc = &uart_sysc, |
| 353 | }; |
| 354 | |
| 355 | /* UART1 */ |
| 356 | |
| 357 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 358 | { .irq = INT_24XX_UART1_IRQ, }, |
| 359 | }; |
| 360 | |
| 361 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 362 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 363 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 364 | }; |
| 365 | |
| 366 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 367 | &omap2_l4_core__uart1, |
| 368 | }; |
| 369 | |
| 370 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 371 | .name = "uart1", |
| 372 | .mpu_irqs = uart1_mpu_irqs, |
| 373 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 374 | .sdma_reqs = uart1_sdma_reqs, |
| 375 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 376 | .main_clk = "uart1_fck", |
| 377 | .prcm = { |
| 378 | .omap2 = { |
| 379 | .module_offs = CORE_MOD, |
| 380 | .prcm_reg_id = 1, |
| 381 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 382 | .idlest_reg_id = 1, |
| 383 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 384 | }, |
| 385 | }, |
| 386 | .slaves = omap2420_uart1_slaves, |
| 387 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 388 | .class = &uart_class, |
| 389 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 390 | }; |
| 391 | |
| 392 | /* UART2 */ |
| 393 | |
| 394 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 395 | { .irq = INT_24XX_UART2_IRQ, }, |
| 396 | }; |
| 397 | |
| 398 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 399 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 400 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 401 | }; |
| 402 | |
| 403 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 404 | &omap2_l4_core__uart2, |
| 405 | }; |
| 406 | |
| 407 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 408 | .name = "uart2", |
| 409 | .mpu_irqs = uart2_mpu_irqs, |
| 410 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 411 | .sdma_reqs = uart2_sdma_reqs, |
| 412 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 413 | .main_clk = "uart2_fck", |
| 414 | .prcm = { |
| 415 | .omap2 = { |
| 416 | .module_offs = CORE_MOD, |
| 417 | .prcm_reg_id = 1, |
| 418 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 419 | .idlest_reg_id = 1, |
| 420 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 421 | }, |
| 422 | }, |
| 423 | .slaves = omap2420_uart2_slaves, |
| 424 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 425 | .class = &uart_class, |
| 426 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 427 | }; |
| 428 | |
| 429 | /* UART3 */ |
| 430 | |
| 431 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 432 | { .irq = INT_24XX_UART3_IRQ, }, |
| 433 | }; |
| 434 | |
| 435 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 436 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 437 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 438 | }; |
| 439 | |
| 440 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 441 | &omap2_l4_core__uart3, |
| 442 | }; |
| 443 | |
| 444 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 445 | .name = "uart3", |
| 446 | .mpu_irqs = uart3_mpu_irqs, |
| 447 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 448 | .sdma_reqs = uart3_sdma_reqs, |
| 449 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 450 | .main_clk = "uart3_fck", |
| 451 | .prcm = { |
| 452 | .omap2 = { |
| 453 | .module_offs = CORE_MOD, |
| 454 | .prcm_reg_id = 2, |
| 455 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 456 | .idlest_reg_id = 2, |
| 457 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 458 | }, |
| 459 | }, |
| 460 | .slaves = omap2420_uart3_slaves, |
| 461 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 462 | .class = &uart_class, |
| 463 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 464 | }; |
| 465 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 466 | /* I2C common */ |
| 467 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 468 | .rev_offs = 0x00, |
| 469 | .sysc_offs = 0x20, |
| 470 | .syss_offs = 0x10, |
| 471 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 472 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 473 | }; |
| 474 | |
| 475 | static struct omap_hwmod_class i2c_class = { |
| 476 | .name = "i2c", |
| 477 | .sysc = &i2c_sysc, |
| 478 | }; |
| 479 | |
| 480 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 481 | |
| 482 | /* I2C1 */ |
| 483 | |
| 484 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 485 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 486 | }; |
| 487 | |
| 488 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 489 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 490 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 491 | }; |
| 492 | |
| 493 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 494 | &omap2420_l4_core__i2c1, |
| 495 | }; |
| 496 | |
| 497 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 498 | .name = "i2c1", |
| 499 | .mpu_irqs = i2c1_mpu_irqs, |
| 500 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 501 | .sdma_reqs = i2c1_sdma_reqs, |
| 502 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 503 | .main_clk = "i2c1_fck", |
| 504 | .prcm = { |
| 505 | .omap2 = { |
| 506 | .module_offs = CORE_MOD, |
| 507 | .prcm_reg_id = 1, |
| 508 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 509 | .idlest_reg_id = 1, |
| 510 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 511 | }, |
| 512 | }, |
| 513 | .slaves = omap2420_i2c1_slaves, |
| 514 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 515 | .class = &i2c_class, |
| 516 | .dev_attr = &i2c_dev_attr, |
| 517 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 518 | .flags = HWMOD_16BIT_REG, |
| 519 | }; |
| 520 | |
| 521 | /* I2C2 */ |
| 522 | |
| 523 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 524 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 525 | }; |
| 526 | |
| 527 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 528 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 529 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 530 | }; |
| 531 | |
| 532 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 533 | &omap2420_l4_core__i2c2, |
| 534 | }; |
| 535 | |
| 536 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 537 | .name = "i2c2", |
| 538 | .mpu_irqs = i2c2_mpu_irqs, |
| 539 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 540 | .sdma_reqs = i2c2_sdma_reqs, |
| 541 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 542 | .main_clk = "i2c2_fck", |
| 543 | .prcm = { |
| 544 | .omap2 = { |
| 545 | .module_offs = CORE_MOD, |
| 546 | .prcm_reg_id = 1, |
| 547 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 548 | .idlest_reg_id = 1, |
| 549 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 550 | }, |
| 551 | }, |
| 552 | .slaves = omap2420_i2c2_slaves, |
| 553 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 554 | .class = &i2c_class, |
| 555 | .dev_attr = &i2c_dev_attr, |
| 556 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 557 | .flags = HWMOD_16BIT_REG, |
| 558 | }; |
| 559 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 560 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 561 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 562 | &omap2420_l4_core_hwmod, |
| 563 | &omap2420_l4_wkup_hwmod, |
| 564 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 565 | &omap2420_iva_hwmod, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 566 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 567 | &omap2420_uart1_hwmod, |
| 568 | &omap2420_uart2_hwmod, |
| 569 | &omap2420_uart3_hwmod, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame^] | 570 | &omap2420_i2c1_hwmod, |
| 571 | &omap2420_i2c2_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 572 | NULL, |
| 573 | }; |
| 574 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 575 | int __init omap2420_hwmod_init(void) |
| 576 | { |
| 577 | return omap_hwmod_init(omap2420_hwmods); |
| 578 | } |