Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
| 29 | * |
| 30 | * This file gather function specific to RS600 which is the IGP of |
| 31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
| 32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
| 33 | * the avivo one, bios is an atombios, 3D block are the one of the |
| 34 | * R4XX family. The GART is different from the RS400 one and is very |
| 35 | * close to the one of the R600 family (R600 likely being an evolution |
| 36 | * of the RS600 GART block). |
| 37 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | #include "drmP.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 39 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 40 | #include "radeon_asic.h" |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 41 | #include "atom.h" |
| 42 | #include "rs600d.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 43 | |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 44 | #include "rs600_reg_safe.h" |
| 45 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 46 | void rs600_gpu_init(struct radeon_device *rdev); |
| 47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 49 | /* hpd for digital panel detect/disconnect */ |
| 50 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 51 | { |
| 52 | u32 tmp; |
| 53 | bool connected = false; |
| 54 | |
| 55 | switch (hpd) { |
| 56 | case RADEON_HPD_1: |
| 57 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
| 58 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
| 59 | connected = true; |
| 60 | break; |
| 61 | case RADEON_HPD_2: |
| 62 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
| 63 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
| 64 | connected = true; |
| 65 | break; |
| 66 | default: |
| 67 | break; |
| 68 | } |
| 69 | return connected; |
| 70 | } |
| 71 | |
| 72 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
| 73 | enum radeon_hpd_id hpd) |
| 74 | { |
| 75 | u32 tmp; |
| 76 | bool connected = rs600_hpd_sense(rdev, hpd); |
| 77 | |
| 78 | switch (hpd) { |
| 79 | case RADEON_HPD_1: |
| 80 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 81 | if (connected) |
| 82 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
| 83 | else |
| 84 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
| 85 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 86 | break; |
| 87 | case RADEON_HPD_2: |
| 88 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 89 | if (connected) |
| 90 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
| 91 | else |
| 92 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
| 93 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 94 | break; |
| 95 | default: |
| 96 | break; |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | void rs600_hpd_init(struct radeon_device *rdev) |
| 101 | { |
| 102 | struct drm_device *dev = rdev->ddev; |
| 103 | struct drm_connector *connector; |
| 104 | |
| 105 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 107 | switch (radeon_connector->hpd.hpd) { |
| 108 | case RADEON_HPD_1: |
| 109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| 110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
| 111 | rdev->irq.hpd[0] = true; |
| 112 | break; |
| 113 | case RADEON_HPD_2: |
| 114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| 115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
| 116 | rdev->irq.hpd[1] = true; |
| 117 | break; |
| 118 | default: |
| 119 | break; |
| 120 | } |
| 121 | } |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 122 | if (rdev->irq.installed) |
| 123 | rs600_irq_set(rdev); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | void rs600_hpd_fini(struct radeon_device *rdev) |
| 127 | { |
| 128 | struct drm_device *dev = rdev->ddev; |
| 129 | struct drm_connector *connector; |
| 130 | |
| 131 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 133 | switch (radeon_connector->hpd.hpd) { |
| 134 | case RADEON_HPD_1: |
| 135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| 136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
| 137 | rdev->irq.hpd[0] = false; |
| 138 | break; |
| 139 | case RADEON_HPD_2: |
| 140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| 141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
| 142 | rdev->irq.hpd[1] = false; |
| 143 | break; |
| 144 | default: |
| 145 | break; |
| 146 | } |
| 147 | } |
| 148 | } |
| 149 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 150 | void rs600_bm_disable(struct radeon_device *rdev) |
| 151 | { |
| 152 | u32 tmp; |
| 153 | |
| 154 | /* disable bus mastering */ |
| 155 | pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); |
| 156 | pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); |
| 157 | mdelay(1); |
| 158 | } |
| 159 | |
| 160 | int rs600_asic_reset(struct radeon_device *rdev) |
| 161 | { |
| 162 | u32 status, tmp; |
| 163 | |
| 164 | struct rv515_mc_save save; |
| 165 | |
| 166 | /* Stops all mc clients */ |
| 167 | rv515_mc_stop(rdev, &save); |
| 168 | status = RREG32(R_000E40_RBBM_STATUS); |
| 169 | if (!G_000E40_GUI_ACTIVE(status)) { |
| 170 | return 0; |
| 171 | } |
| 172 | status = RREG32(R_000E40_RBBM_STATUS); |
| 173 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 174 | /* stop CP */ |
| 175 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 176 | tmp = RREG32(RADEON_CP_RB_CNTL); |
| 177 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
| 178 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
| 179 | WREG32(RADEON_CP_RB_WPTR, 0); |
| 180 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 181 | pci_save_state(rdev->pdev); |
| 182 | /* disable bus mastering */ |
| 183 | rs600_bm_disable(rdev); |
| 184 | /* reset GA+VAP */ |
| 185 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
| 186 | S_0000F0_SOFT_RESET_GA(1)); |
| 187 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 188 | mdelay(500); |
| 189 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 190 | mdelay(1); |
| 191 | status = RREG32(R_000E40_RBBM_STATUS); |
| 192 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 193 | /* reset CP */ |
| 194 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
| 195 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 196 | mdelay(500); |
| 197 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 198 | mdelay(1); |
| 199 | status = RREG32(R_000E40_RBBM_STATUS); |
| 200 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 201 | /* reset MC */ |
| 202 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
| 203 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 204 | mdelay(500); |
| 205 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 206 | mdelay(1); |
| 207 | status = RREG32(R_000E40_RBBM_STATUS); |
| 208 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 209 | /* restore PCI & busmastering */ |
| 210 | pci_restore_state(rdev->pdev); |
| 211 | /* Check if GPU is idle */ |
| 212 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
| 213 | dev_err(rdev->dev, "failed to reset GPU\n"); |
| 214 | rdev->gpu_lockup = true; |
| 215 | return -1; |
| 216 | } |
| 217 | rv515_mc_resume(rdev, &save); |
| 218 | dev_info(rdev->dev, "GPU reset succeed\n"); |
| 219 | return 0; |
| 220 | } |
| 221 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | /* |
| 223 | * GART. |
| 224 | */ |
| 225 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
| 226 | { |
| 227 | uint32_t tmp; |
| 228 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 229 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 230 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| 231 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 233 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
Jerome Glisse | 30f69f3 | 2010-04-16 18:46:35 +0200 | [diff] [blame] | 234 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 235 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 236 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 237 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 238 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| 239 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
| 240 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 241 | } |
| 242 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 243 | int rs600_gart_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 244 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | int r; |
| 246 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 247 | if (rdev->gart.table.vram.robj) { |
| 248 | WARN(1, "RS600 GART already initialized.\n"); |
| 249 | return 0; |
| 250 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | /* Initialize common gart structure */ |
| 252 | r = radeon_gart_init(rdev); |
| 253 | if (r) { |
| 254 | return r; |
| 255 | } |
| 256 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 257 | return radeon_gart_table_vram_alloc(rdev); |
| 258 | } |
| 259 | |
| 260 | int rs600_gart_enable(struct radeon_device *rdev) |
| 261 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 262 | u32 tmp; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 263 | int r, i; |
| 264 | |
| 265 | if (rdev->gart.table.vram.robj == NULL) { |
| 266 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 267 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 269 | r = radeon_gart_table_vram_pin(rdev); |
| 270 | if (r) |
| 271 | return r; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 272 | radeon_gart_restore(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 273 | /* Enable bus master */ |
| 274 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
| 275 | WREG32(R_00004C_BUS_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | /* FIXME: setup default page */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 277 | WREG32_MC(R_000100_MC_PT0_CNTL, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 278 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
| 279 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| 280 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | for (i = 0; i < 19; i++) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 282 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 283 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
| 284 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
| 285 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
| 286 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
| 287 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
| 288 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
| 289 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
| 290 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 291 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 292 | /* enable first context */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 293 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 294 | S_000102_ENABLE_PAGE_TABLE(1) | |
| 295 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
| 296 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 297 | /* disable all other contexts */ |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 298 | for (i = 1; i < 8; i++) |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 299 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 300 | |
| 301 | /* setup the page table */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 302 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 303 | rdev->gart.table_addr); |
| 304 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
| 305 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 306 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 307 | |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 308 | /* System context maps to VRAM space */ |
| 309 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
| 310 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
| 311 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | /* enable page tables */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 313 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 314 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
| 315 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
| 316 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | rs600_gart_tlb_flush(rdev); |
| 318 | rdev->gart.ready = true; |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | void rs600_gart_disable(struct radeon_device *rdev) |
| 323 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 324 | u32 tmp; |
| 325 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | |
| 327 | /* FIXME: disable out of gart access */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 328 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
| 329 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
| 330 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 331 | if (rdev->gart.table.vram.robj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 332 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
| 333 | if (r == 0) { |
| 334 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
| 335 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
| 336 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
| 337 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
| 341 | void rs600_gart_fini(struct radeon_device *rdev) |
| 342 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 343 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 344 | rs600_gart_disable(rdev); |
| 345 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | #define R600_PTE_VALID (1 << 0) |
| 349 | #define R600_PTE_SYSTEM (1 << 1) |
| 350 | #define R600_PTE_SNOOPED (1 << 2) |
| 351 | #define R600_PTE_READABLE (1 << 5) |
| 352 | #define R600_PTE_WRITEABLE (1 << 6) |
| 353 | |
| 354 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| 355 | { |
| 356 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
| 357 | |
| 358 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| 359 | return -EINVAL; |
| 360 | } |
| 361 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
| 362 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
| 363 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
| 364 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
| 365 | return 0; |
| 366 | } |
| 367 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 368 | int rs600_irq_set(struct radeon_device *rdev) |
| 369 | { |
| 370 | uint32_t tmp = 0; |
| 371 | uint32_t mode_int = 0; |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 372 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
| 373 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
| 374 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
| 375 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 376 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 377 | if (!rdev->irq.installed) { |
| 378 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); |
| 379 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 380 | return -EINVAL; |
| 381 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 382 | if (rdev->irq.sw_int) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 383 | tmp |= S_000040_SW_INT_EN(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 384 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 385 | if (rdev->irq.gui_idle) { |
| 386 | tmp |= S_000040_GUI_IDLE(1); |
| 387 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 388 | if (rdev->irq.crtc_vblank_int[0]) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 389 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 390 | } |
| 391 | if (rdev->irq.crtc_vblank_int[1]) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 392 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 393 | } |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 394 | if (rdev->irq.hpd[0]) { |
| 395 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
| 396 | } |
| 397 | if (rdev->irq.hpd[1]) { |
| 398 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
| 399 | } |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 400 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
| 401 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 402 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
| 403 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
| 408 | { |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 409 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 410 | uint32_t irq_mask = S_000044_SW_INT(1); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 411 | u32 tmp; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 412 | |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 413 | /* the interrupt works, but the status bit is permanently asserted */ |
| 414 | if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { |
| 415 | if (!rdev->irq.gui_idle_acked) |
| 416 | irq_mask |= S_000044_GUI_IDLE_STAT(1); |
| 417 | } |
| 418 | |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 419 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 420 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
| 421 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
| 422 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
| 423 | S_006534_D1MODE_VBLANK_ACK(1)); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 424 | } |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 425 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
| 426 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
| 427 | S_006D34_D2MODE_VBLANK_ACK(1)); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 428 | } |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 429 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
| 430 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 431 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
| 432 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 433 | } |
| 434 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { |
| 435 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 436 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
| 437 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 438 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 439 | } else { |
| 440 | *r500_disp_int = 0; |
| 441 | } |
| 442 | |
| 443 | if (irqs) { |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 444 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 445 | } |
| 446 | return irqs & irq_mask; |
| 447 | } |
| 448 | |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 449 | void rs600_irq_disable(struct radeon_device *rdev) |
| 450 | { |
| 451 | u32 tmp; |
| 452 | |
| 453 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 454 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
| 455 | /* Wait and acknowledge irq */ |
| 456 | mdelay(1); |
| 457 | rs600_irq_ack(rdev, &tmp); |
| 458 | } |
| 459 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 460 | int rs600_irq_process(struct radeon_device *rdev) |
| 461 | { |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 462 | uint32_t status, msi_rearm; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 463 | uint32_t r500_disp_int; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 464 | bool queue_hotplug = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 465 | |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 466 | /* reset gui idle ack. the status bit is broken */ |
| 467 | rdev->irq.gui_idle_acked = false; |
| 468 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 469 | status = rs600_irq_ack(rdev, &r500_disp_int); |
| 470 | if (!status && !r500_disp_int) { |
| 471 | return IRQ_NONE; |
| 472 | } |
| 473 | while (status || r500_disp_int) { |
| 474 | /* SW interrupt */ |
Luca Tettamanti | 43b19f1 | 2009-12-28 22:53:05 +0100 | [diff] [blame] | 475 | if (G_000044_SW_INT(status)) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 476 | radeon_fence_process(rdev); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 477 | /* GUI idle */ |
| 478 | if (G_000040_GUI_IDLE(status)) { |
| 479 | rdev->irq.gui_idle_acked = true; |
| 480 | rdev->pm.gui_idle = true; |
| 481 | wake_up(&rdev->irq.idle_queue); |
| 482 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 483 | /* Vertical blank interrupts */ |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 484 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 485 | drm_handle_vblank(rdev->ddev, 0); |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 486 | rdev->pm.vblank_sync = true; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 487 | wake_up(&rdev->irq.vblank_queue); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 488 | } |
| 489 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 490 | drm_handle_vblank(rdev->ddev, 1); |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 491 | rdev->pm.vblank_sync = true; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 492 | wake_up(&rdev->irq.vblank_queue); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 493 | } |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 494 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 495 | queue_hotplug = true; |
| 496 | DRM_DEBUG("HPD1\n"); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 497 | } |
| 498 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 499 | queue_hotplug = true; |
| 500 | DRM_DEBUG("HPD2\n"); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 501 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 502 | status = rs600_irq_ack(rdev, &r500_disp_int); |
| 503 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame^] | 504 | /* reset gui idle ack. the status bit is broken */ |
| 505 | rdev->irq.gui_idle_acked = false; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 506 | if (queue_hotplug) |
| 507 | queue_work(rdev->wq, &rdev->hotplug_work); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 508 | if (rdev->msi_enabled) { |
| 509 | switch (rdev->family) { |
| 510 | case CHIP_RS600: |
| 511 | case CHIP_RS690: |
| 512 | case CHIP_RS740: |
| 513 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
| 514 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
| 515 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
| 516 | break; |
| 517 | default: |
| 518 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
| 519 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
| 520 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
| 521 | break; |
| 522 | } |
| 523 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 524 | return IRQ_HANDLED; |
| 525 | } |
| 526 | |
| 527 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| 528 | { |
| 529 | if (crtc == 0) |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 530 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 531 | else |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 532 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 533 | } |
| 534 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 535 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
| 536 | { |
| 537 | unsigned i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 538 | |
| 539 | for (i = 0; i < rdev->usec_timeout; i++) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 540 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 541 | return 0; |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 542 | udelay(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 543 | } |
| 544 | return -1; |
| 545 | } |
| 546 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 547 | void rs600_gpu_init(struct radeon_device *rdev) |
| 548 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 549 | r420_pipes_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 550 | /* Wait for mc idle */ |
| 551 | if (rs600_mc_wait_for_idle(rdev)) |
| 552 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 553 | } |
| 554 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 555 | void rs600_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 556 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 557 | u64 base; |
| 558 | |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 559 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| 560 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 561 | rdev->mc.vram_is_ddr = true; |
| 562 | rdev->mc.vram_width = 128; |
Alex Deucher | 722f294 | 2009-12-03 16:18:19 -0500 | [diff] [blame] | 563 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
| 564 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 565 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 566 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
| 567 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
| 568 | base = G_000004_MC_FB_START(base) << 16; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 569 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 570 | radeon_vram_location(rdev, &rdev->mc, base); |
| 571 | radeon_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 572 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 573 | } |
| 574 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 575 | void rs600_bandwidth_update(struct radeon_device *rdev) |
| 576 | { |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 577 | struct drm_display_mode *mode0 = NULL; |
| 578 | struct drm_display_mode *mode1 = NULL; |
| 579 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
| 580 | /* FIXME: implement full support */ |
| 581 | |
| 582 | radeon_update_display_priority(rdev); |
| 583 | |
| 584 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 585 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
| 586 | if (rdev->mode_info.crtcs[1]->base.enabled) |
| 587 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
| 588 | |
| 589 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
| 590 | |
| 591 | if (rdev->disp_priority == 2) { |
| 592 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
| 593 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
| 594 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
| 595 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
| 596 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
| 597 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
| 598 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
| 599 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
| 600 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 601 | } |
| 602 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 603 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| 604 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 605 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| 606 | S_000070_MC_IND_CITF_ARB0(1)); |
| 607 | return RREG32(R_000074_MC_IND_DATA); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 608 | } |
| 609 | |
| 610 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 611 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 612 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| 613 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
| 614 | WREG32(R_000074_MC_IND_DATA, v); |
| 615 | } |
| 616 | |
| 617 | void rs600_debugfs(struct radeon_device *rdev) |
| 618 | { |
| 619 | if (r100_debugfs_rbbm_init(rdev)) |
| 620 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 621 | } |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 622 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 623 | void rs600_set_safe_registers(struct radeon_device *rdev) |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 624 | { |
| 625 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
| 626 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 627 | } |
| 628 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 629 | static void rs600_mc_program(struct radeon_device *rdev) |
| 630 | { |
| 631 | struct rv515_mc_save save; |
| 632 | |
| 633 | /* Stops all mc clients */ |
| 634 | rv515_mc_stop(rdev, &save); |
| 635 | |
| 636 | /* Wait for mc idle */ |
| 637 | if (rs600_mc_wait_for_idle(rdev)) |
| 638 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| 639 | |
| 640 | /* FIXME: What does AGP means for such chipset ? */ |
| 641 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
| 642 | WREG32_MC(R_000006_AGP_BASE, 0); |
| 643 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
| 644 | /* Program MC */ |
| 645 | WREG32_MC(R_000004_MC_FB_LOCATION, |
| 646 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 647 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 648 | WREG32(R_000134_HDP_FB_LOCATION, |
| 649 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| 650 | |
| 651 | rv515_mc_resume(rdev, &save); |
| 652 | } |
| 653 | |
| 654 | static int rs600_startup(struct radeon_device *rdev) |
| 655 | { |
| 656 | int r; |
| 657 | |
| 658 | rs600_mc_program(rdev); |
| 659 | /* Resume clock */ |
| 660 | rv515_clock_startup(rdev); |
| 661 | /* Initialize GPU configuration (# pipes, ...) */ |
| 662 | rs600_gpu_init(rdev); |
| 663 | /* Initialize GART (initialize after TTM so we can allocate |
| 664 | * memory through TTM but finalize after TTM) */ |
| 665 | r = rs600_gart_enable(rdev); |
| 666 | if (r) |
| 667 | return r; |
| 668 | /* Enable IRQ */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 669 | rs600_irq_set(rdev); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 670 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 671 | /* 1M ring buffer */ |
| 672 | r = r100_cp_init(rdev, 1024 * 1024); |
| 673 | if (r) { |
| 674 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| 675 | return r; |
| 676 | } |
| 677 | r = r100_wb_init(rdev); |
| 678 | if (r) |
| 679 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| 680 | r = r100_ib_init(rdev); |
| 681 | if (r) { |
| 682 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| 683 | return r; |
| 684 | } |
| 685 | return 0; |
| 686 | } |
| 687 | |
| 688 | int rs600_resume(struct radeon_device *rdev) |
| 689 | { |
| 690 | /* Make sur GART are not working */ |
| 691 | rs600_gart_disable(rdev); |
| 692 | /* Resume clock before doing reset */ |
| 693 | rv515_clock_startup(rdev); |
| 694 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 695 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 696 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 697 | RREG32(R_000E40_RBBM_STATUS), |
| 698 | RREG32(R_0007C0_CP_STAT)); |
| 699 | } |
| 700 | /* post */ |
| 701 | atom_asic_init(rdev->mode_info.atom_context); |
| 702 | /* Resume clock after posting */ |
| 703 | rv515_clock_startup(rdev); |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 704 | /* Initialize surface registers */ |
| 705 | radeon_surface_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 706 | return rs600_startup(rdev); |
| 707 | } |
| 708 | |
| 709 | int rs600_suspend(struct radeon_device *rdev) |
| 710 | { |
| 711 | r100_cp_disable(rdev); |
| 712 | r100_wb_disable(rdev); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 713 | rs600_irq_disable(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 714 | rs600_gart_disable(rdev); |
| 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | void rs600_fini(struct radeon_device *rdev) |
| 719 | { |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 720 | radeon_pm_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 721 | r100_cp_fini(rdev); |
| 722 | r100_wb_fini(rdev); |
| 723 | r100_ib_fini(rdev); |
| 724 | radeon_gem_fini(rdev); |
| 725 | rs600_gart_fini(rdev); |
| 726 | radeon_irq_kms_fini(rdev); |
| 727 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 728 | radeon_bo_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 729 | radeon_atombios_fini(rdev); |
| 730 | kfree(rdev->bios); |
| 731 | rdev->bios = NULL; |
| 732 | } |
| 733 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 734 | int rs600_init(struct radeon_device *rdev) |
| 735 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 736 | int r; |
| 737 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 738 | /* Disable VGA */ |
| 739 | rv515_vga_render_disable(rdev); |
| 740 | /* Initialize scratch registers */ |
| 741 | radeon_scratch_init(rdev); |
| 742 | /* Initialize surface registers */ |
| 743 | radeon_surface_init(rdev); |
| 744 | /* BIOS */ |
| 745 | if (!radeon_get_bios(rdev)) { |
| 746 | if (ASIC_IS_AVIVO(rdev)) |
| 747 | return -EINVAL; |
| 748 | } |
| 749 | if (rdev->is_atom_bios) { |
| 750 | r = radeon_atombios_init(rdev); |
| 751 | if (r) |
| 752 | return r; |
| 753 | } else { |
| 754 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
| 755 | return -EINVAL; |
| 756 | } |
| 757 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 758 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 759 | dev_warn(rdev->dev, |
| 760 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 761 | RREG32(R_000E40_RBBM_STATUS), |
| 762 | RREG32(R_0007C0_CP_STAT)); |
| 763 | } |
| 764 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 765 | if (radeon_boot_test_post_card(rdev) == false) |
| 766 | return -EINVAL; |
| 767 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 768 | /* Initialize clocks */ |
| 769 | radeon_get_clock_info(rdev->ddev); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 770 | /* Initialize power management */ |
| 771 | radeon_pm_init(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 772 | /* initialize memory controller */ |
| 773 | rs600_mc_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 774 | rs600_debugfs(rdev); |
| 775 | /* Fence driver */ |
| 776 | r = radeon_fence_driver_init(rdev); |
| 777 | if (r) |
| 778 | return r; |
| 779 | r = radeon_irq_kms_init(rdev); |
| 780 | if (r) |
| 781 | return r; |
| 782 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 783 | r = radeon_bo_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 784 | if (r) |
| 785 | return r; |
| 786 | r = rs600_gart_init(rdev); |
| 787 | if (r) |
| 788 | return r; |
| 789 | rs600_set_safe_registers(rdev); |
| 790 | rdev->accel_working = true; |
| 791 | r = rs600_startup(rdev); |
| 792 | if (r) { |
| 793 | /* Somethings want wront with the accel init stop accel */ |
| 794 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 795 | r100_cp_fini(rdev); |
| 796 | r100_wb_fini(rdev); |
| 797 | r100_ib_fini(rdev); |
| 798 | rs600_gart_fini(rdev); |
| 799 | radeon_irq_kms_fini(rdev); |
| 800 | rdev->accel_working = false; |
| 801 | } |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 802 | return 0; |
| 803 | } |