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gerrit-public.fairphone.software / kernel / msm-4.9 / 20b80942ef4e3156a1c4aa5628d1bcb3479812da / . / arch / arm / boot / dts / dra7.dtsi
blob: 98ff6553edbc0c91b64ab85de695d54ed5b56158 [file] [log] [blame]
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame^]23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
44 };
45 cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a15";
48 reg = <1>;
49 };
50 };
51
52 timer {
53 compatible = "arm,armv7-timer";
54 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
56 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
57 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
58 };
59
60 gic: interrupt-controller@48211000 {
61 compatible = "arm,cortex-a15-gic";
62 interrupt-controller;
63 #interrupt-cells = <3>;
64 reg = <0x48211000 0x1000>,
65 <0x48212000 0x1000>,
66 <0x48214000 0x2000>,
67 <0x48216000 0x2000>;
68 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
69 };
70
71 /*
72 * The soc node represents the soc top level view. It is uses for IPs
73 * that are not memory mapped in the MPU view or for the MPU itself.
74 */
75 soc {
76 compatible = "ti,omap-infra";
77 mpu {
78 compatible = "ti,omap5-mpu";
79 ti,hwmods = "mpu";
80 };
81 };
82
83 /*
84 * XXX: Use a flat representation of the SOC interconnect.
85 * The real OMAP interconnect network is quite complex.
86 * Since that will not bring real advantage to represent that in DT for
87 * the moment, just use a fake OCP bus entry to represent the whole bus
88 * hierarchy.
89 */
90 ocp {
91 compatible = "ti,omap4-l3-noc", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95 ti,hwmods = "l3_main_1", "l3_main_2";
96 reg = <0x44000000 0x2000>,
97 <0x44800000 0x3000>;
98 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
100
101 counter32k: counter@4ae04000 {
102 compatible = "ti,omap-counter32k";
103 reg = <0x4ae04000 0x40>;
104 ti,hwmods = "counter_32k";
105 };
106
107 dra7_pmx_core: pinmux@4a003400 {
108 compatible = "pinctrl-single";
109 reg = <0x4a003400 0x0464>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 pinctrl-single,register-width = <32>;
113 pinctrl-single,function-mask = <0x3fffffff>;
114 };
115
116 sdma: dma-controller@4a056000 {
117 compatible = "ti,omap4430-sdma";
118 reg = <0x4a056000 0x1000>;
119 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
123 #dma-cells = <1>;
124 #dma-channels = <32>;
125 #dma-requests = <127>;
126 };
127
128 gpio1: gpio@4ae10000 {
129 compatible = "ti,omap4-gpio";
130 reg = <0x4ae10000 0x200>;
131 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
132 ti,hwmods = "gpio1";
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
137 };
138
139 gpio2: gpio@48055000 {
140 compatible = "ti,omap4-gpio";
141 reg = <0x48055000 0x200>;
142 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
143 ti,hwmods = "gpio2";
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149
150 gpio3: gpio@48057000 {
151 compatible = "ti,omap4-gpio";
152 reg = <0x48057000 0x200>;
153 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
154 ti,hwmods = "gpio3";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <1>;
159 };
160
161 gpio4: gpio@48059000 {
162 compatible = "ti,omap4-gpio";
163 reg = <0x48059000 0x200>;
164 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
165 ti,hwmods = "gpio4";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
170 };
171
172 gpio5: gpio@4805b000 {
173 compatible = "ti,omap4-gpio";
174 reg = <0x4805b000 0x200>;
175 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
176 ti,hwmods = "gpio5";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 };
182
183 gpio6: gpio@4805d000 {
184 compatible = "ti,omap4-gpio";
185 reg = <0x4805d000 0x200>;
186 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
187 ti,hwmods = "gpio6";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <1>;
192 };
193
194 gpio7: gpio@48051000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x48051000 0x200>;
197 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
198 ti,hwmods = "gpio7";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <1>;
203 };
204
205 gpio8: gpio@48053000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x48053000 0x200>;
208 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
209 ti,hwmods = "gpio8";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <1>;
214 };
215
216 uart1: serial@4806a000 {
217 compatible = "ti,omap4-uart";
218 reg = <0x4806a000 0x100>;
219 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
220 ti,hwmods = "uart1";
221 clock-frequency = <48000000>;
222 status = "disabled";
223 };
224
225 uart2: serial@4806c000 {
226 compatible = "ti,omap4-uart";
227 reg = <0x4806c000 0x100>;
228 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
229 ti,hwmods = "uart2";
230 clock-frequency = <48000000>;
231 status = "disabled";
232 };
233
234 uart3: serial@48020000 {
235 compatible = "ti,omap4-uart";
236 reg = <0x48020000 0x100>;
237 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
238 ti,hwmods = "uart3";
239 clock-frequency = <48000000>;
240 status = "disabled";
241 };
242
243 uart4: serial@4806e000 {
244 compatible = "ti,omap4-uart";
245 reg = <0x4806e000 0x100>;
246 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
247 ti,hwmods = "uart4";
248 clock-frequency = <48000000>;
249 status = "disabled";
250 };
251
252 uart5: serial@48066000 {
253 compatible = "ti,omap4-uart";
254 reg = <0x48066000 0x100>;
255 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
256 ti,hwmods = "uart5";
257 clock-frequency = <48000000>;
258 status = "disabled";
259 };
260
261 uart6: serial@48068000 {
262 compatible = "ti,omap4-uart";
263 reg = <0x48068000 0x100>;
264 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
265 ti,hwmods = "uart6";
266 clock-frequency = <48000000>;
267 status = "disabled";
268 };
269
270 uart7: serial@48420000 {
271 compatible = "ti,omap4-uart";
272 reg = <0x48420000 0x100>;
273 ti,hwmods = "uart7";
274 clock-frequency = <48000000>;
275 status = "disabled";
276 };
277
278 uart8: serial@48422000 {
279 compatible = "ti,omap4-uart";
280 reg = <0x48422000 0x100>;
281 ti,hwmods = "uart8";
282 clock-frequency = <48000000>;
283 status = "disabled";
284 };
285
286 uart9: serial@48424000 {
287 compatible = "ti,omap4-uart";
288 reg = <0x48424000 0x100>;
289 ti,hwmods = "uart9";
290 clock-frequency = <48000000>;
291 status = "disabled";
292 };
293
294 uart10: serial@4ae2b000 {
295 compatible = "ti,omap4-uart";
296 reg = <0x4ae2b000 0x100>;
297 ti,hwmods = "uart10";
298 clock-frequency = <48000000>;
299 status = "disabled";
300 };
301
302 timer1: timer@4ae18000 {
303 compatible = "ti,omap5430-timer";
304 reg = <0x4ae18000 0x80>;
305 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
306 ti,hwmods = "timer1";
307 ti,timer-alwon;
308 };
309
310 timer2: timer@48032000 {
311 compatible = "ti,omap5430-timer";
312 reg = <0x48032000 0x80>;
313 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
314 ti,hwmods = "timer2";
315 };
316
317 timer3: timer@48034000 {
318 compatible = "ti,omap5430-timer";
319 reg = <0x48034000 0x80>;
320 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
321 ti,hwmods = "timer3";
322 };
323
324 timer4: timer@48036000 {
325 compatible = "ti,omap5430-timer";
326 reg = <0x48036000 0x80>;
327 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
328 ti,hwmods = "timer4";
329 };
330
331 timer5: timer@48820000 {
332 compatible = "ti,omap5430-timer";
333 reg = <0x48820000 0x80>;
334 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "timer5";
336 ti,timer-dsp;
337 };
338
339 timer6: timer@48822000 {
340 compatible = "ti,omap5430-timer";
341 reg = <0x48822000 0x80>;
342 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "timer6";
344 ti,timer-dsp;
345 ti,timer-pwm;
346 };
347
348 timer7: timer@48824000 {
349 compatible = "ti,omap5430-timer";
350 reg = <0x48824000 0x80>;
351 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
352 ti,hwmods = "timer7";
353 ti,timer-dsp;
354 };
355
356 timer8: timer@48826000 {
357 compatible = "ti,omap5430-timer";
358 reg = <0x48826000 0x80>;
359 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
360 ti,hwmods = "timer8";
361 ti,timer-dsp;
362 ti,timer-pwm;
363 };
364
365 timer9: timer@4803e000 {
366 compatible = "ti,omap5430-timer";
367 reg = <0x4803e000 0x80>;
368 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "timer9";
370 };
371
372 timer10: timer@48086000 {
373 compatible = "ti,omap5430-timer";
374 reg = <0x48086000 0x80>;
375 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
376 ti,hwmods = "timer10";
377 };
378
379 timer11: timer@48088000 {
380 compatible = "ti,omap5430-timer";
381 reg = <0x48088000 0x80>;
382 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
383 ti,hwmods = "timer11";
384 ti,timer-pwm;
385 };
386
387 timer13: timer@48828000 {
388 compatible = "ti,omap5430-timer";
389 reg = <0x48828000 0x80>;
390 ti,hwmods = "timer13";
391 status = "disabled";
392 };
393
394 timer14: timer@4882a000 {
395 compatible = "ti,omap5430-timer";
396 reg = <0x4882a000 0x80>;
397 ti,hwmods = "timer14";
398 status = "disabled";
399 };
400
401 timer15: timer@4882c000 {
402 compatible = "ti,omap5430-timer";
403 reg = <0x4882c000 0x80>;
404 ti,hwmods = "timer15";
405 status = "disabled";
406 };
407
408 timer16: timer@4882e000 {
409 compatible = "ti,omap5430-timer";
410 reg = <0x4882e000 0x80>;
411 ti,hwmods = "timer16";
412 status = "disabled";
413 };
414
415 wdt2: wdt@4ae14000 {
416 compatible = "ti,omap4-wdt";
417 reg = <0x4ae14000 0x80>;
418 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
419 ti,hwmods = "wd_timer2";
420 };
421
422 i2c1: i2c@48070000 {
423 compatible = "ti,omap4-i2c";
424 reg = <0x48070000 0x100>;
425 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 ti,hwmods = "i2c1";
429 status = "disabled";
430 };
431
432 i2c2: i2c@48072000 {
433 compatible = "ti,omap4-i2c";
434 reg = <0x48072000 0x100>;
435 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 ti,hwmods = "i2c2";
439 status = "disabled";
440 };
441
442 i2c3: i2c@48060000 {
443 compatible = "ti,omap4-i2c";
444 reg = <0x48060000 0x100>;
445 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 ti,hwmods = "i2c3";
449 status = "disabled";
450 };
451
452 i2c4: i2c@4807a000 {
453 compatible = "ti,omap4-i2c";
454 reg = <0x4807a000 0x100>;
455 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 ti,hwmods = "i2c4";
459 status = "disabled";
460 };
461
462 i2c5: i2c@4807c000 {
463 compatible = "ti,omap4-i2c";
464 reg = <0x4807c000 0x100>;
465 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 ti,hwmods = "i2c5";
469 status = "disabled";
470 };
471
472 mmc1: mmc@4809c000 {
473 compatible = "ti,omap4-hsmmc";
474 reg = <0x4809c000 0x400>;
475 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "mmc1";
477 ti,dual-volt;
478 ti,needs-special-reset;
479 dmas = <&sdma 61>, <&sdma 62>;
480 dma-names = "tx", "rx";
481 status = "disabled";
482 };
483
484 mmc2: mmc@480b4000 {
485 compatible = "ti,omap4-hsmmc";
486 reg = <0x480b4000 0x400>;
487 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
488 ti,hwmods = "mmc2";
489 ti,needs-special-reset;
490 dmas = <&sdma 47>, <&sdma 48>;
491 dma-names = "tx", "rx";
492 status = "disabled";
493 };
494
495 mmc3: mmc@480ad000 {
496 compatible = "ti,omap4-hsmmc";
497 reg = <0x480ad000 0x400>;
498 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
499 ti,hwmods = "mmc3";
500 ti,needs-special-reset;
501 dmas = <&sdma 77>, <&sdma 78>;
502 dma-names = "tx", "rx";
503 status = "disabled";
504 };
505
506 mmc4: mmc@480d1000 {
507 compatible = "ti,omap4-hsmmc";
508 reg = <0x480d1000 0x400>;
509 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
510 ti,hwmods = "mmc4";
511 ti,needs-special-reset;
512 dmas = <&sdma 57>, <&sdma 58>;
513 dma-names = "tx", "rx";
514 status = "disabled";
515 };
516
517 mcspi1: spi@48098000 {
518 compatible = "ti,omap4-mcspi";
519 reg = <0x48098000 0x200>;
520 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 ti,hwmods = "mcspi1";
524 ti,spi-num-cs = <4>;
525 dmas = <&sdma 35>,
526 <&sdma 36>,
527 <&sdma 37>,
528 <&sdma 38>,
529 <&sdma 39>,
530 <&sdma 40>,
531 <&sdma 41>,
532 <&sdma 42>;
533 dma-names = "tx0", "rx0", "tx1", "rx1",
534 "tx2", "rx2", "tx3", "rx3";
535 status = "disabled";
536 };
537
538 mcspi2: spi@4809a000 {
539 compatible = "ti,omap4-mcspi";
540 reg = <0x4809a000 0x200>;
541 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 ti,hwmods = "mcspi2";
545 ti,spi-num-cs = <2>;
546 dmas = <&sdma 43>,
547 <&sdma 44>,
548 <&sdma 45>,
549 <&sdma 46>;
550 dma-names = "tx0", "rx0", "tx1", "rx1";
551 status = "disabled";
552 };
553
554 mcspi3: spi@480b8000 {
555 compatible = "ti,omap4-mcspi";
556 reg = <0x480b8000 0x200>;
557 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 ti,hwmods = "mcspi3";
561 ti,spi-num-cs = <2>;
562 dmas = <&sdma 15>, <&sdma 16>;
563 dma-names = "tx0", "rx0";
564 status = "disabled";
565 };
566
567 mcspi4: spi@480ba000 {
568 compatible = "ti,omap4-mcspi";
569 reg = <0x480ba000 0x200>;
570 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
571 #address-cells = <1>;
572 #size-cells = <0>;
573 ti,hwmods = "mcspi4";
574 ti,spi-num-cs = <1>;
575 dmas = <&sdma 70>, <&sdma 71>;
576 dma-names = "tx0", "rx0";
577 status = "disabled";
578 };
579 };
580};