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Feng Tang7063c0d2010-12-24 13:59:11 +08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Special handling for DW core on Intel MID platform
Feng Tang7063c0d2010-12-24 13:59:11 +08003 *
Andy Shevchenko197e96b2014-09-12 15:12:01 +03004 * Copyright (c) 2009, 2014 Intel Corporation.
Feng Tang7063c0d2010-12-24 13:59:11 +08005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tang7063c0d2010-12-24 13:59:11 +080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/dmaengine.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/spi/spi.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053021#include <linux/types.h>
Grant Likely568a60e2011-02-28 12:47:12 -070022
Grant Likelyca632f52011-06-06 01:16:30 -060023#include "spi-dw.h"
Feng Tang7063c0d2010-12-24 13:59:11 +080024
25#ifdef CONFIG_SPI_DW_MID_DMA
Feng Tang7063c0d2010-12-24 13:59:11 +080026#include <linux/pci.h>
Andy Shevchenkod744f822015-03-09 16:48:50 +020027#include <linux/platform_data/dma-dw.h>
Feng Tang7063c0d2010-12-24 13:59:11 +080028
Andy Shevchenko30c8eb52014-10-28 18:25:02 +020029#define RX_BUSY 0
30#define TX_BUSY 1
31
Andy Shevchenkod744f822015-03-09 16:48:50 +020032static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
33static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
Feng Tang7063c0d2010-12-24 13:59:11 +080034
35static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
36{
Andy Shevchenkod744f822015-03-09 16:48:50 +020037 struct dw_dma_slave *s = param;
Feng Tang7063c0d2010-12-24 13:59:11 +080038
Andy Shevchenkod744f822015-03-09 16:48:50 +020039 if (s->dma_dev != chan->device->dev)
40 return false;
41
42 chan->private = s;
43 return true;
Feng Tang7063c0d2010-12-24 13:59:11 +080044}
45
46static int mid_spi_dma_init(struct dw_spi *dws)
47{
Andy Shevchenkob89e9c82014-09-12 15:12:00 +030048 struct pci_dev *dma_dev;
Andy Shevchenkod744f822015-03-09 16:48:50 +020049 struct dw_dma_slave *tx = dws->dma_tx;
50 struct dw_dma_slave *rx = dws->dma_rx;
Feng Tang7063c0d2010-12-24 13:59:11 +080051 dma_cap_mask_t mask;
52
53 /*
54 * Get pci device for DMA controller, currently it could only
Andy Shevchenkoea092452014-09-12 15:11:59 +030055 * be the DMA controller of Medfield
Feng Tang7063c0d2010-12-24 13:59:11 +080056 */
Andy Shevchenkob89e9c82014-09-12 15:12:00 +030057 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
58 if (!dma_dev)
59 return -ENODEV;
60
Feng Tang7063c0d2010-12-24 13:59:11 +080061 dma_cap_zero(mask);
62 dma_cap_set(DMA_SLAVE, mask);
63
64 /* 1. Init rx channel */
Andy Shevchenkod744f822015-03-09 16:48:50 +020065 rx->dma_dev = &dma_dev->dev;
66 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
Feng Tang7063c0d2010-12-24 13:59:11 +080067 if (!dws->rxchan)
68 goto err_exit;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +020069 dws->master->dma_rx = dws->rxchan;
Feng Tang7063c0d2010-12-24 13:59:11 +080070
71 /* 2. Init tx channel */
Andy Shevchenkod744f822015-03-09 16:48:50 +020072 tx->dma_dev = &dma_dev->dev;
73 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
Feng Tang7063c0d2010-12-24 13:59:11 +080074 if (!dws->txchan)
75 goto free_rxchan;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +020076 dws->master->dma_tx = dws->txchan;
Feng Tang7063c0d2010-12-24 13:59:11 +080077
78 dws->dma_inited = 1;
79 return 0;
80
81free_rxchan:
82 dma_release_channel(dws->rxchan);
83err_exit:
Andy Shevchenkob89e9c82014-09-12 15:12:00 +030084 return -EBUSY;
Feng Tang7063c0d2010-12-24 13:59:11 +080085}
86
87static void mid_spi_dma_exit(struct dw_spi *dws)
88{
Andy Shevchenkofb578622014-09-12 15:11:58 +030089 if (!dws->dma_inited)
90 return;
Andy Shevchenko8e45ef62014-09-18 20:08:53 +030091
92 dmaengine_terminate_all(dws->txchan);
Feng Tang7063c0d2010-12-24 13:59:11 +080093 dma_release_channel(dws->txchan);
Andy Shevchenko8e45ef62014-09-18 20:08:53 +030094
95 dmaengine_terminate_all(dws->rxchan);
Feng Tang7063c0d2010-12-24 13:59:11 +080096 dma_release_channel(dws->rxchan);
97}
98
Andy Shevchenkof051fc82015-03-09 16:48:47 +020099static irqreturn_t dma_transfer(struct dw_spi *dws)
100{
Thor Thayerdd114442015-03-12 14:19:31 -0500101 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
Andy Shevchenkof051fc82015-03-09 16:48:47 +0200102
103 if (!irq_status)
104 return IRQ_NONE;
105
Thor Thayerdd114442015-03-12 14:19:31 -0500106 dw_readl(dws, DW_SPI_ICR);
Andy Shevchenkof051fc82015-03-09 16:48:47 +0200107 spi_reset_chip(dws);
108
109 dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
110 dws->master->cur_msg->status = -EIO;
111 spi_finalize_current_transfer(dws->master);
112 return IRQ_HANDLED;
113}
114
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200115static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
116 struct spi_transfer *xfer)
117{
118 struct dw_spi *dws = spi_master_get_devdata(master);
119
120 if (!dws->dma_inited)
121 return false;
122
123 return xfer->len > dws->fifo_len;
124}
125
Andy Shevchenkoe31abce2015-03-09 16:48:45 +0200126static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
127 if (dma_width == 1)
128 return DMA_SLAVE_BUSWIDTH_1_BYTE;
129 else if (dma_width == 2)
130 return DMA_SLAVE_BUSWIDTH_2_BYTES;
131
132 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
133}
134
Feng Tang7063c0d2010-12-24 13:59:11 +0800135/*
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200136 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
137 * channel will clear a corresponding bit.
Feng Tang7063c0d2010-12-24 13:59:11 +0800138 */
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200139static void dw_spi_dma_tx_done(void *arg)
Feng Tang7063c0d2010-12-24 13:59:11 +0800140{
141 struct dw_spi *dws = arg;
142
Andy Shevchenko854d2f22015-03-06 14:42:01 +0200143 clear_bit(TX_BUSY, &dws->dma_chan_busy);
144 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
Feng Tang7063c0d2010-12-24 13:59:11 +0800145 return;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200146 spi_finalize_current_transfer(dws->master);
Feng Tang7063c0d2010-12-24 13:59:11 +0800147}
148
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200149static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
150 struct spi_transfer *xfer)
Feng Tang7063c0d2010-12-24 13:59:11 +0800151{
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200152 struct dma_slave_config txconf;
153 struct dma_async_tx_descriptor *txdesc;
Feng Tang7063c0d2010-12-24 13:59:11 +0800154
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200155 if (!xfer->tx_buf)
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200156 return NULL;
157
Vinod Koula485df42011-10-14 10:47:38 +0530158 txconf.direction = DMA_MEM_TO_DEV;
Feng Tang7063c0d2010-12-24 13:59:11 +0800159 txconf.dst_addr = dws->dma_addr;
Andy Shevchenkod744f822015-03-09 16:48:50 +0200160 txconf.dst_maxburst = 16;
Feng Tang7063c0d2010-12-24 13:59:11 +0800161 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Andy Shevchenkoe31abce2015-03-09 16:48:45 +0200162 txconf.dst_addr_width = convert_dma_width(dws->dma_width);
Viresh Kumar258aea72012-02-01 16:12:19 +0530163 txconf.device_fc = false;
Feng Tang7063c0d2010-12-24 13:59:11 +0800164
Andy Shevchenko2a285292014-10-02 16:31:08 +0300165 dmaengine_slave_config(dws->txchan, &txconf);
Feng Tang7063c0d2010-12-24 13:59:11 +0800166
Andy Shevchenko2a285292014-10-02 16:31:08 +0300167 txdesc = dmaengine_prep_slave_sg(dws->txchan,
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200168 xfer->tx_sg.sgl,
169 xfer->tx_sg.nents,
Vinod Koula485df42011-10-14 10:47:38 +0530170 DMA_MEM_TO_DEV,
Andy Shevchenkof7477c22014-10-02 16:31:09 +0300171 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Andy Shevchenkoc9dafb22015-03-02 20:15:58 +0200172 if (!txdesc)
173 return NULL;
174
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200175 txdesc->callback = dw_spi_dma_tx_done;
Feng Tang7063c0d2010-12-24 13:59:11 +0800176 txdesc->callback_param = dws;
177
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200178 return txdesc;
179}
180
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200181/*
182 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
183 * channel will clear a corresponding bit.
184 */
185static void dw_spi_dma_rx_done(void *arg)
186{
187 struct dw_spi *dws = arg;
188
Andy Shevchenko854d2f22015-03-06 14:42:01 +0200189 clear_bit(RX_BUSY, &dws->dma_chan_busy);
190 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200191 return;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200192 spi_finalize_current_transfer(dws->master);
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200193}
194
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200195static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
196 struct spi_transfer *xfer)
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200197{
198 struct dma_slave_config rxconf;
199 struct dma_async_tx_descriptor *rxdesc;
200
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200201 if (!xfer->rx_buf)
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200202 return NULL;
203
Vinod Koula485df42011-10-14 10:47:38 +0530204 rxconf.direction = DMA_DEV_TO_MEM;
Feng Tang7063c0d2010-12-24 13:59:11 +0800205 rxconf.src_addr = dws->dma_addr;
Andy Shevchenkod744f822015-03-09 16:48:50 +0200206 rxconf.src_maxburst = 16;
Feng Tang7063c0d2010-12-24 13:59:11 +0800207 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Andy Shevchenkoe31abce2015-03-09 16:48:45 +0200208 rxconf.src_addr_width = convert_dma_width(dws->dma_width);
Viresh Kumar258aea72012-02-01 16:12:19 +0530209 rxconf.device_fc = false;
Feng Tang7063c0d2010-12-24 13:59:11 +0800210
Andy Shevchenko2a285292014-10-02 16:31:08 +0300211 dmaengine_slave_config(dws->rxchan, &rxconf);
Feng Tang7063c0d2010-12-24 13:59:11 +0800212
Andy Shevchenko2a285292014-10-02 16:31:08 +0300213 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200214 xfer->rx_sg.sgl,
215 xfer->rx_sg.nents,
Vinod Koula485df42011-10-14 10:47:38 +0530216 DMA_DEV_TO_MEM,
Andy Shevchenkof7477c22014-10-02 16:31:09 +0300217 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Andy Shevchenkoc9dafb22015-03-02 20:15:58 +0200218 if (!rxdesc)
219 return NULL;
220
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200221 rxdesc->callback = dw_spi_dma_rx_done;
Feng Tang7063c0d2010-12-24 13:59:11 +0800222 rxdesc->callback_param = dws;
223
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200224 return rxdesc;
225}
226
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200227static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200228{
229 u16 dma_ctrl = 0;
230
Thor Thayerdd114442015-03-12 14:19:31 -0500231 dw_writel(dws, DW_SPI_DMARDLR, 0xf);
232 dw_writel(dws, DW_SPI_DMATDLR, 0x10);
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200233
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200234 if (xfer->tx_buf)
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200235 dma_ctrl |= SPI_DMA_TDMAE;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200236 if (xfer->rx_buf)
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200237 dma_ctrl |= SPI_DMA_RDMAE;
Thor Thayerdd114442015-03-12 14:19:31 -0500238 dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200239
Andy Shevchenkof051fc82015-03-09 16:48:47 +0200240 /* Set the interrupt mask */
241 spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
242
243 dws->transfer_handler = dma_transfer;
244
Andy Shevchenko9f145382015-03-09 16:48:46 +0200245 return 0;
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200246}
247
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200248static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200249{
250 struct dma_async_tx_descriptor *txdesc, *rxdesc;
251
Andy Shevchenko9f145382015-03-09 16:48:46 +0200252 /* Prepare the TX dma transfer */
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200253 txdesc = dw_spi_dma_prepare_tx(dws, xfer);
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200254
Andy Shevchenko9f145382015-03-09 16:48:46 +0200255 /* Prepare the RX dma transfer */
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200256 rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
Andy Shevchenkoa5c2db92014-10-28 18:25:01 +0200257
Feng Tang7063c0d2010-12-24 13:59:11 +0800258 /* rx must be started before tx due to spi instinct */
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200259 if (rxdesc) {
260 set_bit(RX_BUSY, &dws->dma_chan_busy);
261 dmaengine_submit(rxdesc);
262 dma_async_issue_pending(dws->rxchan);
263 }
Andy Shevchenkof7477c22014-10-02 16:31:09 +0300264
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200265 if (txdesc) {
266 set_bit(TX_BUSY, &dws->dma_chan_busy);
267 dmaengine_submit(txdesc);
268 dma_async_issue_pending(dws->txchan);
269 }
Andy Shevchenkof7477c22014-10-02 16:31:09 +0300270
Feng Tang7063c0d2010-12-24 13:59:11 +0800271 return 0;
272}
273
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200274static void mid_spi_dma_stop(struct dw_spi *dws)
275{
276 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
277 dmaengine_terminate_all(dws->txchan);
278 clear_bit(TX_BUSY, &dws->dma_chan_busy);
279 }
280 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
281 dmaengine_terminate_all(dws->rxchan);
282 clear_bit(RX_BUSY, &dws->dma_chan_busy);
283 }
284}
285
Feng Tang7063c0d2010-12-24 13:59:11 +0800286static struct dw_spi_dma_ops mid_dma_ops = {
287 .dma_init = mid_spi_dma_init,
288 .dma_exit = mid_spi_dma_exit,
Andy Shevchenko9f145382015-03-09 16:48:46 +0200289 .dma_setup = mid_spi_dma_setup,
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200290 .can_dma = mid_spi_can_dma,
Feng Tang7063c0d2010-12-24 13:59:11 +0800291 .dma_transfer = mid_spi_dma_transfer,
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200292 .dma_stop = mid_spi_dma_stop,
Feng Tang7063c0d2010-12-24 13:59:11 +0800293};
294#endif
295
Andy Shevchenkoea092452014-09-12 15:11:59 +0300296/* Some specific info for SPI0 controller on Intel MID */
Feng Tang7063c0d2010-12-24 13:59:11 +0800297
Andy Shevchenkod9c14742015-01-22 17:59:34 +0200298/* HW info for MRST Clk Control Unit, 32b reg per controller */
Feng Tang7063c0d2010-12-24 13:59:11 +0800299#define MRST_SPI_CLK_BASE 100000000 /* 100m */
Andy Shevchenkod9c14742015-01-22 17:59:34 +0200300#define MRST_CLK_SPI_REG 0xff11d86c
Feng Tang7063c0d2010-12-24 13:59:11 +0800301#define CLK_SPI_BDIV_OFFSET 0
302#define CLK_SPI_BDIV_MASK 0x00000007
303#define CLK_SPI_CDIV_OFFSET 9
304#define CLK_SPI_CDIV_MASK 0x00000e00
305#define CLK_SPI_DISABLE_OFFSET 8
306
307int dw_spi_mid_init(struct dw_spi *dws)
308{
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700309 void __iomem *clk_reg;
310 u32 clk_cdiv;
Feng Tang7063c0d2010-12-24 13:59:11 +0800311
Andy Shevchenkod9c14742015-01-22 17:59:34 +0200312 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
Feng Tang7063c0d2010-12-24 13:59:11 +0800313 if (!clk_reg)
314 return -ENOMEM;
315
Andy Shevchenkod9c14742015-01-22 17:59:34 +0200316 /* Get SPI controller operating freq info */
317 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
318 clk_cdiv &= CLK_SPI_CDIV_MASK;
319 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
Feng Tang7063c0d2010-12-24 13:59:11 +0800320 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
Andy Shevchenkod9c14742015-01-22 17:59:34 +0200321
Feng Tang7063c0d2010-12-24 13:59:11 +0800322 iounmap(clk_reg);
323
Feng Tang7063c0d2010-12-24 13:59:11 +0800324#ifdef CONFIG_SPI_DW_MID_DMA
Andy Shevchenkod744f822015-03-09 16:48:50 +0200325 dws->dma_tx = &mid_dma_tx;
326 dws->dma_rx = &mid_dma_rx;
Feng Tang7063c0d2010-12-24 13:59:11 +0800327 dws->dma_ops = &mid_dma_ops;
328#endif
329 return 0;
330}