Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * hcd_queue.c - DesignWare HS OTG Controller host queuing routines |
| 3 | * |
| 4 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions, and the following disclaimer, |
| 11 | * without modification. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The names of the above-listed copyright holders may not be used |
| 16 | * to endorse or promote products derived from this software without |
| 17 | * specific prior written permission. |
| 18 | * |
| 19 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") as published by the Free Software |
| 21 | * Foundation; either version 2 of the License, or (at your option) any |
| 22 | * later version. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * This file contains the functions to manage Queue Heads and Queue |
| 39 | * Transfer Descriptors for Host mode |
| 40 | */ |
| 41 | #include <linux/kernel.h> |
| 42 | #include <linux/module.h> |
| 43 | #include <linux/spinlock.h> |
| 44 | #include <linux/interrupt.h> |
| 45 | #include <linux/dma-mapping.h> |
| 46 | #include <linux/io.h> |
| 47 | #include <linux/slab.h> |
| 48 | #include <linux/usb.h> |
| 49 | |
| 50 | #include <linux/usb/hcd.h> |
| 51 | #include <linux/usb/ch11.h> |
| 52 | |
| 53 | #include "core.h" |
| 54 | #include "hcd.h" |
| 55 | |
| 56 | /** |
| 57 | * dwc2_qh_init() - Initializes a QH structure |
| 58 | * |
| 59 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 60 | * @qh: The QH to init |
| 61 | * @urb: Holds the information about the device/endpoint needed to initialize |
| 62 | * the QH |
| 63 | */ |
| 64 | #define SCHEDULE_SLOP 10 |
| 65 | static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, |
| 66 | struct dwc2_hcd_urb *urb) |
| 67 | { |
| 68 | int dev_speed, hub_addr, hub_port; |
| 69 | char *speed, *type; |
| 70 | |
| 71 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 72 | |
| 73 | /* Initialize QH */ |
| 74 | qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); |
| 75 | qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; |
| 76 | |
| 77 | qh->data_toggle = DWC2_HC_PID_DATA0; |
| 78 | qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); |
| 79 | INIT_LIST_HEAD(&qh->qtd_list); |
| 80 | INIT_LIST_HEAD(&qh->qh_list_entry); |
| 81 | |
| 82 | /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ |
| 83 | dev_speed = dwc2_host_get_speed(hsotg, urb->priv); |
| 84 | |
| 85 | dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); |
| 86 | |
| 87 | if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && |
| 88 | hub_addr != 0 && hub_addr != 1) { |
| 89 | dev_vdbg(hsotg->dev, |
| 90 | "QH init: EP %d: TT found at hub addr %d, for port %d\n", |
| 91 | dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, |
| 92 | hub_port); |
| 93 | qh->do_split = 1; |
| 94 | } |
| 95 | |
| 96 | if (qh->ep_type == USB_ENDPOINT_XFER_INT || |
| 97 | qh->ep_type == USB_ENDPOINT_XFER_ISOC) { |
| 98 | /* Compute scheduling parameters once and save them */ |
| 99 | u32 hprt, prtspd; |
| 100 | |
| 101 | /* Todo: Account for split transfers in the bus time */ |
| 102 | int bytecount = |
| 103 | dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); |
| 104 | |
| 105 | qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ? |
| 106 | USB_SPEED_HIGH : dev_speed, qh->ep_is_in, |
| 107 | qh->ep_type == USB_ENDPOINT_XFER_ISOC, |
| 108 | bytecount)); |
| 109 | /* Start in a slightly future (micro)frame */ |
| 110 | qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, |
| 111 | SCHEDULE_SLOP); |
| 112 | qh->interval = urb->interval; |
| 113 | #if 0 |
| 114 | /* Increase interrupt polling rate for debugging */ |
| 115 | if (qh->ep_type == USB_ENDPOINT_XFER_INT) |
| 116 | qh->interval = 8; |
| 117 | #endif |
| 118 | hprt = readl(hsotg->regs + HPRT0); |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 119 | prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 120 | if (prtspd == HPRT0_SPD_HIGH_SPEED && |
| 121 | (dev_speed == USB_SPEED_LOW || |
| 122 | dev_speed == USB_SPEED_FULL)) { |
| 123 | qh->interval *= 8; |
| 124 | qh->sched_frame |= 0x7; |
| 125 | qh->start_split_frame = qh->sched_frame; |
| 126 | } |
| 127 | dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); |
| 128 | } |
| 129 | |
| 130 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); |
| 131 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); |
| 132 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", |
| 133 | dwc2_hcd_get_dev_addr(&urb->pipe_info)); |
| 134 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", |
| 135 | dwc2_hcd_get_ep_num(&urb->pipe_info), |
| 136 | dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); |
| 137 | |
| 138 | qh->dev_speed = dev_speed; |
| 139 | |
| 140 | switch (dev_speed) { |
| 141 | case USB_SPEED_LOW: |
| 142 | speed = "low"; |
| 143 | break; |
| 144 | case USB_SPEED_FULL: |
| 145 | speed = "full"; |
| 146 | break; |
| 147 | case USB_SPEED_HIGH: |
| 148 | speed = "high"; |
| 149 | break; |
| 150 | default: |
| 151 | speed = "?"; |
| 152 | break; |
| 153 | } |
| 154 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); |
| 155 | |
| 156 | switch (qh->ep_type) { |
| 157 | case USB_ENDPOINT_XFER_ISOC: |
| 158 | type = "isochronous"; |
| 159 | break; |
| 160 | case USB_ENDPOINT_XFER_INT: |
| 161 | type = "interrupt"; |
| 162 | break; |
| 163 | case USB_ENDPOINT_XFER_CONTROL: |
| 164 | type = "control"; |
| 165 | break; |
| 166 | case USB_ENDPOINT_XFER_BULK: |
| 167 | type = "bulk"; |
| 168 | break; |
| 169 | default: |
| 170 | type = "?"; |
| 171 | break; |
| 172 | } |
| 173 | |
| 174 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); |
| 175 | |
| 176 | if (qh->ep_type == USB_ENDPOINT_XFER_INT) { |
| 177 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", |
| 178 | qh->usecs); |
| 179 | dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", |
| 180 | qh->interval); |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | /** |
| 185 | * dwc2_hcd_qh_create() - Allocates and initializes a QH |
| 186 | * |
| 187 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 188 | * @urb: Holds the information about the device/endpoint needed |
| 189 | * to initialize the QH |
| 190 | * @atomic_alloc: Flag to do atomic allocation if needed |
| 191 | * |
| 192 | * Return: Pointer to the newly allocated QH, or NULL on error |
| 193 | */ |
| 194 | static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, |
| 195 | struct dwc2_hcd_urb *urb, |
| 196 | gfp_t mem_flags) |
| 197 | { |
| 198 | struct dwc2_qh *qh; |
| 199 | |
Paul Zimmerman | b2d6cb5 | 2013-07-13 14:53:51 -0700 | [diff] [blame] | 200 | if (!urb->priv) |
| 201 | return NULL; |
| 202 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 203 | /* Allocate memory */ |
| 204 | qh = kzalloc(sizeof(*qh), mem_flags); |
| 205 | if (!qh) |
| 206 | return NULL; |
| 207 | |
| 208 | dwc2_qh_init(hsotg, qh, urb); |
| 209 | |
| 210 | if (hsotg->core_params->dma_desc_enable > 0 && |
| 211 | dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { |
| 212 | dwc2_hcd_qh_free(hsotg, qh); |
| 213 | return NULL; |
| 214 | } |
| 215 | |
| 216 | return qh; |
| 217 | } |
| 218 | |
| 219 | /** |
| 220 | * dwc2_hcd_qh_free() - Frees the QH |
| 221 | * |
| 222 | * @hsotg: HCD instance |
| 223 | * @qh: The QH to free |
| 224 | * |
| 225 | * QH should already be removed from the list. QTD list should already be empty |
| 226 | * if called from URB Dequeue. |
| 227 | * |
| 228 | * Must NOT be called with interrupt disabled or spinlock held |
| 229 | */ |
| 230 | void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 231 | { |
| 232 | u32 buf_size; |
| 233 | |
| 234 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 235 | dwc2_hcd_qh_free_ddma(hsotg, qh); |
| 236 | } else if (qh->dw_align_buf) { |
| 237 | if (qh->ep_type == USB_ENDPOINT_XFER_ISOC) |
| 238 | buf_size = 4096; |
| 239 | else |
| 240 | buf_size = hsotg->core_params->max_transfer_size; |
| 241 | dma_free_coherent(hsotg->dev, buf_size, qh->dw_align_buf, |
| 242 | qh->dw_align_buf_dma); |
| 243 | } |
| 244 | |
| 245 | kfree(qh); |
| 246 | } |
| 247 | |
| 248 | /** |
| 249 | * dwc2_periodic_channel_available() - Checks that a channel is available for a |
| 250 | * periodic transfer |
| 251 | * |
| 252 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 253 | * |
Masanari Iida | 0dcde508 | 2013-09-13 23:34:36 +0900 | [diff] [blame] | 254 | * Return: 0 if successful, negative error code otherwise |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 255 | */ |
| 256 | static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) |
| 257 | { |
| 258 | /* |
Masanari Iida | 0dcde508 | 2013-09-13 23:34:36 +0900 | [diff] [blame] | 259 | * Currently assuming that there is a dedicated host channel for |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 260 | * each periodic transaction plus at least one host channel for |
| 261 | * non-periodic transactions |
| 262 | */ |
| 263 | int status; |
| 264 | int num_channels; |
| 265 | |
| 266 | num_channels = hsotg->core_params->host_channels; |
| 267 | if (hsotg->periodic_channels + hsotg->non_periodic_channels < |
| 268 | num_channels |
| 269 | && hsotg->periodic_channels < num_channels - 1) { |
| 270 | status = 0; |
| 271 | } else { |
| 272 | dev_dbg(hsotg->dev, |
| 273 | "%s: Total channels: %d, Periodic: %d, " |
| 274 | "Non-periodic: %d\n", __func__, num_channels, |
| 275 | hsotg->periodic_channels, hsotg->non_periodic_channels); |
| 276 | status = -ENOSPC; |
| 277 | } |
| 278 | |
| 279 | return status; |
| 280 | } |
| 281 | |
| 282 | /** |
| 283 | * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth |
| 284 | * for the specified QH in the periodic schedule |
| 285 | * |
| 286 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 287 | * @qh: QH containing periodic bandwidth required |
| 288 | * |
| 289 | * Return: 0 if successful, negative error code otherwise |
| 290 | * |
| 291 | * For simplicity, this calculation assumes that all the transfers in the |
| 292 | * periodic schedule may occur in the same (micro)frame |
| 293 | */ |
| 294 | static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, |
| 295 | struct dwc2_qh *qh) |
| 296 | { |
| 297 | int status; |
| 298 | s16 max_claimed_usecs; |
| 299 | |
| 300 | status = 0; |
| 301 | |
| 302 | if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { |
| 303 | /* |
| 304 | * High speed mode |
| 305 | * Max periodic usecs is 80% x 125 usec = 100 usec |
| 306 | */ |
| 307 | max_claimed_usecs = 100 - qh->usecs; |
| 308 | } else { |
| 309 | /* |
| 310 | * Full speed mode |
| 311 | * Max periodic usecs is 90% x 1000 usec = 900 usec |
| 312 | */ |
| 313 | max_claimed_usecs = 900 - qh->usecs; |
| 314 | } |
| 315 | |
| 316 | if (hsotg->periodic_usecs > max_claimed_usecs) { |
| 317 | dev_err(hsotg->dev, |
| 318 | "%s: already claimed usecs %d, required usecs %d\n", |
| 319 | __func__, hsotg->periodic_usecs, qh->usecs); |
| 320 | status = -ENOSPC; |
| 321 | } |
| 322 | |
| 323 | return status; |
| 324 | } |
| 325 | |
| 326 | /** |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 327 | * Microframe scheduler |
| 328 | * track the total use in hsotg->frame_usecs |
| 329 | * keep each qh use in qh->frame_usecs |
| 330 | * when surrendering the qh then donate the time back |
| 331 | */ |
| 332 | static const unsigned short max_uframe_usecs[] = { |
| 333 | 100, 100, 100, 100, 100, 100, 30, 0 |
| 334 | }; |
| 335 | |
| 336 | void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) |
| 337 | { |
| 338 | int i; |
| 339 | |
| 340 | for (i = 0; i < 8; i++) |
| 341 | hsotg->frame_usecs[i] = max_uframe_usecs[i]; |
| 342 | } |
| 343 | |
| 344 | static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 345 | { |
| 346 | unsigned short utime = qh->usecs; |
| 347 | int done = 0; |
| 348 | int i = 0; |
| 349 | int ret = -1; |
| 350 | |
| 351 | while (!done) { |
| 352 | /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ |
| 353 | if (utime <= hsotg->frame_usecs[i]) { |
| 354 | hsotg->frame_usecs[i] -= utime; |
| 355 | qh->frame_usecs[i] += utime; |
| 356 | ret = i; |
| 357 | done = 1; |
| 358 | } else { |
| 359 | i++; |
| 360 | if (i == 8) |
| 361 | done = 1; |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | return ret; |
| 366 | } |
| 367 | |
| 368 | /* |
| 369 | * use this for FS apps that can span multiple uframes |
| 370 | */ |
| 371 | static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 372 | { |
| 373 | unsigned short utime = qh->usecs; |
| 374 | unsigned short xtime; |
| 375 | int t_left = utime; |
| 376 | int done = 0; |
| 377 | int i = 0; |
| 378 | int j; |
| 379 | int ret = -1; |
| 380 | |
| 381 | while (!done) { |
| 382 | if (hsotg->frame_usecs[i] <= 0) { |
| 383 | i++; |
| 384 | if (i == 8) { |
| 385 | ret = -1; |
| 386 | done = 1; |
| 387 | } |
| 388 | continue; |
| 389 | } |
| 390 | |
| 391 | /* |
| 392 | * we need n consecutive slots so use j as a start slot |
| 393 | * j plus j+1 must be enough time (for now) |
| 394 | */ |
| 395 | xtime = hsotg->frame_usecs[i]; |
| 396 | for (j = i + 1; j < 8; j++) { |
| 397 | /* |
| 398 | * if we add this frame remaining time to xtime we may |
| 399 | * be OK, if not we need to test j for a complete frame |
| 400 | */ |
| 401 | if (xtime + hsotg->frame_usecs[j] < utime) { |
| 402 | if (hsotg->frame_usecs[j] < |
| 403 | max_uframe_usecs[j]) { |
| 404 | ret = -1; |
| 405 | break; |
| 406 | } |
| 407 | } |
| 408 | if (xtime >= utime) { |
| 409 | ret = i; |
| 410 | break; |
| 411 | } |
| 412 | /* add the frame time to x time */ |
| 413 | xtime += hsotg->frame_usecs[j]; |
| 414 | /* we must have a fully available next frame or break */ |
| 415 | if (xtime < utime && |
| 416 | hsotg->frame_usecs[j] == max_uframe_usecs[j]) { |
| 417 | ret = -1; |
| 418 | break; |
| 419 | } |
| 420 | } |
| 421 | if (ret >= 0) { |
| 422 | t_left = utime; |
| 423 | for (j = i; t_left > 0 && j < 8; j++) { |
| 424 | t_left -= hsotg->frame_usecs[j]; |
| 425 | if (t_left <= 0) { |
| 426 | qh->frame_usecs[j] += |
| 427 | hsotg->frame_usecs[j] + t_left; |
| 428 | hsotg->frame_usecs[j] = -t_left; |
| 429 | ret = i; |
| 430 | done = 1; |
| 431 | } else { |
| 432 | qh->frame_usecs[j] += |
| 433 | hsotg->frame_usecs[j]; |
| 434 | hsotg->frame_usecs[j] = 0; |
| 435 | } |
| 436 | } |
| 437 | } else { |
| 438 | i++; |
| 439 | if (i == 8) { |
| 440 | ret = -1; |
| 441 | done = 1; |
| 442 | } |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | return ret; |
| 447 | } |
| 448 | |
| 449 | static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 450 | { |
| 451 | int ret; |
| 452 | |
| 453 | if (qh->dev_speed == USB_SPEED_HIGH) { |
| 454 | /* if this is a hs transaction we need a full frame */ |
| 455 | ret = dwc2_find_single_uframe(hsotg, qh); |
| 456 | } else { |
| 457 | /* |
| 458 | * if this is a fs transaction we may need a sequence |
| 459 | * of frames |
| 460 | */ |
| 461 | ret = dwc2_find_multi_uframe(hsotg, qh); |
| 462 | } |
| 463 | return ret; |
| 464 | } |
| 465 | |
| 466 | /** |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 467 | * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a |
| 468 | * host channel is large enough to handle the maximum data transfer in a single |
| 469 | * (micro)frame for a periodic transfer |
| 470 | * |
| 471 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 472 | * @qh: QH for a periodic endpoint |
| 473 | * |
| 474 | * Return: 0 if successful, negative error code otherwise |
| 475 | */ |
| 476 | static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, |
| 477 | struct dwc2_qh *qh) |
| 478 | { |
| 479 | u32 max_xfer_size; |
| 480 | u32 max_channel_xfer_size; |
| 481 | int status = 0; |
| 482 | |
| 483 | max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); |
| 484 | max_channel_xfer_size = hsotg->core_params->max_transfer_size; |
| 485 | |
| 486 | if (max_xfer_size > max_channel_xfer_size) { |
| 487 | dev_err(hsotg->dev, |
| 488 | "%s: Periodic xfer length %d > max xfer length for channel %d\n", |
| 489 | __func__, max_xfer_size, max_channel_xfer_size); |
| 490 | status = -ENOSPC; |
| 491 | } |
| 492 | |
| 493 | return status; |
| 494 | } |
| 495 | |
| 496 | /** |
| 497 | * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in |
| 498 | * the periodic schedule |
| 499 | * |
| 500 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 501 | * @qh: QH for the periodic transfer. The QH should already contain the |
| 502 | * scheduling information. |
| 503 | * |
| 504 | * Return: 0 if successful, negative error code otherwise |
| 505 | */ |
| 506 | static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 507 | { |
| 508 | int status; |
| 509 | |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 510 | if (hsotg->core_params->uframe_sched > 0) { |
| 511 | int frame = -1; |
| 512 | |
| 513 | status = dwc2_find_uframe(hsotg, qh); |
| 514 | if (status == 0) |
| 515 | frame = 7; |
| 516 | else if (status > 0) |
| 517 | frame = status - 1; |
| 518 | |
| 519 | /* Set the new frame up */ |
| 520 | if (frame > -1) { |
| 521 | qh->sched_frame &= ~0x7; |
| 522 | qh->sched_frame |= (frame & 7); |
| 523 | } |
| 524 | |
| 525 | if (status != -1) |
| 526 | status = 0; |
| 527 | } else { |
| 528 | status = dwc2_periodic_channel_available(hsotg); |
| 529 | if (status) { |
| 530 | dev_info(hsotg->dev, |
| 531 | "%s: No host channel available for periodic transfer\n", |
| 532 | __func__); |
| 533 | return status; |
| 534 | } |
| 535 | |
| 536 | status = dwc2_check_periodic_bandwidth(hsotg, qh); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 537 | } |
| 538 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 539 | if (status) { |
| 540 | dev_dbg(hsotg->dev, |
| 541 | "%s: Insufficient periodic bandwidth for periodic transfer\n", |
| 542 | __func__); |
| 543 | return status; |
| 544 | } |
| 545 | |
| 546 | status = dwc2_check_max_xfer_size(hsotg, qh); |
| 547 | if (status) { |
| 548 | dev_dbg(hsotg->dev, |
| 549 | "%s: Channel max transfer size too small for periodic transfer\n", |
| 550 | __func__); |
| 551 | return status; |
| 552 | } |
| 553 | |
| 554 | if (hsotg->core_params->dma_desc_enable > 0) |
| 555 | /* Don't rely on SOF and start in ready schedule */ |
| 556 | list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); |
| 557 | else |
| 558 | /* Always start in inactive schedule */ |
| 559 | list_add_tail(&qh->qh_list_entry, |
| 560 | &hsotg->periodic_sched_inactive); |
| 561 | |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 562 | if (hsotg->core_params->uframe_sched <= 0) |
| 563 | /* Reserve periodic channel */ |
| 564 | hsotg->periodic_channels++; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 565 | |
| 566 | /* Update claimed usecs per (micro)frame */ |
| 567 | hsotg->periodic_usecs += qh->usecs; |
| 568 | |
| 569 | return status; |
| 570 | } |
| 571 | |
| 572 | /** |
| 573 | * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer |
| 574 | * from the periodic schedule |
| 575 | * |
| 576 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 577 | * @qh: QH for the periodic transfer |
| 578 | */ |
| 579 | static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, |
| 580 | struct dwc2_qh *qh) |
| 581 | { |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 582 | int i; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 583 | |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 584 | list_del_init(&qh->qh_list_entry); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 585 | |
| 586 | /* Update claimed usecs per (micro)frame */ |
| 587 | hsotg->periodic_usecs -= qh->usecs; |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 588 | |
| 589 | if (hsotg->core_params->uframe_sched > 0) { |
| 590 | for (i = 0; i < 8; i++) { |
| 591 | hsotg->frame_usecs[i] += qh->frame_usecs[i]; |
| 592 | qh->frame_usecs[i] = 0; |
| 593 | } |
| 594 | } else { |
| 595 | /* Release periodic channel reservation */ |
| 596 | hsotg->periodic_channels--; |
| 597 | } |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 598 | } |
| 599 | |
| 600 | /** |
| 601 | * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic |
| 602 | * schedule if it is not already in the schedule. If the QH is already in |
| 603 | * the schedule, no action is taken. |
| 604 | * |
| 605 | * @hsotg: The HCD state structure for the DWC OTG controller |
| 606 | * @qh: The QH to add |
| 607 | * |
| 608 | * Return: 0 if successful, negative error code otherwise |
| 609 | */ |
| 610 | int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 611 | { |
| 612 | int status = 0; |
| 613 | u32 intr_mask; |
| 614 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 615 | if (dbg_qh(qh)) |
| 616 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 617 | |
| 618 | if (!list_empty(&qh->qh_list_entry)) |
| 619 | /* QH already in a schedule */ |
| 620 | return status; |
| 621 | |
| 622 | /* Add the new QH to the appropriate schedule */ |
| 623 | if (dwc2_qh_is_non_per(qh)) { |
| 624 | /* Always start in inactive schedule */ |
| 625 | list_add_tail(&qh->qh_list_entry, |
| 626 | &hsotg->non_periodic_sched_inactive); |
| 627 | } else { |
| 628 | status = dwc2_schedule_periodic(hsotg, qh); |
| 629 | if (status == 0) { |
| 630 | if (!hsotg->periodic_qh_count) { |
| 631 | intr_mask = readl(hsotg->regs + GINTMSK); |
| 632 | intr_mask |= GINTSTS_SOF; |
| 633 | writel(intr_mask, hsotg->regs + GINTMSK); |
| 634 | } |
| 635 | hsotg->periodic_qh_count++; |
| 636 | } |
| 637 | } |
| 638 | |
| 639 | return status; |
| 640 | } |
| 641 | |
| 642 | /** |
| 643 | * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic |
| 644 | * schedule. Memory is not freed. |
| 645 | * |
| 646 | * @hsotg: The HCD state structure |
| 647 | * @qh: QH to remove from schedule |
| 648 | */ |
| 649 | void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
| 650 | { |
| 651 | u32 intr_mask; |
| 652 | |
| 653 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 654 | |
| 655 | if (list_empty(&qh->qh_list_entry)) |
| 656 | /* QH is not in a schedule */ |
| 657 | return; |
| 658 | |
| 659 | if (dwc2_qh_is_non_per(qh)) { |
| 660 | if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) |
| 661 | hsotg->non_periodic_qh_ptr = |
| 662 | hsotg->non_periodic_qh_ptr->next; |
| 663 | list_del_init(&qh->qh_list_entry); |
| 664 | } else { |
| 665 | dwc2_deschedule_periodic(hsotg, qh); |
| 666 | hsotg->periodic_qh_count--; |
| 667 | if (!hsotg->periodic_qh_count) { |
| 668 | intr_mask = readl(hsotg->regs + GINTMSK); |
| 669 | intr_mask &= ~GINTSTS_SOF; |
| 670 | writel(intr_mask, hsotg->regs + GINTMSK); |
| 671 | } |
| 672 | } |
| 673 | } |
| 674 | |
| 675 | /* |
| 676 | * Schedule the next continuing periodic split transfer |
| 677 | */ |
| 678 | static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, |
| 679 | struct dwc2_qh *qh, u16 frame_number, |
| 680 | int sched_next_periodic_split) |
| 681 | { |
| 682 | u16 incr; |
| 683 | |
| 684 | if (sched_next_periodic_split) { |
| 685 | qh->sched_frame = frame_number; |
| 686 | incr = dwc2_frame_num_inc(qh->start_split_frame, 1); |
| 687 | if (dwc2_frame_num_le(frame_number, incr)) { |
| 688 | /* |
| 689 | * Allow one frame to elapse after start split |
| 690 | * microframe before scheduling complete split, but |
| 691 | * DON'T if we are doing the next start split in the |
| 692 | * same frame for an ISOC out |
| 693 | */ |
| 694 | if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || |
| 695 | qh->ep_is_in != 0) { |
| 696 | qh->sched_frame = |
| 697 | dwc2_frame_num_inc(qh->sched_frame, 1); |
| 698 | } |
| 699 | } |
| 700 | } else { |
| 701 | qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, |
| 702 | qh->interval); |
| 703 | if (dwc2_frame_num_le(qh->sched_frame, frame_number)) |
| 704 | qh->sched_frame = frame_number; |
| 705 | qh->sched_frame |= 0x7; |
| 706 | qh->start_split_frame = qh->sched_frame; |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | /* |
| 711 | * Deactivates a QH. For non-periodic QHs, removes the QH from the active |
| 712 | * non-periodic schedule. The QH is added to the inactive non-periodic |
| 713 | * schedule if any QTDs are still attached to the QH. |
| 714 | * |
| 715 | * For periodic QHs, the QH is removed from the periodic queued schedule. If |
| 716 | * there are any QTDs still attached to the QH, the QH is added to either the |
| 717 | * periodic inactive schedule or the periodic ready schedule and its next |
| 718 | * scheduled frame is calculated. The QH is placed in the ready schedule if |
| 719 | * the scheduled frame has been reached already. Otherwise it's placed in the |
| 720 | * inactive schedule. If there are no QTDs attached to the QH, the QH is |
| 721 | * completely removed from the periodic schedule. |
| 722 | */ |
| 723 | void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, |
| 724 | int sched_next_periodic_split) |
| 725 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 726 | if (dbg_qh(qh)) |
| 727 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 728 | |
| 729 | if (dwc2_qh_is_non_per(qh)) { |
| 730 | dwc2_hcd_qh_unlink(hsotg, qh); |
| 731 | if (!list_empty(&qh->qtd_list)) |
| 732 | /* Add back to inactive non-periodic schedule */ |
| 733 | dwc2_hcd_qh_add(hsotg, qh); |
| 734 | } else { |
| 735 | u16 frame_number = dwc2_hcd_get_frame_number(hsotg); |
| 736 | |
| 737 | if (qh->do_split) { |
| 738 | dwc2_sched_periodic_split(hsotg, qh, frame_number, |
| 739 | sched_next_periodic_split); |
| 740 | } else { |
| 741 | qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, |
| 742 | qh->interval); |
| 743 | if (dwc2_frame_num_le(qh->sched_frame, frame_number)) |
| 744 | qh->sched_frame = frame_number; |
| 745 | } |
| 746 | |
| 747 | if (list_empty(&qh->qtd_list)) { |
| 748 | dwc2_hcd_qh_unlink(hsotg, qh); |
| 749 | } else { |
| 750 | /* |
| 751 | * Remove from periodic_sched_queued and move to |
| 752 | * appropriate queue |
| 753 | */ |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame^] | 754 | if ((hsotg->core_params->uframe_sched > 0 && |
| 755 | dwc2_frame_num_le(qh->sched_frame, frame_number)) |
| 756 | || (hsotg->core_params->uframe_sched <= 0 && |
| 757 | qh->sched_frame == frame_number)) |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 758 | list_move(&qh->qh_list_entry, |
| 759 | &hsotg->periodic_sched_ready); |
| 760 | else |
| 761 | list_move(&qh->qh_list_entry, |
| 762 | &hsotg->periodic_sched_inactive); |
| 763 | } |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | /** |
| 768 | * dwc2_hcd_qtd_init() - Initializes a QTD structure |
| 769 | * |
| 770 | * @qtd: The QTD to initialize |
| 771 | * @urb: The associated URB |
| 772 | */ |
| 773 | void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) |
| 774 | { |
| 775 | qtd->urb = urb; |
| 776 | if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == |
| 777 | USB_ENDPOINT_XFER_CONTROL) { |
| 778 | /* |
| 779 | * The only time the QTD data toggle is used is on the data |
| 780 | * phase of control transfers. This phase always starts with |
| 781 | * DATA1. |
| 782 | */ |
| 783 | qtd->data_toggle = DWC2_HC_PID_DATA1; |
| 784 | qtd->control_phase = DWC2_CONTROL_SETUP; |
| 785 | } |
| 786 | |
| 787 | /* Start split */ |
| 788 | qtd->complete_split = 0; |
| 789 | qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; |
| 790 | qtd->isoc_split_offset = 0; |
| 791 | qtd->in_process = 0; |
| 792 | |
| 793 | /* Store the qtd ptr in the urb to reference the QTD */ |
| 794 | urb->qtd = qtd; |
| 795 | } |
| 796 | |
| 797 | /** |
| 798 | * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH |
| 799 | * |
| 800 | * @hsotg: The DWC HCD structure |
| 801 | * @qtd: The QTD to add |
| 802 | * @qh: Out parameter to return queue head |
| 803 | * @atomic_alloc: Flag to do atomic alloc if needed |
| 804 | * |
| 805 | * Return: 0 if successful, negative error code otherwise |
| 806 | * |
| 807 | * Finds the correct QH to place the QTD into. If it does not find a QH, it |
| 808 | * will create a new QH. If the QH to which the QTD is added is not currently |
| 809 | * scheduled, it is placed into the proper schedule based on its EP type. |
| 810 | */ |
| 811 | int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, |
| 812 | struct dwc2_qh **qh, gfp_t mem_flags) |
| 813 | { |
| 814 | struct dwc2_hcd_urb *urb = qtd->urb; |
| 815 | unsigned long flags; |
| 816 | int allocated = 0; |
Paul Zimmerman | b2d6cb5 | 2013-07-13 14:53:51 -0700 | [diff] [blame] | 817 | int retval; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 818 | |
| 819 | /* |
| 820 | * Get the QH which holds the QTD-list to insert to. Create QH if it |
| 821 | * doesn't exist. |
| 822 | */ |
| 823 | if (*qh == NULL) { |
| 824 | *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); |
| 825 | if (*qh == NULL) |
| 826 | return -ENOMEM; |
| 827 | allocated = 1; |
| 828 | } |
| 829 | |
| 830 | spin_lock_irqsave(&hsotg->lock, flags); |
Paul Zimmerman | b2d6cb5 | 2013-07-13 14:53:51 -0700 | [diff] [blame] | 831 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 832 | retval = dwc2_hcd_qh_add(hsotg, *qh); |
Paul Zimmerman | b2d6cb5 | 2013-07-13 14:53:51 -0700 | [diff] [blame] | 833 | if (retval) |
| 834 | goto fail; |
| 835 | |
| 836 | qtd->qh = *qh; |
| 837 | list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list); |
| 838 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 839 | |
| 840 | return 0; |
| 841 | |
| 842 | fail: |
| 843 | if (allocated) { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 844 | struct dwc2_qtd *qtd2, *qtd2_tmp; |
| 845 | struct dwc2_qh *qh_tmp = *qh; |
| 846 | |
| 847 | *qh = NULL; |
| 848 | dwc2_hcd_qh_unlink(hsotg, qh_tmp); |
| 849 | |
| 850 | /* Free each QTD in the QH's QTD list */ |
| 851 | list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list, |
| 852 | qtd_list_entry) |
| 853 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); |
| 854 | |
| 855 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 856 | dwc2_hcd_qh_free(hsotg, qh_tmp); |
| 857 | } else { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 858 | spin_unlock_irqrestore(&hsotg->lock, flags); |
| 859 | } |
| 860 | |
| 861 | return retval; |
| 862 | } |