Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 219f43164e8c611c6b8e7b628def9183098b430b / . / sound / soc / omap / mcbsp.h
blob: 5590ab271eecaa1ad91f3ec0d2086d89ec6bfbb8 [file] [log] [blame]
Peter Ujfalusi219f4312012-02-03 13:11:47 +0200[diff] [blame^]1/*
2 * sound/soc/omap/mcbsp.h
3 *
4 * OMAP Multi-Channel Buffered Serial Port
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASOC_MCBSP_H
25#define __ASOC_MCBSP_H
26
27/* McBSP register numbers. Register address offset = num * reg_step */
28enum {
29 /* Common registers */
30 OMAP_MCBSP_REG_SPCR2 = 4,
31 OMAP_MCBSP_REG_SPCR1,
32 OMAP_MCBSP_REG_RCR2,
33 OMAP_MCBSP_REG_RCR1,
34 OMAP_MCBSP_REG_XCR2,
35 OMAP_MCBSP_REG_XCR1,
36 OMAP_MCBSP_REG_SRGR2,
37 OMAP_MCBSP_REG_SRGR1,
38 OMAP_MCBSP_REG_MCR2,
39 OMAP_MCBSP_REG_MCR1,
40 OMAP_MCBSP_REG_RCERA,
41 OMAP_MCBSP_REG_RCERB,
42 OMAP_MCBSP_REG_XCERA,
43 OMAP_MCBSP_REG_XCERB,
44 OMAP_MCBSP_REG_PCR0,
45 OMAP_MCBSP_REG_RCERC,
46 OMAP_MCBSP_REG_RCERD,
47 OMAP_MCBSP_REG_XCERC,
48 OMAP_MCBSP_REG_XCERD,
49 OMAP_MCBSP_REG_RCERE,
50 OMAP_MCBSP_REG_RCERF,
51 OMAP_MCBSP_REG_XCERE,
52 OMAP_MCBSP_REG_XCERF,
53 OMAP_MCBSP_REG_RCERG,
54 OMAP_MCBSP_REG_RCERH,
55 OMAP_MCBSP_REG_XCERG,
56 OMAP_MCBSP_REG_XCERH,
57
58 /* OMAP1-OMAP2420 registers */
59 OMAP_MCBSP_REG_DRR2 = 0,
60 OMAP_MCBSP_REG_DRR1,
61 OMAP_MCBSP_REG_DXR2,
62 OMAP_MCBSP_REG_DXR1,
63
64 /* OMAP2430 and onwards */
65 OMAP_MCBSP_REG_DRR = 0,
66 OMAP_MCBSP_REG_DXR = 2,
67 OMAP_MCBSP_REG_SYSCON = 35,
68 OMAP_MCBSP_REG_THRSH2,
69 OMAP_MCBSP_REG_THRSH1,
70 OMAP_MCBSP_REG_IRQST = 40,
71 OMAP_MCBSP_REG_IRQEN,
72 OMAP_MCBSP_REG_WAKEUPEN,
73 OMAP_MCBSP_REG_XCCR,
74 OMAP_MCBSP_REG_RCCR,
75 OMAP_MCBSP_REG_XBUFFSTAT,
76 OMAP_MCBSP_REG_RBUFFSTAT,
77 OMAP_MCBSP_REG_SSELCR,
78};
79
80/* OMAP3 sidetone control registers */
81#define OMAP_ST_REG_REV 0x00
82#define OMAP_ST_REG_SYSCONFIG 0x10
83#define OMAP_ST_REG_IRQSTATUS 0x18
84#define OMAP_ST_REG_IRQENABLE 0x1C
85#define OMAP_ST_REG_SGAINCR 0x24
86#define OMAP_ST_REG_SFIRCR 0x28
87#define OMAP_ST_REG_SSELCR 0x2C
88
89/************************** McBSP SPCR1 bit definitions ***********************/
90#define RRST 0x0001
91#define RRDY 0x0002
92#define RFULL 0x0004
93#define RSYNC_ERR 0x0008
94#define RINTM(value) ((value)<<4) /* bits 4:5 */
95#define ABIS 0x0040
96#define DXENA 0x0080
97#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
98#define RJUST(value) ((value)<<13) /* bits 13:14 */
99#define ALB 0x8000
100#define DLB 0x8000
101
102/************************** McBSP SPCR2 bit definitions ***********************/
103#define XRST 0x0001
104#define XRDY 0x0002
105#define XEMPTY 0x0004
106#define XSYNC_ERR 0x0008
107#define XINTM(value) ((value)<<4) /* bits 4:5 */
108#define GRST 0x0040
109#define FRST 0x0080
110#define SOFT 0x0100
111#define FREE 0x0200
112
113/************************** McBSP PCR bit definitions *************************/
114#define CLKRP 0x0001
115#define CLKXP 0x0002
116#define FSRP 0x0004
117#define FSXP 0x0008
118#define DR_STAT 0x0010
119#define DX_STAT 0x0020
120#define CLKS_STAT 0x0040
121#define SCLKME 0x0080
122#define CLKRM 0x0100
123#define CLKXM 0x0200
124#define FSRM 0x0400
125#define FSXM 0x0800
126#define RIOEN 0x1000
127#define XIOEN 0x2000
128#define IDLE_EN 0x4000
129
130/************************** McBSP RCR1 bit definitions ************************/
131#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
132#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
133
134/************************** McBSP XCR1 bit definitions ************************/
135#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
136#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
137
138/*************************** McBSP RCR2 bit definitions ***********************/
139#define RDATDLY(value) (value) /* Bits 0:1 */
140#define RFIG 0x0004
141#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
142#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
143#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
144#define RPHASE 0x8000
145
146/*************************** McBSP XCR2 bit definitions ***********************/
147#define XDATDLY(value) (value) /* Bits 0:1 */
148#define XFIG 0x0004
149#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
150#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
151#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
152#define XPHASE 0x8000
153
154/************************* McBSP SRGR1 bit definitions ************************/
155#define CLKGDV(value) (value) /* Bits 0:7 */
156#define FWID(value) ((value)<<8) /* Bits 8:15 */
157
158/************************* McBSP SRGR2 bit definitions ************************/
159#define FPER(value) (value) /* Bits 0:11 */
160#define FSGM 0x1000
161#define CLKSM 0x2000
162#define CLKSP 0x4000
163#define GSYNC 0x8000
164
165/************************* McBSP MCR1 bit definitions *************************/
166#define RMCM 0x0001
167#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
168#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
169#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
170
171/************************* McBSP MCR2 bit definitions *************************/
172#define XMCM(value) (value) /* Bits 0:1 */
173#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
174#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
175#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
176
177/*********************** McBSP XCCR bit definitions *************************/
178#define EXTCLKGATE 0x8000
179#define PPCONNECT 0x4000
180#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
181#define XFULL_CYCLE 0x0800
182#define DILB 0x0020
183#define XDMAEN 0x0008
184#define XDISABLE 0x0001
185
186/********************** McBSP RCCR bit definitions *************************/
187#define RFULL_CYCLE 0x0800
188#define RDMAEN 0x0008
189#define RDISABLE 0x0001
190
191/********************** McBSP SYSCONFIG bit definitions ********************/
192#define CLOCKACTIVITY(value) ((value)<<8)
193#define SIDLEMODE(value) ((value)<<3)
194#define ENAWAKEUP 0x0004
195#define SOFTRST 0x0002
196
197/********************** McBSP SSELCR bit definitions ***********************/
198#define SIDETONEEN 0x0400
199
200/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
201#define ST_AUTOIDLE 0x0001
202
203/********************** McBSP Sidetone SGAINCR bit definitions *************/
204#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
205#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
206
207/********************** McBSP Sidetone SFIRCR bit definitions **************/
208#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
209
210/********************** McBSP Sidetone SSELCR bit definitions **************/
211#define ST_COEFFWRDONE 0x0004
212#define ST_COEFFWREN 0x0002
213#define ST_SIDETONEEN 0x0001
214
215/********************** McBSP DMA operating modes **************************/
216#define MCBSP_DMA_MODE_ELEMENT 0
217#define MCBSP_DMA_MODE_THRESHOLD 1
218#define MCBSP_DMA_MODE_FRAME 2
219
220/********************** McBSP WAKEUPEN bit definitions *********************/
221#define XEMPTYEOFEN 0x4000
222#define XRDYEN 0x0400
223#define XEOFEN 0x0200
224#define XFSXEN 0x0100
225#define XSYNCERREN 0x0080
226#define RRDYEN 0x0008
227#define REOFEN 0x0004
228#define RFSREN 0x0002
229#define RSYNCERREN 0x0001
230
231/* we don't do multichannel for now */
232struct omap_mcbsp_reg_cfg {
233 u16 spcr2;
234 u16 spcr1;
235 u16 rcr2;
236 u16 rcr1;
237 u16 xcr2;
238 u16 xcr1;
239 u16 srgr2;
240 u16 srgr1;
241 u16 mcr2;
242 u16 mcr1;
243 u16 pcr0;
244 u16 rcerc;
245 u16 rcerd;
246 u16 xcerc;
247 u16 xcerd;
248 u16 rcere;
249 u16 rcerf;
250 u16 xcere;
251 u16 xcerf;
252 u16 rcerg;
253 u16 rcerh;
254 u16 xcerg;
255 u16 xcerh;
256 u16 xccr;
257 u16 rccr;
258};
259
260void omap_mcbsp_config(unsigned int id,
261 const struct omap_mcbsp_reg_cfg *config);
262void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
263void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
264u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
265u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
266u16 omap_mcbsp_get_fifo_size(unsigned int id);
267u16 omap_mcbsp_get_tx_delay(unsigned int id);
268u16 omap_mcbsp_get_rx_delay(unsigned int id);
269int omap_mcbsp_get_dma_op_mode(unsigned int id);
270int omap_mcbsp_request(unsigned int id);
271void omap_mcbsp_free(unsigned int id);
272void omap_mcbsp_start(unsigned int id, int tx, int rx);
273void omap_mcbsp_stop(unsigned int id, int tx, int rx);
274
275/* McBSP functional clock source changing function */
276int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
277
278/* McBSP signal muxing API */
279void omap2_mcbsp1_mux_clkr_src(u8 mux);
280void omap2_mcbsp1_mux_fsr_src(u8 mux);
281
282int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
283int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
284
285/* Sidetone specific API */
286int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
287int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
288int omap_st_enable(unsigned int id);
289int omap_st_disable(unsigned int id);
290int omap_st_is_enabled(unsigned int id);
291
292#endif /* __ASOC_MCBSP_H */