| Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1 | /* mach/dma.h - arch-specific DMA defines |
| Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 2 | * |
| Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 4 | * |
| Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 5 | * Licensed under the GPL-2 or later. |
| Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _MACH_DMA_H_ |
| 9 | #define _MACH_DMA_H_ |
| 10 | |
| 11 | #define CH_PPI 0 |
| 12 | #define CH_SPORT0_RX 1 |
| 13 | #define CH_SPORT0_TX 2 |
| 14 | #define CH_SPORT1_RX 3 |
| 15 | #define CH_SPORT1_TX 4 |
| 16 | #define CH_SPI0 5 |
| 17 | #define CH_UART0_RX 6 |
| 18 | #define CH_UART0_TX 7 |
| 19 | #define CH_SPORT2_RX 8 |
| 20 | #define CH_SPORT2_TX 9 |
| 21 | #define CH_SPORT3_RX 10 |
| 22 | #define CH_SPORT3_TX 11 |
| 23 | #define CH_SPI1 14 |
| 24 | #define CH_SPI2 15 |
| 25 | #define CH_UART1_RX 16 |
| 26 | #define CH_UART1_TX 17 |
| 27 | #define CH_UART2_RX 18 |
| 28 | #define CH_UART2_TX 19 |
| 29 | |
| 30 | #define CH_MEM_STREAM0_DEST 20 |
| 31 | #define CH_MEM_STREAM0_SRC 21 |
| 32 | #define CH_MEM_STREAM1_DEST 22 |
| 33 | #define CH_MEM_STREAM1_SRC 23 |
| 34 | #define CH_MEM_STREAM2_DEST 24 |
| 35 | #define CH_MEM_STREAM2_SRC 25 |
| 36 | #define CH_MEM_STREAM3_DEST 26 |
| 37 | #define CH_MEM_STREAM3_SRC 27 |
| 38 | |
| Mike Frysinger | 211daf9 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 39 | #define MAX_DMA_CHANNELS 28 |
| Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 40 | |
| 41 | #endif |