Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * arch/arm/mach-u300/clock.c |
| 4 | * |
| 5 | * |
| 6 | * Copyright (C) 2007-2009 ST-Ericsson AB |
| 7 | * License terms: GNU General Public License (GPL) version 2 |
| 8 | * Define clocks in the app platform. |
| 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 10 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/string.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/mutex.h> |
| 21 | #include <linux/spinlock.h> |
| 22 | #include <linux/debugfs.h> |
| 23 | #include <linux/device.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/timer.h> |
| 26 | #include <linux/io.h> |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 27 | #include <linux/seq_file.h> |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 28 | |
| 29 | #include <asm/clkdev.h> |
| 30 | #include <mach/hardware.h> |
| 31 | #include <mach/syscon.h> |
| 32 | |
| 33 | #include "clock.h" |
| 34 | |
| 35 | /* |
| 36 | * TODO: |
| 37 | * - move all handling of the CCR register into this file and create |
| 38 | * a spinlock for the CCR register |
| 39 | * - switch to the clkdevice lookup mechanism that maps clocks to |
| 40 | * device ID:s instead when it becomes available in kernel 2.6.29. |
| 41 | * - implement rate get/set for all clocks that need it. |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | * Syscon clock I/O registers lock so clock requests don't collide |
| 46 | * NOTE: this is a local lock only used to lock access to clock and |
| 47 | * reset registers in syscon. |
| 48 | */ |
| 49 | static DEFINE_SPINLOCK(syscon_clkreg_lock); |
| 50 | static DEFINE_SPINLOCK(syscon_resetreg_lock); |
| 51 | |
| 52 | /* |
| 53 | * The clocking hierarchy currently looks like this. |
| 54 | * NOTE: the idea is NOT to show how the clocks are routed on the chip! |
| 55 | * The ideas is to show dependencies, so a clock higher up in the |
| 56 | * hierarchy has to be on in order for another clock to be on. Now, |
| 57 | * both CPU and DMA can actually be on top of the hierarchy, and that |
| 58 | * is not modeled currently. Instead we have the backbone AMBA bus on |
| 59 | * top. This bus cannot be programmed in any way but conceptually it |
| 60 | * needs to be active for the bridges and devices to transport data. |
| 61 | * |
| 62 | * Please be aware that a few clocks are hw controlled, which mean that |
| 63 | * the hw itself can turn on/off or change the rate of the clock when |
| 64 | * needed! |
| 65 | * |
| 66 | * AMBA bus |
| 67 | * | |
| 68 | * +- CPU |
| 69 | * +- NANDIF NAND Flash interface |
| 70 | * +- SEMI Shared Memory interface |
| 71 | * +- ISP Image Signal Processor (U335 only) |
| 72 | * +- CDS (U335 only) |
| 73 | * +- DMA Direct Memory Access Controller |
| 74 | * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL) |
| 75 | * +- APEX |
| 76 | * +- VIDEO_ENC AVE2/3 Video Encoder |
| 77 | * +- XGAM Graphics Accelerator Controller |
| 78 | * +- AHB |
| 79 | * | |
| 80 | * +- ahb:0 AHB Bridge |
| 81 | * | | |
| 82 | * | +- ahb:1 INTCON Interrupt controller |
| 83 | * | +- ahb:3 MSPRO Memory Stick Pro controller |
| 84 | * | +- ahb:4 EMIF External Memory interface |
| 85 | * | |
| 86 | * +- fast:0 FAST bridge |
| 87 | * | | |
| 88 | * | +- fast:1 MMCSD MMC/SD card reader controller |
| 89 | * | +- fast:2 I2S0 PCM I2S channel 0 controller |
| 90 | * | +- fast:3 I2S1 PCM I2S channel 1 controller |
| 91 | * | +- fast:4 I2C0 I2C channel 0 controller |
| 92 | * | +- fast:5 I2C1 I2C channel 1 controller |
| 93 | * | +- fast:6 SPI SPI controller |
| 94 | * | +- fast:7 UART1 Secondary UART (U335 only) |
| 95 | * | |
| 96 | * +- slow:0 SLOW bridge |
| 97 | * | |
| 98 | * +- slow:1 SYSCON (not possible to control) |
| 99 | * +- slow:2 WDOG Watchdog |
| 100 | * +- slow:3 UART0 primary UART |
| 101 | * +- slow:4 TIMER_APP Application timer - used in Linux |
| 102 | * +- slow:5 KEYPAD controller |
| 103 | * +- slow:6 GPIO controller |
| 104 | * +- slow:7 RTC controller |
| 105 | * +- slow:8 BT Bus Tracer (not used currently) |
| 106 | * +- slow:9 EH Event Handler (not used currently) |
| 107 | * +- slow:a TIMER_ACC Access style timer (not used currently) |
| 108 | * +- slow:b PPM (U335 only, what is that?) |
| 109 | */ |
| 110 | |
| 111 | /* |
| 112 | * Reset control functions. We remember if a block has been |
| 113 | * taken out of reset and don't remove the reset assertion again |
| 114 | * and vice versa. Currently we only remove resets so the |
| 115 | * enablement function is defined out. |
| 116 | */ |
| 117 | static void syscon_block_reset_enable(struct clk *clk) |
| 118 | { |
| 119 | u16 val; |
| 120 | unsigned long iflags; |
| 121 | |
| 122 | /* Not all blocks support resetting */ |
| 123 | if (!clk->res_reg || !clk->res_mask) |
| 124 | return; |
| 125 | spin_lock_irqsave(&syscon_resetreg_lock, iflags); |
| 126 | val = readw(clk->res_reg); |
| 127 | val |= clk->res_mask; |
| 128 | writew(val, clk->res_reg); |
| 129 | spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); |
| 130 | clk->reset = true; |
| 131 | } |
| 132 | |
| 133 | static void syscon_block_reset_disable(struct clk *clk) |
| 134 | { |
| 135 | u16 val; |
| 136 | unsigned long iflags; |
| 137 | |
| 138 | /* Not all blocks support resetting */ |
| 139 | if (!clk->res_reg || !clk->res_mask) |
| 140 | return; |
| 141 | spin_lock_irqsave(&syscon_resetreg_lock, iflags); |
| 142 | val = readw(clk->res_reg); |
| 143 | val &= ~clk->res_mask; |
| 144 | writew(val, clk->res_reg); |
| 145 | spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); |
| 146 | clk->reset = false; |
| 147 | } |
| 148 | |
| 149 | int __clk_get(struct clk *clk) |
| 150 | { |
| 151 | u16 val; |
| 152 | |
| 153 | /* The MMC and MSPRO clocks need some special set-up */ |
| 154 | if (!strcmp(clk->name, "MCLK")) { |
| 155 | /* Set default MMC clock divisor to 18.9 MHz */ |
| 156 | writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R); |
| 157 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); |
| 158 | /* Disable the MMC feedback clock */ |
| 159 | val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; |
| 160 | /* Disable MSPRO frequency */ |
| 161 | val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; |
| 162 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR); |
| 163 | } |
| 164 | if (!strcmp(clk->name, "MSPRO")) { |
| 165 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); |
| 166 | /* Disable the MMC feedback clock */ |
| 167 | val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; |
| 168 | /* Enable MSPRO frequency */ |
| 169 | val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; |
| 170 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR); |
| 171 | } |
| 172 | return 1; |
| 173 | } |
| 174 | EXPORT_SYMBOL(__clk_get); |
| 175 | |
| 176 | void __clk_put(struct clk *clk) |
| 177 | { |
| 178 | } |
| 179 | EXPORT_SYMBOL(__clk_put); |
| 180 | |
| 181 | static void syscon_clk_disable(struct clk *clk) |
| 182 | { |
| 183 | unsigned long iflags; |
| 184 | |
| 185 | /* Don't touch the hardware controlled clocks */ |
| 186 | if (clk->hw_ctrld) |
| 187 | return; |
| 188 | |
| 189 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 190 | writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR); |
| 191 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 192 | } |
| 193 | |
| 194 | static void syscon_clk_enable(struct clk *clk) |
| 195 | { |
| 196 | unsigned long iflags; |
| 197 | |
| 198 | /* Don't touch the hardware controlled clocks */ |
| 199 | if (clk->hw_ctrld) |
| 200 | return; |
| 201 | |
| 202 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 203 | writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER); |
| 204 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 205 | } |
| 206 | |
| 207 | static u16 syscon_clk_get_rate(void) |
| 208 | { |
| 209 | u16 val; |
| 210 | unsigned long iflags; |
| 211 | |
| 212 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 213 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 214 | val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; |
| 215 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 216 | return val; |
| 217 | } |
| 218 | |
| 219 | #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER |
| 220 | static void enable_i2s0_vcxo(void) |
| 221 | { |
| 222 | u16 val; |
| 223 | unsigned long iflags; |
| 224 | |
| 225 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 226 | /* Set I2S0 to use the VCXO 26 MHz clock */ |
| 227 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 228 | val |= U300_SYSCON_CCR_TURN_VCXO_ON; |
| 229 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 230 | val |= U300_SYSCON_CCR_I2S0_USE_VCXO; |
| 231 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 232 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 233 | val |= U300_SYSCON_CEFR_I2S0_CLK_EN; |
| 234 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 235 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 236 | } |
| 237 | |
| 238 | static void enable_i2s1_vcxo(void) |
| 239 | { |
| 240 | u16 val; |
| 241 | unsigned long iflags; |
| 242 | |
| 243 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 244 | /* Set I2S1 to use the VCXO 26 MHz clock */ |
| 245 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 246 | val |= U300_SYSCON_CCR_TURN_VCXO_ON; |
| 247 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 248 | val |= U300_SYSCON_CCR_I2S1_USE_VCXO; |
| 249 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 250 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 251 | val |= U300_SYSCON_CEFR_I2S1_CLK_EN; |
| 252 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 253 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 254 | } |
| 255 | |
| 256 | static void disable_i2s0_vcxo(void) |
| 257 | { |
| 258 | u16 val; |
| 259 | unsigned long iflags; |
| 260 | |
| 261 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 262 | /* Disable I2S0 use of the VCXO 26 MHz clock */ |
| 263 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 264 | val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO; |
| 265 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 266 | /* Deactivate VCXO if noone else is using VCXO */ |
| 267 | if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO)) |
| 268 | val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; |
| 269 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 270 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 271 | val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN; |
| 272 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 273 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 274 | } |
| 275 | |
| 276 | static void disable_i2s1_vcxo(void) |
| 277 | { |
| 278 | u16 val; |
| 279 | unsigned long iflags; |
| 280 | |
| 281 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 282 | /* Disable I2S1 use of the VCXO 26 MHz clock */ |
| 283 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 284 | val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO; |
| 285 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 286 | /* Deactivate VCXO if noone else is using VCXO */ |
| 287 | if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO)) |
| 288 | val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; |
| 289 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 290 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 291 | val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN; |
| 292 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); |
| 293 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 294 | } |
| 295 | #endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */ |
| 296 | |
| 297 | |
| 298 | static void syscon_clk_rate_set_mclk(unsigned long rate) |
| 299 | { |
| 300 | u16 val; |
| 301 | u32 reg; |
| 302 | unsigned long iflags; |
| 303 | |
| 304 | switch (rate) { |
| 305 | case 18900000: |
| 306 | val = 0x0054; |
| 307 | break; |
| 308 | case 20800000: |
| 309 | val = 0x0044; |
| 310 | break; |
| 311 | case 23100000: |
| 312 | val = 0x0043; |
| 313 | break; |
| 314 | case 26000000: |
| 315 | val = 0x0033; |
| 316 | break; |
| 317 | case 29700000: |
| 318 | val = 0x0032; |
| 319 | break; |
| 320 | case 34700000: |
| 321 | val = 0x0022; |
| 322 | break; |
| 323 | case 41600000: |
| 324 | val = 0x0021; |
| 325 | break; |
| 326 | case 52000000: |
| 327 | val = 0x0011; |
| 328 | break; |
| 329 | case 104000000: |
| 330 | val = 0x0000; |
| 331 | break; |
| 332 | default: |
| 333 | printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n", |
| 334 | rate); |
| 335 | return; |
| 336 | } |
| 337 | |
| 338 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 339 | reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & |
| 340 | ~U300_SYSCON_MMF0R_MASK; |
| 341 | writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R); |
| 342 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 343 | } |
| 344 | |
| 345 | void syscon_clk_rate_set_cpuclk(unsigned long rate) |
| 346 | { |
| 347 | u16 val; |
| 348 | unsigned long iflags; |
| 349 | |
| 350 | switch (rate) { |
| 351 | case 13000000: |
| 352 | val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER; |
| 353 | break; |
| 354 | case 52000000: |
| 355 | val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE; |
| 356 | break; |
| 357 | case 104000000: |
| 358 | val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH; |
| 359 | break; |
| 360 | case 208000000: |
| 361 | val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST; |
| 362 | break; |
| 363 | default: |
| 364 | return; |
| 365 | } |
| 366 | spin_lock_irqsave(&syscon_clkreg_lock, iflags); |
| 367 | val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) & |
| 368 | ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ; |
| 369 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 370 | spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); |
| 371 | } |
| 372 | EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk); |
| 373 | |
| 374 | void clk_disable(struct clk *clk) |
| 375 | { |
| 376 | unsigned long iflags; |
| 377 | |
| 378 | spin_lock_irqsave(&clk->lock, iflags); |
| 379 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 380 | /* some blocks lack clocking registers and cannot be disabled */ |
| 381 | if (clk->disable) |
| 382 | clk->disable(clk); |
| 383 | if (likely((u32)clk->parent)) |
| 384 | clk_disable(clk->parent); |
| 385 | } |
| 386 | #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER |
| 387 | if (unlikely(!strcmp(clk->name, "I2S0"))) |
| 388 | disable_i2s0_vcxo(); |
| 389 | if (unlikely(!strcmp(clk->name, "I2S1"))) |
| 390 | disable_i2s1_vcxo(); |
| 391 | #endif |
| 392 | spin_unlock_irqrestore(&clk->lock, iflags); |
| 393 | } |
| 394 | EXPORT_SYMBOL(clk_disable); |
| 395 | |
| 396 | int clk_enable(struct clk *clk) |
| 397 | { |
| 398 | int ret = 0; |
| 399 | unsigned long iflags; |
| 400 | |
| 401 | spin_lock_irqsave(&clk->lock, iflags); |
| 402 | if (clk->usecount++ == 0) { |
| 403 | if (likely((u32)clk->parent)) |
| 404 | ret = clk_enable(clk->parent); |
| 405 | |
| 406 | if (unlikely(ret != 0)) |
| 407 | clk->usecount--; |
| 408 | else { |
| 409 | /* remove reset line (we never enable reset again) */ |
| 410 | syscon_block_reset_disable(clk); |
| 411 | /* clocks without enable function are always on */ |
| 412 | if (clk->enable) |
| 413 | clk->enable(clk); |
| 414 | #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER |
| 415 | if (unlikely(!strcmp(clk->name, "I2S0"))) |
| 416 | enable_i2s0_vcxo(); |
| 417 | if (unlikely(!strcmp(clk->name, "I2S1"))) |
| 418 | enable_i2s1_vcxo(); |
| 419 | #endif |
| 420 | } |
| 421 | } |
| 422 | spin_unlock_irqrestore(&clk->lock, iflags); |
| 423 | return ret; |
| 424 | |
| 425 | } |
| 426 | EXPORT_SYMBOL(clk_enable); |
| 427 | |
| 428 | /* Returns the clock rate in Hz */ |
| 429 | static unsigned long clk_get_rate_cpuclk(struct clk *clk) |
| 430 | { |
| 431 | u16 val; |
| 432 | |
| 433 | val = syscon_clk_get_rate(); |
| 434 | |
| 435 | switch (val) { |
| 436 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 437 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 438 | return 13000000; |
| 439 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 440 | return 52000000; |
| 441 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 442 | return 104000000; |
| 443 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 444 | return 208000000; |
| 445 | default: |
| 446 | break; |
| 447 | } |
| 448 | return clk->rate; |
| 449 | } |
| 450 | |
| 451 | static unsigned long clk_get_rate_ahb_clk(struct clk *clk) |
| 452 | { |
| 453 | u16 val; |
| 454 | |
| 455 | val = syscon_clk_get_rate(); |
| 456 | |
| 457 | switch (val) { |
| 458 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 459 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 460 | return 6500000; |
| 461 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 462 | return 26000000; |
| 463 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 464 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 465 | return 52000000; |
| 466 | default: |
| 467 | break; |
| 468 | } |
| 469 | return clk->rate; |
| 470 | |
| 471 | } |
| 472 | |
| 473 | static unsigned long clk_get_rate_emif_clk(struct clk *clk) |
| 474 | { |
| 475 | u16 val; |
| 476 | |
| 477 | val = syscon_clk_get_rate(); |
| 478 | |
| 479 | switch (val) { |
| 480 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 481 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 482 | return 13000000; |
| 483 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 484 | return 52000000; |
| 485 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 486 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 487 | return 104000000; |
| 488 | default: |
| 489 | break; |
| 490 | } |
| 491 | return clk->rate; |
| 492 | |
| 493 | } |
| 494 | |
| 495 | static unsigned long clk_get_rate_xgamclk(struct clk *clk) |
| 496 | { |
| 497 | u16 val; |
| 498 | |
| 499 | val = syscon_clk_get_rate(); |
| 500 | |
| 501 | switch (val) { |
| 502 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 503 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 504 | return 6500000; |
| 505 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 506 | return 26000000; |
| 507 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 508 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 509 | return 52000000; |
| 510 | default: |
| 511 | break; |
| 512 | } |
| 513 | |
| 514 | return clk->rate; |
| 515 | } |
| 516 | |
| 517 | static unsigned long clk_get_rate_mclk(struct clk *clk) |
| 518 | { |
| 519 | u16 val; |
| 520 | |
| 521 | val = syscon_clk_get_rate(); |
| 522 | |
| 523 | switch (val) { |
| 524 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 525 | /* |
| 526 | * Here, the 208 MHz PLL gets shut down and the always |
| 527 | * on 13 MHz PLL used for RTC etc kicks into use |
| 528 | * instead. |
| 529 | */ |
| 530 | return 13000000; |
| 531 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 532 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 533 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 534 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 535 | { |
| 536 | /* |
| 537 | * This clock is under program control. The register is |
| 538 | * divided in two nybbles, bit 7-4 gives cycles-1 to count |
| 539 | * high, bit 3-0 gives cycles-1 to count low. Distribute |
| 540 | * these with no more than 1 cycle difference between |
| 541 | * low and high and add low and high to get the actual |
| 542 | * divisor. The base PLL is 208 MHz. Writing 0x00 will |
| 543 | * divide by 1 and 1 so the highest frequency possible |
| 544 | * is 104 MHz. |
| 545 | * |
| 546 | * e.g. 0x54 => |
| 547 | * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz |
| 548 | */ |
| 549 | u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & |
| 550 | U300_SYSCON_MMF0R_MASK; |
| 551 | switch (val) { |
| 552 | case 0x0054: |
| 553 | return 18900000; |
| 554 | case 0x0044: |
| 555 | return 20800000; |
| 556 | case 0x0043: |
| 557 | return 23100000; |
| 558 | case 0x0033: |
| 559 | return 26000000; |
| 560 | case 0x0032: |
| 561 | return 29700000; |
| 562 | case 0x0022: |
| 563 | return 34700000; |
| 564 | case 0x0021: |
| 565 | return 41600000; |
| 566 | case 0x0011: |
| 567 | return 52000000; |
| 568 | case 0x0000: |
| 569 | return 104000000; |
| 570 | default: |
| 571 | break; |
| 572 | } |
| 573 | } |
| 574 | default: |
| 575 | break; |
| 576 | } |
| 577 | |
| 578 | return clk->rate; |
| 579 | } |
| 580 | |
| 581 | static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk) |
| 582 | { |
| 583 | u16 val; |
| 584 | |
| 585 | val = syscon_clk_get_rate(); |
| 586 | |
| 587 | switch (val) { |
| 588 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: |
| 589 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: |
| 590 | return 13000000; |
| 591 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: |
| 592 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: |
| 593 | case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: |
| 594 | return 26000000; |
| 595 | default: |
| 596 | break; |
| 597 | } |
| 598 | |
| 599 | return clk->rate; |
| 600 | } |
| 601 | |
| 602 | unsigned long clk_get_rate(struct clk *clk) |
| 603 | { |
| 604 | if (clk->get_rate) |
| 605 | return clk->get_rate(clk); |
| 606 | else |
| 607 | return clk->rate; |
| 608 | } |
| 609 | EXPORT_SYMBOL(clk_get_rate); |
| 610 | |
| 611 | static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate) |
| 612 | { |
| 613 | if (rate >= 18900000) |
| 614 | return 18900000; |
| 615 | if (rate >= 20800000) |
| 616 | return 20800000; |
| 617 | if (rate >= 23100000) |
| 618 | return 23100000; |
| 619 | if (rate >= 26000000) |
| 620 | return 26000000; |
| 621 | if (rate >= 29700000) |
| 622 | return 29700000; |
| 623 | if (rate >= 34700000) |
| 624 | return 34700000; |
| 625 | if (rate >= 41600000) |
| 626 | return 41600000; |
| 627 | if (rate >= 52000000) |
| 628 | return 52000000; |
| 629 | return -EINVAL; |
| 630 | } |
| 631 | |
| 632 | static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) |
| 633 | { |
| 634 | if (rate >= 13000000) |
| 635 | return 13000000; |
| 636 | if (rate >= 52000000) |
| 637 | return 52000000; |
| 638 | if (rate >= 104000000) |
| 639 | return 104000000; |
| 640 | if (rate >= 208000000) |
| 641 | return 208000000; |
| 642 | return -EINVAL; |
| 643 | } |
| 644 | |
| 645 | /* |
| 646 | * This adjusts a requested rate to the closest exact rate |
| 647 | * a certain clock can provide. For a fixed clock it's |
| 648 | * mostly clk->rate. |
| 649 | */ |
| 650 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 651 | { |
| 652 | /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */ |
| 653 | /* Else default to fixed value */ |
| 654 | |
| 655 | if (clk->round_rate) { |
| 656 | return (long) clk->round_rate(clk, rate); |
| 657 | } else { |
| 658 | printk(KERN_ERR "clock: Failed to round rate of %s\n", |
| 659 | clk->name); |
| 660 | } |
| 661 | return (long) clk->rate; |
| 662 | } |
| 663 | EXPORT_SYMBOL(clk_round_rate); |
| 664 | |
| 665 | static int clk_set_rate_mclk(struct clk *clk, unsigned long rate) |
| 666 | { |
| 667 | syscon_clk_rate_set_mclk(clk_round_rate(clk, rate)); |
| 668 | return 0; |
| 669 | } |
| 670 | |
| 671 | static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate) |
| 672 | { |
| 673 | syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate)); |
| 674 | return 0; |
| 675 | } |
| 676 | |
| 677 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 678 | { |
| 679 | /* TODO: set for EMIFCLK and AHBCLK */ |
| 680 | /* Else assume the clock is fixed and fail */ |
| 681 | if (clk->set_rate) { |
| 682 | return clk->set_rate(clk, rate); |
| 683 | } else { |
| 684 | printk(KERN_ERR "clock: Failed to set %s to %ld hz\n", |
| 685 | clk->name, rate); |
Russell King | ed31b2d | 2009-05-31 15:08:11 +0100 | [diff] [blame] | 686 | return -EINVAL; |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 687 | } |
| 688 | } |
| 689 | EXPORT_SYMBOL(clk_set_rate); |
| 690 | |
| 691 | /* |
| 692 | * Clock definitions. The clock parents are set to respective |
| 693 | * bridge and the clock framework makes sure that the clocks have |
| 694 | * parents activated and are brought out of reset when in use. |
| 695 | * |
| 696 | * Clocks that have hw_ctrld = true are hw controlled, and the hw |
| 697 | * can by itself turn these clocks on and off. |
| 698 | * So in other words, we don't really have to care about them. |
| 699 | */ |
| 700 | |
| 701 | static struct clk amba_clk = { |
| 702 | .name = "AMBA", |
| 703 | .rate = 52000000, /* this varies! */ |
| 704 | .hw_ctrld = true, |
| 705 | .reset = false, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 706 | .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 707 | }; |
| 708 | |
| 709 | /* |
| 710 | * These blocks are connected directly to the AMBA bus |
| 711 | * with no bridge. |
| 712 | */ |
| 713 | |
| 714 | static struct clk cpu_clk = { |
| 715 | .name = "CPU", |
| 716 | .parent = &amba_clk, |
| 717 | .rate = 208000000, /* this varies! */ |
| 718 | .hw_ctrld = true, |
| 719 | .reset = true, |
| 720 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 721 | .res_mask = U300_SYSCON_RRR_CPU_RESET_EN, |
| 722 | .set_rate = clk_set_rate_cpuclk, |
| 723 | .get_rate = clk_get_rate_cpuclk, |
| 724 | .round_rate = clk_round_rate_cpuclk, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 725 | .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 726 | }; |
| 727 | |
| 728 | static struct clk nandif_clk = { |
| 729 | .name = "NANDIF", |
| 730 | .parent = &amba_clk, |
| 731 | .hw_ctrld = false, |
| 732 | .reset = true, |
| 733 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 734 | .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN, |
| 735 | .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, |
| 736 | .enable = syscon_clk_enable, |
| 737 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 738 | .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 739 | }; |
| 740 | |
| 741 | static struct clk semi_clk = { |
| 742 | .name = "SEMI", |
| 743 | .parent = &amba_clk, |
| 744 | .rate = 0, /* FIXME */ |
| 745 | /* It is not possible to reset SEMI */ |
| 746 | .hw_ctrld = false, |
| 747 | .reset = false, |
| 748 | .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, |
| 749 | .enable = syscon_clk_enable, |
| 750 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 751 | .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 752 | }; |
| 753 | |
| 754 | #ifdef CONFIG_MACH_U300_BS335 |
| 755 | static struct clk isp_clk = { |
| 756 | .name = "ISP", |
| 757 | .parent = &amba_clk, |
| 758 | .rate = 0, /* FIXME */ |
| 759 | .hw_ctrld = false, |
| 760 | .reset = true, |
| 761 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 762 | .res_mask = U300_SYSCON_RRR_ISP_RESET_EN, |
| 763 | .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN, |
| 764 | .enable = syscon_clk_enable, |
| 765 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 766 | .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 767 | }; |
| 768 | |
| 769 | static struct clk cds_clk = { |
| 770 | .name = "CDS", |
| 771 | .parent = &amba_clk, |
| 772 | .rate = 0, /* FIXME */ |
| 773 | .hw_ctrld = false, |
| 774 | .reset = true, |
| 775 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 776 | .res_mask = U300_SYSCON_RRR_CDS_RESET_EN, |
| 777 | .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN, |
| 778 | .enable = syscon_clk_enable, |
| 779 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 780 | .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 781 | }; |
| 782 | #endif |
| 783 | |
| 784 | static struct clk dma_clk = { |
| 785 | .name = "DMA", |
| 786 | .parent = &amba_clk, |
| 787 | .rate = 52000000, /* this varies! */ |
| 788 | .hw_ctrld = true, |
| 789 | .reset = true, |
| 790 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 791 | .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN, |
| 792 | .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, |
| 793 | .enable = syscon_clk_enable, |
| 794 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 795 | .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 796 | }; |
| 797 | |
| 798 | static struct clk aaif_clk = { |
| 799 | .name = "AAIF", |
| 800 | .parent = &amba_clk, |
| 801 | .rate = 52000000, /* this varies! */ |
| 802 | .hw_ctrld = true, |
| 803 | .reset = true, |
| 804 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 805 | .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN, |
| 806 | .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN, |
| 807 | .enable = syscon_clk_enable, |
| 808 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 809 | .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 810 | }; |
| 811 | |
| 812 | static struct clk apex_clk = { |
| 813 | .name = "APEX", |
| 814 | .parent = &amba_clk, |
| 815 | .rate = 0, /* FIXME */ |
| 816 | .hw_ctrld = true, |
| 817 | .reset = true, |
| 818 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 819 | .res_mask = U300_SYSCON_RRR_APEX_RESET_EN, |
| 820 | .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN, |
| 821 | .enable = syscon_clk_enable, |
| 822 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 823 | .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 824 | }; |
| 825 | |
| 826 | static struct clk video_enc_clk = { |
| 827 | .name = "VIDEO_ENC", |
| 828 | .parent = &amba_clk, |
| 829 | .rate = 208000000, /* this varies! */ |
| 830 | .hw_ctrld = false, |
| 831 | .reset = false, |
| 832 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 833 | /* This has XGAM in the name but refers to the video encoder */ |
| 834 | .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN, |
| 835 | .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN, |
| 836 | .enable = syscon_clk_enable, |
| 837 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 838 | .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 839 | }; |
| 840 | |
| 841 | static struct clk xgam_clk = { |
| 842 | .name = "XGAMCLK", |
| 843 | .parent = &amba_clk, |
| 844 | .rate = 52000000, /* this varies! */ |
| 845 | .hw_ctrld = false, |
| 846 | .reset = true, |
| 847 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 848 | .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN, |
| 849 | .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN, |
| 850 | .get_rate = clk_get_rate_xgamclk, |
| 851 | .enable = syscon_clk_enable, |
| 852 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 853 | .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 854 | }; |
| 855 | |
| 856 | /* This clock is used to activate the video encoder */ |
| 857 | static struct clk ahb_clk = { |
| 858 | .name = "AHB", |
| 859 | .parent = &amba_clk, |
| 860 | .rate = 52000000, /* this varies! */ |
| 861 | .hw_ctrld = false, /* This one is set to false due to HW bug */ |
| 862 | .reset = true, |
| 863 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 864 | .res_mask = U300_SYSCON_RRR_AHB_RESET_EN, |
| 865 | .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN, |
| 866 | .enable = syscon_clk_enable, |
| 867 | .disable = syscon_clk_disable, |
| 868 | .get_rate = clk_get_rate_ahb_clk, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 869 | .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 870 | }; |
| 871 | |
| 872 | |
| 873 | /* |
| 874 | * Clocks on the AHB bridge |
| 875 | */ |
| 876 | |
| 877 | static struct clk ahb_subsys_clk = { |
| 878 | .name = "AHB_SUBSYS", |
| 879 | .parent = &amba_clk, |
| 880 | .rate = 52000000, /* this varies! */ |
| 881 | .hw_ctrld = true, |
| 882 | .reset = false, |
| 883 | .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN, |
| 884 | .enable = syscon_clk_enable, |
| 885 | .disable = syscon_clk_disable, |
| 886 | .get_rate = clk_get_rate_ahb_clk, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 887 | .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 888 | }; |
| 889 | |
| 890 | static struct clk intcon_clk = { |
| 891 | .name = "INTCON", |
| 892 | .parent = &ahb_subsys_clk, |
| 893 | .rate = 52000000, /* this varies! */ |
| 894 | .hw_ctrld = false, |
| 895 | .reset = true, |
| 896 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 897 | .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN, |
| 898 | /* INTCON can be reset but not clock-gated */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 899 | .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock), |
| 900 | |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 901 | }; |
| 902 | |
| 903 | static struct clk mspro_clk = { |
| 904 | .name = "MSPRO", |
| 905 | .parent = &ahb_subsys_clk, |
| 906 | .rate = 0, /* FIXME */ |
| 907 | .hw_ctrld = false, |
| 908 | .reset = true, |
| 909 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 910 | .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN, |
| 911 | .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN, |
| 912 | .enable = syscon_clk_enable, |
| 913 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 914 | .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 915 | }; |
| 916 | |
| 917 | static struct clk emif_clk = { |
| 918 | .name = "EMIF", |
| 919 | .parent = &ahb_subsys_clk, |
| 920 | .rate = 104000000, /* this varies! */ |
| 921 | .hw_ctrld = false, |
| 922 | .reset = true, |
| 923 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
| 924 | .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN, |
| 925 | .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN, |
| 926 | .enable = syscon_clk_enable, |
| 927 | .disable = syscon_clk_disable, |
| 928 | .get_rate = clk_get_rate_emif_clk, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 929 | .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 930 | }; |
| 931 | |
| 932 | |
| 933 | /* |
| 934 | * Clocks on the FAST bridge |
| 935 | */ |
| 936 | static struct clk fast_clk = { |
| 937 | .name = "FAST_BRIDGE", |
| 938 | .parent = &amba_clk, |
| 939 | .rate = 13000000, /* this varies! */ |
| 940 | .hw_ctrld = true, |
| 941 | .reset = true, |
| 942 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 943 | .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE, |
| 944 | .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, |
| 945 | .enable = syscon_clk_enable, |
| 946 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 947 | .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 948 | }; |
| 949 | |
| 950 | static struct clk mmcsd_clk = { |
| 951 | .name = "MCLK", |
| 952 | .parent = &fast_clk, |
| 953 | .rate = 18900000, /* this varies! */ |
| 954 | .hw_ctrld = false, |
| 955 | .reset = true, |
| 956 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 957 | .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE, |
| 958 | .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN, |
| 959 | .get_rate = clk_get_rate_mclk, |
| 960 | .set_rate = clk_set_rate_mclk, |
| 961 | .round_rate = clk_round_rate_mclk, |
| 962 | .disable = syscon_clk_disable, |
| 963 | .enable = syscon_clk_enable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 964 | .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 965 | }; |
| 966 | |
| 967 | static struct clk i2s0_clk = { |
| 968 | .name = "i2s0", |
| 969 | .parent = &fast_clk, |
| 970 | .rate = 26000000, /* this varies! */ |
| 971 | .hw_ctrld = true, |
| 972 | .reset = true, |
| 973 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 974 | .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE, |
| 975 | .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN, |
| 976 | .enable = syscon_clk_enable, |
| 977 | .disable = syscon_clk_disable, |
| 978 | .get_rate = clk_get_rate_i2s_i2c_spi, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 979 | .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 980 | }; |
| 981 | |
| 982 | static struct clk i2s1_clk = { |
| 983 | .name = "i2s1", |
| 984 | .parent = &fast_clk, |
| 985 | .rate = 26000000, /* this varies! */ |
| 986 | .hw_ctrld = true, |
| 987 | .reset = true, |
| 988 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 989 | .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE, |
| 990 | .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN, |
| 991 | .enable = syscon_clk_enable, |
| 992 | .disable = syscon_clk_disable, |
| 993 | .get_rate = clk_get_rate_i2s_i2c_spi, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 994 | .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 995 | }; |
| 996 | |
| 997 | static struct clk i2c0_clk = { |
| 998 | .name = "I2C0", |
| 999 | .parent = &fast_clk, |
| 1000 | .rate = 26000000, /* this varies! */ |
| 1001 | .hw_ctrld = false, |
| 1002 | .reset = true, |
| 1003 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 1004 | .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE, |
| 1005 | .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN, |
| 1006 | .enable = syscon_clk_enable, |
| 1007 | .disable = syscon_clk_disable, |
| 1008 | .get_rate = clk_get_rate_i2s_i2c_spi, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1009 | .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1010 | }; |
| 1011 | |
| 1012 | static struct clk i2c1_clk = { |
| 1013 | .name = "I2C1", |
| 1014 | .parent = &fast_clk, |
| 1015 | .rate = 26000000, /* this varies! */ |
| 1016 | .hw_ctrld = false, |
| 1017 | .reset = true, |
| 1018 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 1019 | .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE, |
| 1020 | .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN, |
| 1021 | .enable = syscon_clk_enable, |
| 1022 | .disable = syscon_clk_disable, |
| 1023 | .get_rate = clk_get_rate_i2s_i2c_spi, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1024 | .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1025 | }; |
| 1026 | |
| 1027 | static struct clk spi_clk = { |
| 1028 | .name = "SPI", |
| 1029 | .parent = &fast_clk, |
| 1030 | .rate = 26000000, /* this varies! */ |
| 1031 | .hw_ctrld = false, |
| 1032 | .reset = true, |
| 1033 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 1034 | .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE, |
| 1035 | .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN, |
| 1036 | .enable = syscon_clk_enable, |
| 1037 | .disable = syscon_clk_disable, |
| 1038 | .get_rate = clk_get_rate_i2s_i2c_spi, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1039 | .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1040 | }; |
| 1041 | |
| 1042 | #ifdef CONFIG_MACH_U300_BS335 |
| 1043 | static struct clk uart1_clk = { |
| 1044 | .name = "UART1", |
| 1045 | .parent = &fast_clk, |
| 1046 | .rate = 13000000, |
| 1047 | .hw_ctrld = false, |
| 1048 | .reset = true, |
| 1049 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
| 1050 | .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE, |
| 1051 | .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, |
| 1052 | .enable = syscon_clk_enable, |
| 1053 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1054 | .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1055 | }; |
| 1056 | #endif |
| 1057 | |
| 1058 | |
| 1059 | /* |
| 1060 | * Clocks on the SLOW bridge |
| 1061 | */ |
| 1062 | static struct clk slow_clk = { |
| 1063 | .name = "SLOW_BRIDGE", |
| 1064 | .parent = &amba_clk, |
| 1065 | .rate = 13000000, |
| 1066 | .hw_ctrld = true, |
| 1067 | .reset = true, |
| 1068 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1069 | .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN, |
| 1070 | .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, |
| 1071 | .enable = syscon_clk_enable, |
| 1072 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1073 | .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1074 | }; |
| 1075 | |
| 1076 | /* TODO: implement SYSCON clock? */ |
| 1077 | |
| 1078 | static struct clk wdog_clk = { |
| 1079 | .name = "WDOG", |
| 1080 | .parent = &slow_clk, |
| 1081 | .hw_ctrld = false, |
| 1082 | .rate = 32768, |
| 1083 | .reset = false, |
| 1084 | /* This is always on, cannot be enabled/disabled or reset */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1085 | .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1086 | }; |
| 1087 | |
| 1088 | /* This one is hardwired to PLL13 */ |
| 1089 | static struct clk uart_clk = { |
| 1090 | .name = "UARTCLK", |
| 1091 | .parent = &slow_clk, |
| 1092 | .rate = 13000000, |
| 1093 | .hw_ctrld = false, |
| 1094 | .reset = true, |
| 1095 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1096 | .res_mask = U300_SYSCON_RSR_UART_RESET_EN, |
| 1097 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, |
| 1098 | .enable = syscon_clk_enable, |
| 1099 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1100 | .lock = __SPIN_LOCK_UNLOCKED(uart_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1101 | }; |
| 1102 | |
| 1103 | static struct clk keypad_clk = { |
| 1104 | .name = "KEYPAD", |
| 1105 | .parent = &slow_clk, |
| 1106 | .rate = 32768, |
| 1107 | .hw_ctrld = false, |
| 1108 | .reset = true, |
| 1109 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1110 | .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN, |
| 1111 | .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN, |
| 1112 | .enable = syscon_clk_enable, |
| 1113 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1114 | .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1115 | }; |
| 1116 | |
| 1117 | static struct clk gpio_clk = { |
| 1118 | .name = "GPIO", |
| 1119 | .parent = &slow_clk, |
| 1120 | .rate = 13000000, |
| 1121 | .hw_ctrld = true, |
| 1122 | .reset = true, |
| 1123 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1124 | .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN, |
| 1125 | .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, |
| 1126 | .enable = syscon_clk_enable, |
| 1127 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1128 | .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1129 | }; |
| 1130 | |
| 1131 | static struct clk rtc_clk = { |
| 1132 | .name = "RTC", |
| 1133 | .parent = &slow_clk, |
| 1134 | .rate = 32768, |
| 1135 | .hw_ctrld = true, |
| 1136 | .reset = true, |
| 1137 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1138 | .res_mask = U300_SYSCON_RSR_RTC_RESET_EN, |
| 1139 | /* This clock is always on, cannot be enabled/disabled */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1140 | .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1141 | }; |
| 1142 | |
| 1143 | static struct clk bustr_clk = { |
| 1144 | .name = "BUSTR", |
| 1145 | .parent = &slow_clk, |
| 1146 | .rate = 13000000, |
| 1147 | .hw_ctrld = true, |
| 1148 | .reset = true, |
| 1149 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1150 | .res_mask = U300_SYSCON_RSR_BTR_RESET_EN, |
| 1151 | .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN, |
| 1152 | .enable = syscon_clk_enable, |
| 1153 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1154 | .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1155 | }; |
| 1156 | |
| 1157 | static struct clk evhist_clk = { |
| 1158 | .name = "EVHIST", |
| 1159 | .parent = &slow_clk, |
| 1160 | .rate = 13000000, |
| 1161 | .hw_ctrld = true, |
| 1162 | .reset = true, |
| 1163 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1164 | .res_mask = U300_SYSCON_RSR_EH_RESET_EN, |
| 1165 | .clk_val = U300_SYSCON_SBCER_EH_CLK_EN, |
| 1166 | .enable = syscon_clk_enable, |
| 1167 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1168 | .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1169 | }; |
| 1170 | |
| 1171 | static struct clk timer_clk = { |
| 1172 | .name = "TIMER", |
| 1173 | .parent = &slow_clk, |
| 1174 | .rate = 13000000, |
| 1175 | .hw_ctrld = true, |
| 1176 | .reset = true, |
| 1177 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1178 | .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN, |
| 1179 | .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, |
| 1180 | .enable = syscon_clk_enable, |
| 1181 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1182 | .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1183 | }; |
| 1184 | |
| 1185 | static struct clk app_timer_clk = { |
| 1186 | .name = "TIMER_APP", |
| 1187 | .parent = &slow_clk, |
| 1188 | .rate = 13000000, |
| 1189 | .hw_ctrld = true, |
| 1190 | .reset = true, |
| 1191 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1192 | .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN, |
| 1193 | .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, |
| 1194 | .enable = syscon_clk_enable, |
| 1195 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1196 | .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1197 | }; |
| 1198 | |
| 1199 | #ifdef CONFIG_MACH_U300_BS335 |
| 1200 | static struct clk ppm_clk = { |
| 1201 | .name = "PPM", |
| 1202 | .parent = &slow_clk, |
| 1203 | .rate = 0, /* FIXME */ |
| 1204 | .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */ |
| 1205 | .reset = true, |
| 1206 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
| 1207 | .res_mask = U300_SYSCON_RSR_PPM_RESET_EN, |
| 1208 | .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN, |
| 1209 | .enable = syscon_clk_enable, |
| 1210 | .disable = syscon_clk_disable, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1211 | .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1212 | }; |
| 1213 | #endif |
| 1214 | |
| 1215 | #define DEF_LOOKUP(devid, clkref) \ |
| 1216 | { \ |
| 1217 | .dev_id = devid, \ |
| 1218 | .clk = clkref, \ |
| 1219 | } |
| 1220 | |
| 1221 | /* |
| 1222 | * Here we only define clocks that are meaningful to |
| 1223 | * look up through clockdevice. |
| 1224 | */ |
| 1225 | static struct clk_lookup lookups[] = { |
| 1226 | /* Connected directly to the AMBA bus */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1227 | DEF_LOOKUP("amba", &amba_clk), |
| 1228 | DEF_LOOKUP("cpu", &cpu_clk), |
| 1229 | DEF_LOOKUP("fsmc", &nandif_clk), |
| 1230 | DEF_LOOKUP("semi", &semi_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1231 | #ifdef CONFIG_MACH_U300_BS335 |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1232 | DEF_LOOKUP("isp", &isp_clk), |
| 1233 | DEF_LOOKUP("cds", &cds_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1234 | #endif |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1235 | DEF_LOOKUP("dma", &dma_clk), |
| 1236 | DEF_LOOKUP("msl", &aaif_clk), |
| 1237 | DEF_LOOKUP("apex", &apex_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1238 | DEF_LOOKUP("video_enc", &video_enc_clk), |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1239 | DEF_LOOKUP("xgam", &xgam_clk), |
| 1240 | DEF_LOOKUP("ahb", &ahb_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1241 | /* AHB bridge clocks */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1242 | DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk), |
| 1243 | DEF_LOOKUP("intcon", &intcon_clk), |
| 1244 | DEF_LOOKUP("mspro", &mspro_clk), |
| 1245 | DEF_LOOKUP("pl172", &emif_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1246 | /* FAST bridge clocks */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1247 | DEF_LOOKUP("fast", &fast_clk), |
| 1248 | DEF_LOOKUP("mmci", &mmcsd_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1249 | /* |
| 1250 | * The .0 and .1 identifiers on these comes from the platform device |
| 1251 | * .id field and are assigned when the platform devices are registered. |
| 1252 | */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1253 | DEF_LOOKUP("i2s.0", &i2s0_clk), |
| 1254 | DEF_LOOKUP("i2s.1", &i2s1_clk), |
| 1255 | DEF_LOOKUP("stu300.0", &i2c0_clk), |
| 1256 | DEF_LOOKUP("stu300.1", &i2c1_clk), |
| 1257 | DEF_LOOKUP("pl022", &spi_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1258 | #ifdef CONFIG_MACH_U300_BS335 |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1259 | DEF_LOOKUP("uart1", &uart1_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1260 | #endif |
| 1261 | /* SLOW bridge clocks */ |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1262 | DEF_LOOKUP("slow", &slow_clk), |
| 1263 | DEF_LOOKUP("coh901327_wdog", &wdog_clk), |
| 1264 | DEF_LOOKUP("uart0", &uart_clk), |
| 1265 | DEF_LOOKUP("apptimer", &app_timer_clk), |
| 1266 | DEF_LOOKUP("coh901461-keypad", &keypad_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1267 | DEF_LOOKUP("u300-gpio", &gpio_clk), |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1268 | DEF_LOOKUP("rtc-coh901331", &rtc_clk), |
| 1269 | DEF_LOOKUP("bustr", &bustr_clk), |
| 1270 | DEF_LOOKUP("evhist", &evhist_clk), |
| 1271 | DEF_LOOKUP("timer", &timer_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1272 | #ifdef CONFIG_MACH_U300_BS335 |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1273 | DEF_LOOKUP("ppm", &ppm_clk), |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1274 | #endif |
| 1275 | }; |
| 1276 | |
| 1277 | static void __init clk_register(void) |
| 1278 | { |
| 1279 | int i; |
| 1280 | |
| 1281 | /* Register the lookups */ |
| 1282 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1283 | clkdev_add(&lookups[i]); |
| 1284 | } |
| 1285 | |
| 1286 | /* |
| 1287 | * These are the clocks for cells registered as primecell drivers |
| 1288 | * on the AMBA bus. These must be on during AMBA device registration |
| 1289 | * since the bus probe will attempt to read magic configuration |
| 1290 | * registers for these devices. If they are deactivated these probes |
| 1291 | * will fail. |
| 1292 | * |
| 1293 | * |
| 1294 | * Please note that on emif, both RAM and NAND is connected in dual |
| 1295 | * RAM phones. On single RAM phones, ram is on semi and NAND on emif. |
| 1296 | * |
| 1297 | */ |
| 1298 | void u300_clock_primecells(void) |
| 1299 | { |
| 1300 | clk_enable(&intcon_clk); |
| 1301 | clk_enable(&uart_clk); |
| 1302 | #ifdef CONFIG_MACH_U300_BS335 |
| 1303 | clk_enable(&uart1_clk); |
| 1304 | #endif |
| 1305 | clk_enable(&spi_clk); |
| 1306 | |
| 1307 | clk_enable(&mmcsd_clk); |
| 1308 | |
| 1309 | } |
| 1310 | EXPORT_SYMBOL(u300_clock_primecells); |
| 1311 | |
| 1312 | void u300_unclock_primecells(void) |
| 1313 | { |
| 1314 | |
| 1315 | clk_disable(&intcon_clk); |
| 1316 | clk_disable(&uart_clk); |
| 1317 | #ifdef CONFIG_MACH_U300_BS335 |
| 1318 | clk_disable(&uart1_clk); |
| 1319 | #endif |
| 1320 | clk_disable(&spi_clk); |
| 1321 | clk_disable(&mmcsd_clk); |
| 1322 | |
| 1323 | } |
| 1324 | EXPORT_SYMBOL(u300_unclock_primecells); |
| 1325 | |
| 1326 | /* |
| 1327 | * The interrupt controller is enabled before the clock API is registered. |
| 1328 | */ |
| 1329 | void u300_enable_intcon_clock(void) |
| 1330 | { |
| 1331 | clk_enable(&intcon_clk); |
| 1332 | } |
| 1333 | EXPORT_SYMBOL(u300_enable_intcon_clock); |
| 1334 | |
| 1335 | /* |
| 1336 | * The timer is enabled before the clock API is registered. |
| 1337 | */ |
| 1338 | void u300_enable_timer_clock(void) |
| 1339 | { |
| 1340 | clk_enable(&app_timer_clk); |
| 1341 | } |
| 1342 | EXPORT_SYMBOL(u300_enable_timer_clock); |
| 1343 | |
| 1344 | #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) |
| 1345 | /* |
| 1346 | * The following makes it possible to view the status (especially |
| 1347 | * reference count and reset status) for the clocks in the platform |
| 1348 | * by looking into the special file <debugfs>/u300_clocks |
| 1349 | */ |
| 1350 | |
| 1351 | /* A list of all clocks in the platform */ |
| 1352 | static struct clk *clks[] = { |
| 1353 | /* Top node clock for the AMBA bus */ |
| 1354 | &amba_clk, |
| 1355 | /* Connected directly to the AMBA bus */ |
| 1356 | &cpu_clk, |
| 1357 | &nandif_clk, |
| 1358 | &semi_clk, |
| 1359 | #ifdef CONFIG_MACH_U300_BS335 |
| 1360 | &isp_clk, |
| 1361 | &cds_clk, |
| 1362 | #endif |
| 1363 | &dma_clk, |
| 1364 | &aaif_clk, |
| 1365 | &apex_clk, |
| 1366 | &video_enc_clk, |
| 1367 | &xgam_clk, |
| 1368 | &ahb_clk, |
| 1369 | |
| 1370 | /* AHB bridge clocks */ |
| 1371 | &ahb_subsys_clk, |
| 1372 | &intcon_clk, |
| 1373 | &mspro_clk, |
| 1374 | &emif_clk, |
| 1375 | /* FAST bridge clocks */ |
| 1376 | &fast_clk, |
| 1377 | &mmcsd_clk, |
| 1378 | &i2s0_clk, |
| 1379 | &i2s1_clk, |
| 1380 | &i2c0_clk, |
| 1381 | &i2c1_clk, |
| 1382 | &spi_clk, |
| 1383 | #ifdef CONFIG_MACH_U300_BS335 |
| 1384 | &uart1_clk, |
| 1385 | #endif |
| 1386 | /* SLOW bridge clocks */ |
| 1387 | &slow_clk, |
| 1388 | &wdog_clk, |
| 1389 | &uart_clk, |
| 1390 | &app_timer_clk, |
| 1391 | &keypad_clk, |
| 1392 | &gpio_clk, |
| 1393 | &rtc_clk, |
| 1394 | &bustr_clk, |
| 1395 | &evhist_clk, |
| 1396 | &timer_clk, |
| 1397 | #ifdef CONFIG_MACH_U300_BS335 |
| 1398 | &ppm_clk, |
| 1399 | #endif |
| 1400 | }; |
| 1401 | |
| 1402 | static int u300_clocks_show(struct seq_file *s, void *data) |
| 1403 | { |
| 1404 | struct clk *clk; |
| 1405 | int i; |
| 1406 | |
| 1407 | seq_printf(s, "CLOCK DEVICE RESET STATE\t" \ |
| 1408 | "ACTIVE\tUSERS\tHW CTRL FREQ\n"); |
| 1409 | seq_printf(s, "---------------------------------------------" \ |
| 1410 | "-----------------------------------------\n"); |
| 1411 | for (i = 0; i < ARRAY_SIZE(clks); i++) { |
| 1412 | clk = clks[i]; |
| 1413 | if (clk != ERR_PTR(-ENOENT)) { |
| 1414 | /* Format clock and device name nicely */ |
| 1415 | char cdp[33]; |
| 1416 | int chars; |
| 1417 | |
| 1418 | chars = snprintf(&cdp[0], 17, "%s", clk->name); |
| 1419 | while (chars < 16) { |
| 1420 | cdp[chars] = ' '; |
| 1421 | chars++; |
| 1422 | } |
| 1423 | chars = snprintf(&cdp[16], 17, "%s", clk->dev ? |
| 1424 | dev_name(clk->dev) : "N/A"); |
| 1425 | while (chars < 16) { |
| 1426 | cdp[chars+16] = ' '; |
| 1427 | chars++; |
| 1428 | } |
| 1429 | cdp[32] = '\0'; |
| 1430 | if (clk->get_rate) |
| 1431 | seq_printf(s, |
| 1432 | "%s%s\t%s\t%d\t%s\t%lu Hz\n", |
| 1433 | &cdp[0], |
| 1434 | clk->reset ? |
| 1435 | "ASSERTED" : "RELEASED", |
| 1436 | clk->usecount ? "ON" : "OFF", |
| 1437 | clk->usecount, |
| 1438 | clk->hw_ctrld ? "YES" : "NO ", |
| 1439 | clk->get_rate(clk)); |
| 1440 | else |
| 1441 | seq_printf(s, |
| 1442 | "%s%s\t%s\t%d\t%s\t" \ |
| 1443 | "(unknown rate)\n", |
| 1444 | &cdp[0], |
| 1445 | clk->reset ? |
| 1446 | "ASSERTED" : "RELEASED", |
| 1447 | clk->usecount ? "ON" : "OFF", |
| 1448 | clk->usecount, |
| 1449 | clk->hw_ctrld ? "YES" : "NO "); |
| 1450 | } |
| 1451 | } |
| 1452 | return 0; |
| 1453 | } |
| 1454 | |
| 1455 | static int u300_clocks_open(struct inode *inode, struct file *file) |
| 1456 | { |
| 1457 | return single_open(file, u300_clocks_show, NULL); |
| 1458 | } |
| 1459 | |
| 1460 | static const struct file_operations u300_clocks_operations = { |
| 1461 | .open = u300_clocks_open, |
| 1462 | .read = seq_read, |
| 1463 | .llseek = seq_lseek, |
| 1464 | .release = single_release, |
| 1465 | }; |
| 1466 | |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1467 | static int __init init_clk_read_debugfs(void) |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1468 | { |
| 1469 | /* Expose a simple debugfs interface to view all clocks */ |
| 1470 | (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO, |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1471 | NULL, NULL, |
| 1472 | &u300_clocks_operations); |
| 1473 | return 0; |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1474 | } |
Linus Walleij | 4ebfc3d | 2009-07-02 00:27:57 +0100 | [diff] [blame] | 1475 | /* |
| 1476 | * This needs to come in after the core_initcall() for the |
| 1477 | * overall clocks, because debugfs is not available until |
| 1478 | * the subsystems come up. |
| 1479 | */ |
| 1480 | module_init(init_clk_read_debugfs); |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1481 | #endif |
| 1482 | |
| 1483 | static int __init u300_clock_init(void) |
| 1484 | { |
| 1485 | u16 val; |
| 1486 | |
| 1487 | /* |
| 1488 | * FIXME: shall all this powermanagement stuff really live here??? |
| 1489 | */ |
| 1490 | |
| 1491 | /* Set system to run at PLL208, max performance, a known state. */ |
| 1492 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 1493 | val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; |
| 1494 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); |
| 1495 | /* Wait for the PLL208 to lock if not locked in yet */ |
| 1496 | while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & |
| 1497 | U300_SYSCON_CSR_PLL208_LOCK_IND)); |
| 1498 | |
| 1499 | /* Power management enable */ |
| 1500 | val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); |
| 1501 | val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; |
| 1502 | writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR); |
| 1503 | |
| 1504 | clk_register(); |
| 1505 | |
Linus Walleij | cd27e48 | 2009-04-23 10:21:30 +0100 | [diff] [blame] | 1506 | /* |
| 1507 | * Some of these may be on when we boot the system so make sure they |
| 1508 | * are turned OFF. |
| 1509 | */ |
| 1510 | syscon_block_reset_enable(&timer_clk); |
| 1511 | timer_clk.disable(&timer_clk); |
| 1512 | |
| 1513 | /* |
| 1514 | * These shall be turned on by default when we boot the system |
| 1515 | * so make sure they are ON. (Adding CPU here is a bit too much.) |
| 1516 | * These clocks will be claimed by drivers later. |
| 1517 | */ |
| 1518 | syscon_block_reset_disable(&semi_clk); |
| 1519 | syscon_block_reset_disable(&emif_clk); |
| 1520 | semi_clk.enable(&semi_clk); |
| 1521 | emif_clk.enable(&emif_clk); |
| 1522 | |
| 1523 | return 0; |
| 1524 | } |
| 1525 | /* initialize clocking early to be available later in the boot */ |
| 1526 | core_initcall(u300_clock_init); |