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Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -07001/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
mark gross98bcef52008-02-23 15:23:35 -080017 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070021 *
Suresh Siddhae61d98d2008-07-10 11:16:35 -070022 * This file implements early detection/parsing of Remapping Devices
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070023 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
24 * tables.
Suresh Siddhae61d98d2008-07-10 11:16:35 -070025 *
26 * These routines are used by both DMA-remapping and Interrupt-remapping
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070027 */
28
Donald Dutilee9071b02012-06-08 17:13:11 -040029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt /* has to precede printk.h */
30
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070031#include <linux/pci.h>
32#include <linux/dmar.h>
Kay, Allen M38717942008-09-09 18:37:29 +030033#include <linux/iova.h>
34#include <linux/intel-iommu.h>
Suresh Siddhafe962e92008-07-10 11:16:42 -070035#include <linux/timer.h>
Suresh Siddha0ac24912009-03-16 17:04:54 -070036#include <linux/irq.h>
37#include <linux/interrupt.h>
Shane Wang69575d32009-09-01 18:25:07 -070038#include <linux/tboot.h>
Len Browneb27cae2009-07-06 23:40:19 -040039#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Suresh Siddha8a8f4222012-03-30 11:47:08 -070041#include <asm/irq_remapping.h>
Konrad Rzeszutek Wilk4db77ff2010-08-26 13:58:04 -040042#include <asm/iommu_table.h>
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070043
Joerg Roedel078e1ee2012-09-26 12:44:43 +020044#include "irq_remapping.h"
45
Jiang Liu3a5670e2014-02-19 14:07:33 +080046/*
47 * Assumptions:
48 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
49 * before IO devices managed by that unit.
50 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
51 * after IO devices managed by that unit.
52 * 3) Hotplug events are rare.
53 *
54 * Locking rules for DMA and interrupt remapping related global data structures:
55 * 1) Use dmar_global_lock in process context
56 * 2) Use RCU in interrupt context
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070057 */
Jiang Liu3a5670e2014-02-19 14:07:33 +080058DECLARE_RWSEM(dmar_global_lock);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070059LIST_HEAD(dmar_drhd_units);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070060
Suresh Siddha41750d32011-08-23 17:05:18 -070061struct acpi_table_header * __initdata dmar_tbl;
Yinghai Lu8e1568f2009-02-11 01:06:59 -080062static acpi_size dmar_tbl_size;
Jiang Liu2e455282014-02-19 14:07:36 +080063static int dmar_dev_scope_status = 1;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070064
Jiang Liu694835d2014-01-06 14:18:16 +080065static int alloc_iommu(struct dmar_drhd_unit *drhd);
Jiang Liua868e6b2014-01-06 14:18:20 +080066static void free_iommu(struct intel_iommu *iommu);
Jiang Liu694835d2014-01-06 14:18:16 +080067
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070068static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
69{
70 /*
71 * add INCLUDE_ALL at the tail, so scan the list will find it at
72 * the very end.
73 */
74 if (drhd->include_all)
Jiang Liu0e242612014-02-19 14:07:34 +080075 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070076 else
Jiang Liu0e242612014-02-19 14:07:34 +080077 list_add_rcu(&drhd->list, &dmar_drhd_units);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070078}
79
Jiang Liubb3a6b72014-02-19 14:07:24 +080080void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070081{
82 struct acpi_dmar_device_scope *scope;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070083
84 *cnt = 0;
85 while (start < end) {
86 scope = start;
David Woodhouse07cb52f2014-03-07 14:39:27 +000087 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ACPI ||
88 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070089 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
90 (*cnt)++;
Linn Crosettoae3e7f32013-04-23 12:26:45 -060091 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
92 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
Donald Dutilee9071b02012-06-08 17:13:11 -040093 pr_warn("Unsupported device scope\n");
Yinghai Lu5715f0f2010-04-08 19:58:22 +010094 }
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070095 start += scope->length;
96 }
97 if (*cnt == 0)
Jiang Liubb3a6b72014-02-19 14:07:24 +080098 return NULL;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070099
David Woodhouse832bd852014-03-07 15:08:36 +0000100 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
Jiang Liubb3a6b72014-02-19 14:07:24 +0800101}
102
David Woodhouse832bd852014-03-07 15:08:36 +0000103void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
Jiang Liuada4d4b2014-01-06 14:18:09 +0800104{
Jiang Liub683b232014-02-19 14:07:32 +0800105 int i;
David Woodhouse832bd852014-03-07 15:08:36 +0000106 struct device *tmp_dev;
Jiang Liub683b232014-02-19 14:07:32 +0800107
Jiang Liuada4d4b2014-01-06 14:18:09 +0800108 if (*devices && *cnt) {
Jiang Liub683b232014-02-19 14:07:32 +0800109 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
David Woodhouse832bd852014-03-07 15:08:36 +0000110 put_device(tmp_dev);
Jiang Liuada4d4b2014-01-06 14:18:09 +0800111 kfree(*devices);
Jiang Liuada4d4b2014-01-06 14:18:09 +0800112 }
Jiang Liu0e242612014-02-19 14:07:34 +0800113
114 *devices = NULL;
115 *cnt = 0;
Jiang Liuada4d4b2014-01-06 14:18:09 +0800116}
117
Jiang Liu59ce0512014-02-19 14:07:35 +0800118/* Optimize out kzalloc()/kfree() for normal cases */
119static char dmar_pci_notify_info_buf[64];
120
121static struct dmar_pci_notify_info *
122dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
123{
124 int level = 0;
125 size_t size;
126 struct pci_dev *tmp;
127 struct dmar_pci_notify_info *info;
128
129 BUG_ON(dev->is_virtfn);
130
131 /* Only generate path[] for device addition event */
132 if (event == BUS_NOTIFY_ADD_DEVICE)
133 for (tmp = dev; tmp; tmp = tmp->bus->self)
134 level++;
135
136 size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path);
137 if (size <= sizeof(dmar_pci_notify_info_buf)) {
138 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
139 } else {
140 info = kzalloc(size, GFP_KERNEL);
141 if (!info) {
142 pr_warn("Out of memory when allocating notify_info "
143 "for %s.\n", pci_name(dev));
Jiang Liu2e455282014-02-19 14:07:36 +0800144 if (dmar_dev_scope_status == 0)
145 dmar_dev_scope_status = -ENOMEM;
Jiang Liu59ce0512014-02-19 14:07:35 +0800146 return NULL;
147 }
148 }
149
150 info->event = event;
151 info->dev = dev;
152 info->seg = pci_domain_nr(dev->bus);
153 info->level = level;
154 if (event == BUS_NOTIFY_ADD_DEVICE) {
Jiang Liu5ae05662014-04-15 10:35:35 +0800155 for (tmp = dev; tmp; tmp = tmp->bus->self) {
156 level--;
Jiang Liu59ce0512014-02-19 14:07:35 +0800157 info->path[level].device = PCI_SLOT(tmp->devfn);
158 info->path[level].function = PCI_FUNC(tmp->devfn);
159 if (pci_is_root_bus(tmp->bus))
160 info->bus = tmp->bus->number;
161 }
162 }
163
164 return info;
165}
166
167static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
168{
169 if ((void *)info != dmar_pci_notify_info_buf)
170 kfree(info);
171}
172
173static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
174 struct acpi_dmar_pci_path *path, int count)
175{
176 int i;
177
178 if (info->bus != bus)
179 return false;
180 if (info->level != count)
181 return false;
182
183 for (i = 0; i < count; i++) {
184 if (path[i].device != info->path[i].device ||
185 path[i].function != info->path[i].function)
186 return false;
187 }
188
189 return true;
190}
191
192/* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
193int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
194 void *start, void*end, u16 segment,
David Woodhouse832bd852014-03-07 15:08:36 +0000195 struct dmar_dev_scope *devices,
196 int devices_cnt)
Jiang Liu59ce0512014-02-19 14:07:35 +0800197{
198 int i, level;
David Woodhouse832bd852014-03-07 15:08:36 +0000199 struct device *tmp, *dev = &info->dev->dev;
Jiang Liu59ce0512014-02-19 14:07:35 +0800200 struct acpi_dmar_device_scope *scope;
201 struct acpi_dmar_pci_path *path;
202
203 if (segment != info->seg)
204 return 0;
205
206 for (; start < end; start += scope->length) {
207 scope = start;
208 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
209 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
210 continue;
211
212 path = (struct acpi_dmar_pci_path *)(scope + 1);
213 level = (scope->length - sizeof(*scope)) / sizeof(*path);
214 if (!dmar_match_pci_path(info, scope->bus, path, level))
215 continue;
216
217 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT) ^
David Woodhouse832bd852014-03-07 15:08:36 +0000218 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL)) {
Jiang Liu59ce0512014-02-19 14:07:35 +0800219 pr_warn("Device scope type does not match for %s\n",
David Woodhouse832bd852014-03-07 15:08:36 +0000220 pci_name(info->dev));
Jiang Liu59ce0512014-02-19 14:07:35 +0800221 return -EINVAL;
222 }
223
224 for_each_dev_scope(devices, devices_cnt, i, tmp)
225 if (tmp == NULL) {
David Woodhouse832bd852014-03-07 15:08:36 +0000226 devices[i].bus = info->dev->bus->number;
227 devices[i].devfn = info->dev->devfn;
228 rcu_assign_pointer(devices[i].dev,
229 get_device(dev));
Jiang Liu59ce0512014-02-19 14:07:35 +0800230 return 1;
231 }
232 BUG_ON(i >= devices_cnt);
233 }
234
235 return 0;
236}
237
238int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
David Woodhouse832bd852014-03-07 15:08:36 +0000239 struct dmar_dev_scope *devices, int count)
Jiang Liu59ce0512014-02-19 14:07:35 +0800240{
241 int index;
David Woodhouse832bd852014-03-07 15:08:36 +0000242 struct device *tmp;
Jiang Liu59ce0512014-02-19 14:07:35 +0800243
244 if (info->seg != segment)
245 return 0;
246
247 for_each_active_dev_scope(devices, count, index, tmp)
David Woodhouse832bd852014-03-07 15:08:36 +0000248 if (tmp == &info->dev->dev) {
249 rcu_assign_pointer(devices[index].dev, NULL);
Jiang Liu59ce0512014-02-19 14:07:35 +0800250 synchronize_rcu();
David Woodhouse832bd852014-03-07 15:08:36 +0000251 put_device(tmp);
Jiang Liu59ce0512014-02-19 14:07:35 +0800252 return 1;
253 }
254
255 return 0;
256}
257
258static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
259{
260 int ret = 0;
261 struct dmar_drhd_unit *dmaru;
262 struct acpi_dmar_hardware_unit *drhd;
263
264 for_each_drhd_unit(dmaru) {
265 if (dmaru->include_all)
266 continue;
267
268 drhd = container_of(dmaru->hdr,
269 struct acpi_dmar_hardware_unit, header);
270 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
271 ((void *)drhd) + drhd->header.length,
272 dmaru->segment,
273 dmaru->devices, dmaru->devices_cnt);
274 if (ret != 0)
275 break;
276 }
277 if (ret >= 0)
278 ret = dmar_iommu_notify_scope_dev(info);
Jiang Liu2e455282014-02-19 14:07:36 +0800279 if (ret < 0 && dmar_dev_scope_status == 0)
280 dmar_dev_scope_status = ret;
Jiang Liu59ce0512014-02-19 14:07:35 +0800281
282 return ret;
283}
284
285static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
286{
287 struct dmar_drhd_unit *dmaru;
288
289 for_each_drhd_unit(dmaru)
290 if (dmar_remove_dev_scope(info, dmaru->segment,
291 dmaru->devices, dmaru->devices_cnt))
292 break;
293 dmar_iommu_notify_scope_dev(info);
294}
295
296static int dmar_pci_bus_notifier(struct notifier_block *nb,
297 unsigned long action, void *data)
298{
299 struct pci_dev *pdev = to_pci_dev(data);
300 struct dmar_pci_notify_info *info;
301
302 /* Only care about add/remove events for physical functions */
303 if (pdev->is_virtfn)
304 return NOTIFY_DONE;
305 if (action != BUS_NOTIFY_ADD_DEVICE && action != BUS_NOTIFY_DEL_DEVICE)
306 return NOTIFY_DONE;
307
308 info = dmar_alloc_pci_notify_info(pdev, action);
309 if (!info)
310 return NOTIFY_DONE;
311
312 down_write(&dmar_global_lock);
313 if (action == BUS_NOTIFY_ADD_DEVICE)
314 dmar_pci_bus_add_dev(info);
315 else if (action == BUS_NOTIFY_DEL_DEVICE)
316 dmar_pci_bus_del_dev(info);
317 up_write(&dmar_global_lock);
318
319 dmar_free_pci_notify_info(info);
320
321 return NOTIFY_OK;
322}
323
324static struct notifier_block dmar_pci_bus_nb = {
325 .notifier_call = dmar_pci_bus_notifier,
326 .priority = INT_MIN,
327};
328
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700329/**
330 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
331 * structure which uniquely represent one DMA remapping hardware unit
332 * present in the platform
333 */
334static int __init
335dmar_parse_one_drhd(struct acpi_dmar_header *header)
336{
337 struct acpi_dmar_hardware_unit *drhd;
338 struct dmar_drhd_unit *dmaru;
339 int ret = 0;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700340
David Woodhousee523b382009-04-10 22:27:48 -0700341 drhd = (struct acpi_dmar_hardware_unit *)header;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700342 dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL);
343 if (!dmaru)
344 return -ENOMEM;
345
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700346 dmaru->hdr = header;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700347 dmaru->reg_base_addr = drhd->address;
David Woodhouse276dbf992009-04-04 01:45:37 +0100348 dmaru->segment = drhd->segment;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700349 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
David Woodhouse07cb52f2014-03-07 14:39:27 +0000350 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
351 ((void *)drhd) + drhd->header.length,
352 &dmaru->devices_cnt);
353 if (dmaru->devices_cnt && dmaru->devices == NULL) {
354 kfree(dmaru);
355 return -ENOMEM;
Jiang Liu2e455282014-02-19 14:07:36 +0800356 }
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700357
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700358 ret = alloc_iommu(dmaru);
359 if (ret) {
David Woodhouse07cb52f2014-03-07 14:39:27 +0000360 dmar_free_dev_scope(&dmaru->devices,
361 &dmaru->devices_cnt);
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700362 kfree(dmaru);
363 return ret;
364 }
365 dmar_register_drhd_unit(dmaru);
366 return 0;
367}
368
Jiang Liua868e6b2014-01-06 14:18:20 +0800369static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
370{
371 if (dmaru->devices && dmaru->devices_cnt)
372 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
373 if (dmaru->iommu)
374 free_iommu(dmaru->iommu);
375 kfree(dmaru);
376}
377
David Woodhousee625b4a2014-03-07 14:34:38 +0000378static int __init dmar_parse_one_andd(struct acpi_dmar_header *header)
379{
380 struct acpi_dmar_andd *andd = (void *)header;
381
382 /* Check for NUL termination within the designated length */
383 if (strnlen(andd->object_name, header->length - 8) == header->length - 8) {
384 WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
385 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
386 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
387 dmi_get_system_info(DMI_BIOS_VENDOR),
388 dmi_get_system_info(DMI_BIOS_VERSION),
389 dmi_get_system_info(DMI_PRODUCT_VERSION));
390 return -EINVAL;
391 }
392 pr_info("ANDD device: %x name: %s\n", andd->device_number,
393 andd->object_name);
394
395 return 0;
396}
397
David Woodhouseaa697072009-10-07 12:18:00 +0100398#ifdef CONFIG_ACPI_NUMA
Suresh Siddhaee34b322009-10-02 11:01:21 -0700399static int __init
400dmar_parse_one_rhsa(struct acpi_dmar_header *header)
401{
402 struct acpi_dmar_rhsa *rhsa;
403 struct dmar_drhd_unit *drhd;
404
405 rhsa = (struct acpi_dmar_rhsa *)header;
David Woodhouseaa697072009-10-07 12:18:00 +0100406 for_each_drhd_unit(drhd) {
Suresh Siddhaee34b322009-10-02 11:01:21 -0700407 if (drhd->reg_base_addr == rhsa->base_address) {
408 int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
409
410 if (!node_online(node))
411 node = -1;
412 drhd->iommu->node = node;
David Woodhouseaa697072009-10-07 12:18:00 +0100413 return 0;
414 }
Suresh Siddhaee34b322009-10-02 11:01:21 -0700415 }
Ben Hutchingsfd0c8892010-04-03 19:38:43 +0100416 WARN_TAINT(
417 1, TAINT_FIRMWARE_WORKAROUND,
418 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
419 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
420 drhd->reg_base_addr,
421 dmi_get_system_info(DMI_BIOS_VENDOR),
422 dmi_get_system_info(DMI_BIOS_VERSION),
423 dmi_get_system_info(DMI_PRODUCT_VERSION));
Suresh Siddhaee34b322009-10-02 11:01:21 -0700424
David Woodhouseaa697072009-10-07 12:18:00 +0100425 return 0;
Suresh Siddhaee34b322009-10-02 11:01:21 -0700426}
David Woodhouseaa697072009-10-07 12:18:00 +0100427#endif
Suresh Siddhaee34b322009-10-02 11:01:21 -0700428
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700429static void __init
430dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
431{
432 struct acpi_dmar_hardware_unit *drhd;
433 struct acpi_dmar_reserved_memory *rmrr;
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800434 struct acpi_dmar_atsr *atsr;
Roland Dreier17b60972009-09-24 12:14:00 -0700435 struct acpi_dmar_rhsa *rhsa;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700436
437 switch (header->type) {
438 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800439 drhd = container_of(header, struct acpi_dmar_hardware_unit,
440 header);
Donald Dutilee9071b02012-06-08 17:13:11 -0400441 pr_info("DRHD base: %#016Lx flags: %#x\n",
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800442 (unsigned long long)drhd->address, drhd->flags);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700443 break;
444 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800445 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
446 header);
Donald Dutilee9071b02012-06-08 17:13:11 -0400447 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700448 (unsigned long long)rmrr->base_address,
449 (unsigned long long)rmrr->end_address);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700450 break;
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800451 case ACPI_DMAR_TYPE_ATSR:
452 atsr = container_of(header, struct acpi_dmar_atsr, header);
Donald Dutilee9071b02012-06-08 17:13:11 -0400453 pr_info("ATSR flags: %#x\n", atsr->flags);
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800454 break;
Roland Dreier17b60972009-09-24 12:14:00 -0700455 case ACPI_DMAR_HARDWARE_AFFINITY:
456 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
Donald Dutilee9071b02012-06-08 17:13:11 -0400457 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
Roland Dreier17b60972009-09-24 12:14:00 -0700458 (unsigned long long)rhsa->base_address,
459 rhsa->proximity_domain);
460 break;
David Woodhousee625b4a2014-03-07 14:34:38 +0000461 case ACPI_DMAR_TYPE_ANDD:
462 /* We don't print this here because we need to sanity-check
463 it first. So print it in dmar_parse_one_andd() instead. */
464 break;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700465 }
466}
467
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700468/**
469 * dmar_table_detect - checks to see if the platform supports DMAR devices
470 */
471static int __init dmar_table_detect(void)
472{
473 acpi_status status = AE_OK;
474
475 /* if we could find DMAR table, then there are DMAR devices */
Yinghai Lu8e1568f2009-02-11 01:06:59 -0800476 status = acpi_get_table_with_size(ACPI_SIG_DMAR, 0,
477 (struct acpi_table_header **)&dmar_tbl,
478 &dmar_tbl_size);
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700479
480 if (ACPI_SUCCESS(status) && !dmar_tbl) {
Donald Dutilee9071b02012-06-08 17:13:11 -0400481 pr_warn("Unable to map DMAR\n");
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700482 status = AE_NOT_FOUND;
483 }
484
485 return (ACPI_SUCCESS(status) ? 1 : 0);
486}
Suresh Siddhaaaa9d1d2008-07-10 11:16:38 -0700487
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700488/**
489 * parse_dmar_table - parses the DMA reporting table
490 */
491static int __init
492parse_dmar_table(void)
493{
494 struct acpi_table_dmar *dmar;
495 struct acpi_dmar_header *entry_header;
496 int ret = 0;
Li, Zhen-Hua7cef3342013-05-20 15:57:32 +0800497 int drhd_count = 0;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700498
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700499 /*
500 * Do it again, earlier dmar_tbl mapping could be mapped with
501 * fixed map.
502 */
503 dmar_table_detect();
504
Joseph Cihulaa59b50e2009-06-30 19:31:10 -0700505 /*
506 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
507 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
508 */
509 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
510
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700511 dmar = (struct acpi_table_dmar *)dmar_tbl;
512 if (!dmar)
513 return -ENODEV;
514
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700515 if (dmar->width < PAGE_SHIFT - 1) {
Donald Dutilee9071b02012-06-08 17:13:11 -0400516 pr_warn("Invalid DMAR haw\n");
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700517 return -EINVAL;
518 }
519
Donald Dutilee9071b02012-06-08 17:13:11 -0400520 pr_info("Host address width %d\n", dmar->width + 1);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700521
522 entry_header = (struct acpi_dmar_header *)(dmar + 1);
523 while (((unsigned long)entry_header) <
524 (((unsigned long)dmar) + dmar_tbl->length)) {
Tony Battersby084eb962009-02-11 13:24:19 -0800525 /* Avoid looping forever on bad ACPI tables */
526 if (entry_header->length == 0) {
Donald Dutilee9071b02012-06-08 17:13:11 -0400527 pr_warn("Invalid 0-length structure\n");
Tony Battersby084eb962009-02-11 13:24:19 -0800528 ret = -EINVAL;
529 break;
530 }
531
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700532 dmar_table_print_dmar_entry(entry_header);
533
534 switch (entry_header->type) {
535 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
Li, Zhen-Hua7cef3342013-05-20 15:57:32 +0800536 drhd_count++;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700537 ret = dmar_parse_one_drhd(entry_header);
538 break;
539 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
540 ret = dmar_parse_one_rmrr(entry_header);
541 break;
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800542 case ACPI_DMAR_TYPE_ATSR:
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800543 ret = dmar_parse_one_atsr(entry_header);
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800544 break;
Roland Dreier17b60972009-09-24 12:14:00 -0700545 case ACPI_DMAR_HARDWARE_AFFINITY:
David Woodhouseaa697072009-10-07 12:18:00 +0100546#ifdef CONFIG_ACPI_NUMA
Suresh Siddhaee34b322009-10-02 11:01:21 -0700547 ret = dmar_parse_one_rhsa(entry_header);
David Woodhouseaa697072009-10-07 12:18:00 +0100548#endif
Roland Dreier17b60972009-09-24 12:14:00 -0700549 break;
David Woodhousee625b4a2014-03-07 14:34:38 +0000550 case ACPI_DMAR_TYPE_ANDD:
551 ret = dmar_parse_one_andd(entry_header);
552 break;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700553 default:
Donald Dutilee9071b02012-06-08 17:13:11 -0400554 pr_warn("Unknown DMAR structure type %d\n",
Roland Dreier4de75cf2009-09-24 01:01:29 +0100555 entry_header->type);
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700556 ret = 0; /* for forward compatibility */
557 break;
558 }
559 if (ret)
560 break;
561
562 entry_header = ((void *)entry_header + entry_header->length);
563 }
Li, Zhen-Hua7cef3342013-05-20 15:57:32 +0800564 if (drhd_count == 0)
565 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700566 return ret;
567}
568
David Woodhouse832bd852014-03-07 15:08:36 +0000569static int dmar_pci_device_match(struct dmar_dev_scope devices[],
570 int cnt, struct pci_dev *dev)
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700571{
572 int index;
David Woodhouse832bd852014-03-07 15:08:36 +0000573 struct device *tmp;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700574
575 while (dev) {
Jiang Liub683b232014-02-19 14:07:32 +0800576 for_each_active_dev_scope(devices, cnt, index, tmp)
David Woodhouse832bd852014-03-07 15:08:36 +0000577 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700578 return 1;
579
580 /* Check our parent */
581 dev = dev->bus->self;
582 }
583
584 return 0;
585}
586
587struct dmar_drhd_unit *
588dmar_find_matched_drhd_unit(struct pci_dev *dev)
589{
Jiang Liu0e242612014-02-19 14:07:34 +0800590 struct dmar_drhd_unit *dmaru;
Yu Zhao2e824f72008-12-22 16:54:58 +0800591 struct acpi_dmar_hardware_unit *drhd;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700592
Yinghaidda56542010-04-09 01:07:55 +0100593 dev = pci_physfn(dev);
594
Jiang Liu0e242612014-02-19 14:07:34 +0800595 rcu_read_lock();
Yijing Wang8b161f02013-10-31 17:25:16 +0800596 for_each_drhd_unit(dmaru) {
Yu Zhao2e824f72008-12-22 16:54:58 +0800597 drhd = container_of(dmaru->hdr,
598 struct acpi_dmar_hardware_unit,
599 header);
600
601 if (dmaru->include_all &&
602 drhd->segment == pci_domain_nr(dev->bus))
Jiang Liu0e242612014-02-19 14:07:34 +0800603 goto out;
Yu Zhao2e824f72008-12-22 16:54:58 +0800604
605 if (dmar_pci_device_match(dmaru->devices,
606 dmaru->devices_cnt, dev))
Jiang Liu0e242612014-02-19 14:07:34 +0800607 goto out;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700608 }
Jiang Liu0e242612014-02-19 14:07:34 +0800609 dmaru = NULL;
610out:
611 rcu_read_unlock();
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700612
Jiang Liu0e242612014-02-19 14:07:34 +0800613 return dmaru;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700614}
615
David Woodhouseed403562014-03-07 23:15:42 +0000616static void __init dmar_acpi_insert_dev_scope(u8 device_number,
617 struct acpi_device *adev)
618{
619 struct dmar_drhd_unit *dmaru;
620 struct acpi_dmar_hardware_unit *drhd;
621 struct acpi_dmar_device_scope *scope;
622 struct device *tmp;
623 int i;
624 struct acpi_dmar_pci_path *path;
625
626 for_each_drhd_unit(dmaru) {
627 drhd = container_of(dmaru->hdr,
628 struct acpi_dmar_hardware_unit,
629 header);
630
631 for (scope = (void *)(drhd + 1);
632 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
633 scope = ((void *)scope) + scope->length) {
634 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ACPI)
635 continue;
636 if (scope->enumeration_id != device_number)
637 continue;
638
639 path = (void *)(scope + 1);
640 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
641 dev_name(&adev->dev), dmaru->reg_base_addr,
642 scope->bus, path->device, path->function);
643 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
644 if (tmp == NULL) {
645 dmaru->devices[i].bus = scope->bus;
646 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
647 path->function);
648 rcu_assign_pointer(dmaru->devices[i].dev,
649 get_device(&adev->dev));
650 return;
651 }
652 BUG_ON(i >= dmaru->devices_cnt);
653 }
654 }
655 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
656 device_number, dev_name(&adev->dev));
657}
658
659static int __init dmar_acpi_dev_scope_init(void)
660{
Joerg Roedel11f1a772014-03-25 20:16:40 +0100661 struct acpi_dmar_andd *andd;
662
663 if (dmar_tbl == NULL)
664 return -ENODEV;
665
David Woodhouse7713ec02014-04-01 14:58:36 +0100666 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
667 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
668 andd = ((void *)andd) + andd->header.length) {
David Woodhouseed403562014-03-07 23:15:42 +0000669 if (andd->header.type == ACPI_DMAR_TYPE_ANDD) {
670 acpi_handle h;
671 struct acpi_device *adev;
672
673 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
674 andd->object_name,
675 &h))) {
676 pr_err("Failed to find handle for ACPI object %s\n",
677 andd->object_name);
678 continue;
679 }
680 acpi_bus_get_device(h, &adev);
681 if (!adev) {
682 pr_err("Failed to get device for ACPI object %s\n",
683 andd->object_name);
684 continue;
685 }
686 dmar_acpi_insert_dev_scope(andd->device_number, adev);
687 }
David Woodhouseed403562014-03-07 23:15:42 +0000688 }
689 return 0;
690}
691
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700692int __init dmar_dev_scope_init(void)
693{
Jiang Liu2e455282014-02-19 14:07:36 +0800694 struct pci_dev *dev = NULL;
695 struct dmar_pci_notify_info *info;
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700696
Jiang Liu2e455282014-02-19 14:07:36 +0800697 if (dmar_dev_scope_status != 1)
698 return dmar_dev_scope_status;
Suresh Siddhac2c72862011-08-23 17:05:19 -0700699
Jiang Liu2e455282014-02-19 14:07:36 +0800700 if (list_empty(&dmar_drhd_units)) {
701 dmar_dev_scope_status = -ENODEV;
702 } else {
703 dmar_dev_scope_status = 0;
Suresh Siddha318fe7d2011-08-23 17:05:20 -0700704
David Woodhouse63b42622014-03-28 11:28:40 +0000705 dmar_acpi_dev_scope_init();
706
Jiang Liu2e455282014-02-19 14:07:36 +0800707 for_each_pci_dev(dev) {
708 if (dev->is_virtfn)
709 continue;
710
711 info = dmar_alloc_pci_notify_info(dev,
712 BUS_NOTIFY_ADD_DEVICE);
713 if (!info) {
714 return dmar_dev_scope_status;
715 } else {
716 dmar_pci_bus_add_dev(info);
717 dmar_free_pci_notify_info(info);
718 }
719 }
720
721 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700722 }
723
Jiang Liu2e455282014-02-19 14:07:36 +0800724 return dmar_dev_scope_status;
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700725}
726
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700727
728int __init dmar_table_init(void)
729{
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700730 static int dmar_table_initialized;
Fenghua Yu093f87d2007-11-21 15:07:14 -0800731 int ret;
732
Jiang Liucc053012014-01-06 14:18:24 +0800733 if (dmar_table_initialized == 0) {
734 ret = parse_dmar_table();
735 if (ret < 0) {
736 if (ret != -ENODEV)
737 pr_info("parse DMAR table failure.\n");
738 } else if (list_empty(&dmar_drhd_units)) {
739 pr_info("No DMAR devices found\n");
740 ret = -ENODEV;
741 }
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700742
Jiang Liucc053012014-01-06 14:18:24 +0800743 if (ret < 0)
744 dmar_table_initialized = ret;
745 else
746 dmar_table_initialized = 1;
Fenghua Yu093f87d2007-11-21 15:07:14 -0800747 }
748
Jiang Liucc053012014-01-06 14:18:24 +0800749 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700750}
751
Ben Hutchings3a8663e2010-04-03 19:37:23 +0100752static void warn_invalid_dmar(u64 addr, const char *message)
753{
Ben Hutchingsfd0c8892010-04-03 19:38:43 +0100754 WARN_TAINT_ONCE(
755 1, TAINT_FIRMWARE_WORKAROUND,
756 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
757 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
758 addr, message,
759 dmi_get_system_info(DMI_BIOS_VENDOR),
760 dmi_get_system_info(DMI_BIOS_VERSION),
761 dmi_get_system_info(DMI_PRODUCT_VERSION));
Ben Hutchings3a8663e2010-04-03 19:37:23 +0100762}
David Woodhouse6ecbf012009-12-02 09:20:27 +0000763
Rashika Kheria21004dc2013-12-18 12:01:46 +0530764static int __init check_zero_address(void)
David Woodhouse86cf8982009-11-09 22:15:15 +0000765{
766 struct acpi_table_dmar *dmar;
767 struct acpi_dmar_header *entry_header;
768 struct acpi_dmar_hardware_unit *drhd;
769
770 dmar = (struct acpi_table_dmar *)dmar_tbl;
771 entry_header = (struct acpi_dmar_header *)(dmar + 1);
772
773 while (((unsigned long)entry_header) <
774 (((unsigned long)dmar) + dmar_tbl->length)) {
775 /* Avoid looping forever on bad ACPI tables */
776 if (entry_header->length == 0) {
Donald Dutilee9071b02012-06-08 17:13:11 -0400777 pr_warn("Invalid 0-length structure\n");
David Woodhouse86cf8982009-11-09 22:15:15 +0000778 return 0;
779 }
780
781 if (entry_header->type == ACPI_DMAR_TYPE_HARDWARE_UNIT) {
Chris Wright2c992202009-12-02 09:17:13 +0000782 void __iomem *addr;
783 u64 cap, ecap;
784
David Woodhouse86cf8982009-11-09 22:15:15 +0000785 drhd = (void *)entry_header;
786 if (!drhd->address) {
Ben Hutchings3a8663e2010-04-03 19:37:23 +0100787 warn_invalid_dmar(0, "");
Chris Wright2c992202009-12-02 09:17:13 +0000788 goto failed;
David Woodhouse86cf8982009-11-09 22:15:15 +0000789 }
Chris Wright2c992202009-12-02 09:17:13 +0000790
791 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
792 if (!addr ) {
793 printk("IOMMU: can't validate: %llx\n", drhd->address);
794 goto failed;
795 }
796 cap = dmar_readq(addr + DMAR_CAP_REG);
797 ecap = dmar_readq(addr + DMAR_ECAP_REG);
798 early_iounmap(addr, VTD_PAGE_SIZE);
799 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
Ben Hutchings3a8663e2010-04-03 19:37:23 +0100800 warn_invalid_dmar(drhd->address,
801 " returns all ones");
Chris Wright2c992202009-12-02 09:17:13 +0000802 goto failed;
803 }
David Woodhouse86cf8982009-11-09 22:15:15 +0000804 }
805
806 entry_header = ((void *)entry_header + entry_header->length);
807 }
808 return 1;
Chris Wright2c992202009-12-02 09:17:13 +0000809
810failed:
Chris Wright2c992202009-12-02 09:17:13 +0000811 return 0;
David Woodhouse86cf8982009-11-09 22:15:15 +0000812}
813
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400814int __init detect_intel_iommu(void)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700815{
816 int ret;
817
Jiang Liu3a5670e2014-02-19 14:07:33 +0800818 down_write(&dmar_global_lock);
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700819 ret = dmar_table_detect();
David Woodhouse86cf8982009-11-09 22:15:15 +0000820 if (ret)
821 ret = check_zero_address();
Suresh Siddha2ae21012008-07-10 11:16:43 -0700822 {
Linus Torvalds11bd04f2009-12-11 12:18:16 -0800823 if (ret && !no_iommu && !iommu_detected && !dmar_disabled) {
Suresh Siddha2ae21012008-07-10 11:16:43 -0700824 iommu_detected = 1;
Chris Wright5d990b62009-12-04 12:15:21 -0800825 /* Make sure ACS will be enabled */
826 pci_request_acs();
827 }
Suresh Siddhaf5d1b972011-08-23 17:05:22 -0700828
FUJITA Tomonori9d5ce732009-11-10 19:46:16 +0900829#ifdef CONFIG_X86
830 if (ret)
831 x86_init.iommu.iommu_init = intel_iommu_init;
832#endif
Youquan Songcacd4212008-10-16 16:31:57 -0700833 }
Jiang Liub707cb02014-01-06 14:18:26 +0800834 early_acpi_os_unmap_memory((void __iomem *)dmar_tbl, dmar_tbl_size);
Yinghai Luf6dd5c32008-09-03 16:58:32 -0700835 dmar_tbl = NULL;
Jiang Liu3a5670e2014-02-19 14:07:33 +0800836 up_write(&dmar_global_lock);
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400837
Konrad Rzeszutek Wilk4db77ff2010-08-26 13:58:04 -0400838 return ret ? 1 : -ENODEV;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700839}
840
841
Donald Dutile6f5cf522012-06-04 17:29:02 -0400842static void unmap_iommu(struct intel_iommu *iommu)
843{
844 iounmap(iommu->reg);
845 release_mem_region(iommu->reg_phys, iommu->reg_size);
846}
847
848/**
849 * map_iommu: map the iommu's registers
850 * @iommu: the iommu to map
851 * @phys_addr: the physical address of the base resgister
Donald Dutilee9071b02012-06-08 17:13:11 -0400852 *
Donald Dutile6f5cf522012-06-04 17:29:02 -0400853 * Memory map the iommu's registers. Start w/ a single page, and
Donald Dutilee9071b02012-06-08 17:13:11 -0400854 * possibly expand if that turns out to be insufficent.
Donald Dutile6f5cf522012-06-04 17:29:02 -0400855 */
856static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
857{
858 int map_size, err=0;
859
860 iommu->reg_phys = phys_addr;
861 iommu->reg_size = VTD_PAGE_SIZE;
862
863 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
864 pr_err("IOMMU: can't reserve memory\n");
865 err = -EBUSY;
866 goto out;
867 }
868
869 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
870 if (!iommu->reg) {
871 pr_err("IOMMU: can't map the region\n");
872 err = -ENOMEM;
873 goto release;
874 }
875
876 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
877 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
878
879 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
880 err = -EINVAL;
881 warn_invalid_dmar(phys_addr, " returns all ones");
882 goto unmap;
883 }
884
885 /* the registers might be more than one page */
886 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
887 cap_max_fault_reg_offset(iommu->cap));
888 map_size = VTD_PAGE_ALIGN(map_size);
889 if (map_size > iommu->reg_size) {
890 iounmap(iommu->reg);
891 release_mem_region(iommu->reg_phys, iommu->reg_size);
892 iommu->reg_size = map_size;
893 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
894 iommu->name)) {
895 pr_err("IOMMU: can't reserve memory\n");
896 err = -EBUSY;
897 goto out;
898 }
899 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
900 if (!iommu->reg) {
901 pr_err("IOMMU: can't map the region\n");
902 err = -ENOMEM;
903 goto release;
904 }
905 }
906 err = 0;
907 goto out;
908
909unmap:
910 iounmap(iommu->reg);
911release:
912 release_mem_region(iommu->reg_phys, iommu->reg_size);
913out:
914 return err;
915}
916
Jiang Liu694835d2014-01-06 14:18:16 +0800917static int alloc_iommu(struct dmar_drhd_unit *drhd)
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700918{
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700919 struct intel_iommu *iommu;
Takao Indoh3a93c842013-04-23 17:35:03 +0900920 u32 ver, sts;
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700921 static int iommu_allocated = 0;
Joerg Roedel43f73922009-01-03 23:56:27 +0100922 int agaw = 0;
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -0700923 int msagaw = 0;
Donald Dutile6f5cf522012-06-04 17:29:02 -0400924 int err;
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700925
David Woodhouse6ecbf012009-12-02 09:20:27 +0000926 if (!drhd->reg_base_addr) {
Ben Hutchings3a8663e2010-04-03 19:37:23 +0100927 warn_invalid_dmar(0, "");
David Woodhouse6ecbf012009-12-02 09:20:27 +0000928 return -EINVAL;
929 }
930
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700931 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
932 if (!iommu)
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700933 return -ENOMEM;
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700934
935 iommu->seq_id = iommu_allocated++;
Suresh Siddha9d783ba2009-03-16 17:04:55 -0700936 sprintf (iommu->name, "dmar%d", iommu->seq_id);
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700937
Donald Dutile6f5cf522012-06-04 17:29:02 -0400938 err = map_iommu(iommu, drhd->reg_base_addr);
939 if (err) {
940 pr_err("IOMMU: failed to map %s\n", iommu->name);
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700941 goto error;
942 }
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700943
Donald Dutile6f5cf522012-06-04 17:29:02 -0400944 err = -EINVAL;
Weidong Han1b573682008-12-08 15:34:06 +0800945 agaw = iommu_calculate_agaw(iommu);
946 if (agaw < 0) {
Donald Dutilebf947fcb2012-06-04 17:29:01 -0400947 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
948 iommu->seq_id);
David Woodhouse08155652009-08-04 09:17:20 +0100949 goto err_unmap;
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -0700950 }
951 msagaw = iommu_calculate_max_sagaw(iommu);
952 if (msagaw < 0) {
Donald Dutilebf947fcb2012-06-04 17:29:01 -0400953 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
Weidong Han1b573682008-12-08 15:34:06 +0800954 iommu->seq_id);
David Woodhouse08155652009-08-04 09:17:20 +0100955 goto err_unmap;
Weidong Han1b573682008-12-08 15:34:06 +0800956 }
957 iommu->agaw = agaw;
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -0700958 iommu->msagaw = msagaw;
David Woodhouse67ccac42014-03-09 13:49:45 -0700959 iommu->segment = drhd->segment;
Weidong Han1b573682008-12-08 15:34:06 +0800960
Suresh Siddhaee34b322009-10-02 11:01:21 -0700961 iommu->node = -1;
962
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700963 ver = readl(iommu->reg + DMAR_VER_REG);
Yinghai Lu680a7522010-04-08 19:58:23 +0100964 pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
965 iommu->seq_id,
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700966 (unsigned long long)drhd->reg_base_addr,
967 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
968 (unsigned long long)iommu->cap,
969 (unsigned long long)iommu->ecap);
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700970
Takao Indoh3a93c842013-04-23 17:35:03 +0900971 /* Reflect status in gcmd */
972 sts = readl(iommu->reg + DMAR_GSTS_REG);
973 if (sts & DMA_GSTS_IRES)
974 iommu->gcmd |= DMA_GCMD_IRE;
975 if (sts & DMA_GSTS_TES)
976 iommu->gcmd |= DMA_GCMD_TE;
977 if (sts & DMA_GSTS_QIES)
978 iommu->gcmd |= DMA_GCMD_QIE;
979
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200980 raw_spin_lock_init(&iommu->register_lock);
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700981
982 drhd->iommu = iommu;
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700983 return 0;
David Woodhouse08155652009-08-04 09:17:20 +0100984
985 err_unmap:
Donald Dutile6f5cf522012-06-04 17:29:02 -0400986 unmap_iommu(iommu);
David Woodhouse08155652009-08-04 09:17:20 +0100987 error:
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700988 kfree(iommu);
Donald Dutile6f5cf522012-06-04 17:29:02 -0400989 return err;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700990}
991
Jiang Liua868e6b2014-01-06 14:18:20 +0800992static void free_iommu(struct intel_iommu *iommu)
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700993{
Jiang Liua868e6b2014-01-06 14:18:20 +0800994 if (iommu->irq) {
995 free_irq(iommu->irq, iommu);
996 irq_set_handler_data(iommu->irq, NULL);
997 destroy_irq(iommu->irq);
998 }
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700999
Jiang Liua84da702014-01-06 14:18:23 +08001000 if (iommu->qi) {
1001 free_page((unsigned long)iommu->qi->desc);
1002 kfree(iommu->qi->desc_status);
1003 kfree(iommu->qi);
1004 }
1005
Suresh Siddhae61d98d2008-07-10 11:16:35 -07001006 if (iommu->reg)
Donald Dutile6f5cf522012-06-04 17:29:02 -04001007 unmap_iommu(iommu);
1008
Suresh Siddhae61d98d2008-07-10 11:16:35 -07001009 kfree(iommu);
1010}
Suresh Siddhafe962e92008-07-10 11:16:42 -07001011
1012/*
1013 * Reclaim all the submitted descriptors which have completed its work.
1014 */
1015static inline void reclaim_free_desc(struct q_inval *qi)
1016{
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001017 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1018 qi->desc_status[qi->free_tail] == QI_ABORT) {
Suresh Siddhafe962e92008-07-10 11:16:42 -07001019 qi->desc_status[qi->free_tail] = QI_FREE;
1020 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1021 qi->free_cnt++;
1022 }
1023}
1024
Yu Zhao704126a2009-01-04 16:28:52 +08001025static int qi_check_fault(struct intel_iommu *iommu, int index)
1026{
1027 u32 fault;
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001028 int head, tail;
Yu Zhao704126a2009-01-04 16:28:52 +08001029 struct q_inval *qi = iommu->qi;
1030 int wait_index = (index + 1) % QI_LENGTH;
1031
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001032 if (qi->desc_status[wait_index] == QI_ABORT)
1033 return -EAGAIN;
1034
Yu Zhao704126a2009-01-04 16:28:52 +08001035 fault = readl(iommu->reg + DMAR_FSTS_REG);
1036
1037 /*
1038 * If IQE happens, the head points to the descriptor associated
1039 * with the error. No new descriptors are fetched until the IQE
1040 * is cleared.
1041 */
1042 if (fault & DMA_FSTS_IQE) {
1043 head = readl(iommu->reg + DMAR_IQH_REG);
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001044 if ((head >> DMAR_IQ_SHIFT) == index) {
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001045 pr_err("VT-d detected invalid descriptor: "
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001046 "low=%llx, high=%llx\n",
1047 (unsigned long long)qi->desc[index].low,
1048 (unsigned long long)qi->desc[index].high);
Yu Zhao704126a2009-01-04 16:28:52 +08001049 memcpy(&qi->desc[index], &qi->desc[wait_index],
1050 sizeof(struct qi_desc));
1051 __iommu_flush_cache(iommu, &qi->desc[index],
1052 sizeof(struct qi_desc));
1053 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1054 return -EINVAL;
1055 }
1056 }
1057
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001058 /*
1059 * If ITE happens, all pending wait_desc commands are aborted.
1060 * No new descriptors are fetched until the ITE is cleared.
1061 */
1062 if (fault & DMA_FSTS_ITE) {
1063 head = readl(iommu->reg + DMAR_IQH_REG);
1064 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1065 head |= 1;
1066 tail = readl(iommu->reg + DMAR_IQT_REG);
1067 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1068
1069 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1070
1071 do {
1072 if (qi->desc_status[head] == QI_IN_USE)
1073 qi->desc_status[head] = QI_ABORT;
1074 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1075 } while (head != tail);
1076
1077 if (qi->desc_status[wait_index] == QI_ABORT)
1078 return -EAGAIN;
1079 }
1080
1081 if (fault & DMA_FSTS_ICE)
1082 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1083
Yu Zhao704126a2009-01-04 16:28:52 +08001084 return 0;
1085}
1086
Suresh Siddhafe962e92008-07-10 11:16:42 -07001087/*
1088 * Submit the queued invalidation descriptor to the remapping
1089 * hardware unit and wait for its completion.
1090 */
Yu Zhao704126a2009-01-04 16:28:52 +08001091int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
Suresh Siddhafe962e92008-07-10 11:16:42 -07001092{
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001093 int rc;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001094 struct q_inval *qi = iommu->qi;
1095 struct qi_desc *hw, wait_desc;
1096 int wait_index, index;
1097 unsigned long flags;
1098
1099 if (!qi)
Yu Zhao704126a2009-01-04 16:28:52 +08001100 return 0;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001101
1102 hw = qi->desc;
1103
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001104restart:
1105 rc = 0;
1106
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001107 raw_spin_lock_irqsave(&qi->q_lock, flags);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001108 while (qi->free_cnt < 3) {
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001109 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001110 cpu_relax();
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001111 raw_spin_lock_irqsave(&qi->q_lock, flags);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001112 }
1113
1114 index = qi->free_head;
1115 wait_index = (index + 1) % QI_LENGTH;
1116
1117 qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1118
1119 hw[index] = *desc;
1120
Yu Zhao704126a2009-01-04 16:28:52 +08001121 wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
1122 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001123 wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
1124
1125 hw[wait_index] = wait_desc;
1126
1127 __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc));
1128 __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc));
1129
1130 qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1131 qi->free_cnt -= 2;
1132
Suresh Siddhafe962e92008-07-10 11:16:42 -07001133 /*
1134 * update the HW tail register indicating the presence of
1135 * new descriptors.
1136 */
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001137 writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001138
1139 while (qi->desc_status[wait_index] != QI_DONE) {
Suresh Siddhaf05810c2008-10-16 16:31:54 -07001140 /*
1141 * We will leave the interrupts disabled, to prevent interrupt
1142 * context to queue another cmd while a cmd is already submitted
1143 * and waiting for completion on this cpu. This is to avoid
1144 * a deadlock where the interrupt context can wait indefinitely
1145 * for free slots in the queue.
1146 */
Yu Zhao704126a2009-01-04 16:28:52 +08001147 rc = qi_check_fault(iommu, index);
1148 if (rc)
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001149 break;
Yu Zhao704126a2009-01-04 16:28:52 +08001150
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001151 raw_spin_unlock(&qi->q_lock);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001152 cpu_relax();
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001153 raw_spin_lock(&qi->q_lock);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001154 }
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001155
1156 qi->desc_status[index] = QI_DONE;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001157
1158 reclaim_free_desc(qi);
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001159 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
Yu Zhao704126a2009-01-04 16:28:52 +08001160
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001161 if (rc == -EAGAIN)
1162 goto restart;
1163
Yu Zhao704126a2009-01-04 16:28:52 +08001164 return rc;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001165}
1166
1167/*
1168 * Flush the global interrupt entry cache.
1169 */
1170void qi_global_iec(struct intel_iommu *iommu)
1171{
1172 struct qi_desc desc;
1173
1174 desc.low = QI_IEC_TYPE;
1175 desc.high = 0;
1176
Yu Zhao704126a2009-01-04 16:28:52 +08001177 /* should never fail */
Suresh Siddhafe962e92008-07-10 11:16:42 -07001178 qi_submit_sync(&desc, iommu);
1179}
1180
David Woodhouse4c25a2c2009-05-10 17:16:06 +01001181void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1182 u64 type)
Youquan Song3481f212008-10-16 16:31:55 -07001183{
Youquan Song3481f212008-10-16 16:31:55 -07001184 struct qi_desc desc;
1185
Youquan Song3481f212008-10-16 16:31:55 -07001186 desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1187 | QI_CC_GRAN(type) | QI_CC_TYPE;
1188 desc.high = 0;
1189
David Woodhouse4c25a2c2009-05-10 17:16:06 +01001190 qi_submit_sync(&desc, iommu);
Youquan Song3481f212008-10-16 16:31:55 -07001191}
1192
David Woodhouse1f0ef2a2009-05-10 19:58:49 +01001193void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1194 unsigned int size_order, u64 type)
Youquan Song3481f212008-10-16 16:31:55 -07001195{
1196 u8 dw = 0, dr = 0;
1197
1198 struct qi_desc desc;
1199 int ih = 0;
1200
Youquan Song3481f212008-10-16 16:31:55 -07001201 if (cap_write_drain(iommu->cap))
1202 dw = 1;
1203
1204 if (cap_read_drain(iommu->cap))
1205 dr = 1;
1206
1207 desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1208 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1209 desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1210 | QI_IOTLB_AM(size_order);
1211
David Woodhouse1f0ef2a2009-05-10 19:58:49 +01001212 qi_submit_sync(&desc, iommu);
Youquan Song3481f212008-10-16 16:31:55 -07001213}
1214
Yu Zhao6ba6c3a2009-05-18 13:51:35 +08001215void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
1216 u64 addr, unsigned mask)
1217{
1218 struct qi_desc desc;
1219
1220 if (mask) {
1221 BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
1222 addr |= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1223 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1224 } else
1225 desc.high = QI_DEV_IOTLB_ADDR(addr);
1226
1227 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1228 qdep = 0;
1229
1230 desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1231 QI_DIOTLB_TYPE;
1232
1233 qi_submit_sync(&desc, iommu);
1234}
1235
Suresh Siddhafe962e92008-07-10 11:16:42 -07001236/*
Suresh Siddhaeba67e52009-03-16 17:04:56 -07001237 * Disable Queued Invalidation interface.
1238 */
1239void dmar_disable_qi(struct intel_iommu *iommu)
1240{
1241 unsigned long flags;
1242 u32 sts;
1243 cycles_t start_time = get_cycles();
1244
1245 if (!ecap_qis(iommu->ecap))
1246 return;
1247
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001248 raw_spin_lock_irqsave(&iommu->register_lock, flags);
Suresh Siddhaeba67e52009-03-16 17:04:56 -07001249
1250 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
1251 if (!(sts & DMA_GSTS_QIES))
1252 goto end;
1253
1254 /*
1255 * Give a chance to HW to complete the pending invalidation requests.
1256 */
1257 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1258 readl(iommu->reg + DMAR_IQH_REG)) &&
1259 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1260 cpu_relax();
1261
1262 iommu->gcmd &= ~DMA_GCMD_QIE;
Suresh Siddhaeba67e52009-03-16 17:04:56 -07001263 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1264
1265 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1266 !(sts & DMA_GSTS_QIES), sts);
1267end:
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001268 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
Suresh Siddhaeba67e52009-03-16 17:04:56 -07001269}
1270
1271/*
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001272 * Enable queued invalidation.
1273 */
1274static void __dmar_enable_qi(struct intel_iommu *iommu)
1275{
David Woodhousec416daa2009-05-10 20:30:58 +01001276 u32 sts;
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001277 unsigned long flags;
1278 struct q_inval *qi = iommu->qi;
1279
1280 qi->free_head = qi->free_tail = 0;
1281 qi->free_cnt = QI_LENGTH;
1282
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001283 raw_spin_lock_irqsave(&iommu->register_lock, flags);
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001284
1285 /* write zero to the tail reg */
1286 writel(0, iommu->reg + DMAR_IQT_REG);
1287
1288 dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1289
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001290 iommu->gcmd |= DMA_GCMD_QIE;
David Woodhousec416daa2009-05-10 20:30:58 +01001291 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001292
1293 /* Make sure hardware complete it */
1294 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1295
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001296 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001297}
1298
1299/*
Suresh Siddhafe962e92008-07-10 11:16:42 -07001300 * Enable Queued Invalidation interface. This is a must to support
1301 * interrupt-remapping. Also used by DMA-remapping, which replaces
1302 * register based IOTLB invalidation.
1303 */
1304int dmar_enable_qi(struct intel_iommu *iommu)
1305{
Suresh Siddhafe962e92008-07-10 11:16:42 -07001306 struct q_inval *qi;
Suresh Siddha751cafe2009-10-02 11:01:22 -07001307 struct page *desc_page;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001308
1309 if (!ecap_qis(iommu->ecap))
1310 return -ENOENT;
1311
1312 /*
1313 * queued invalidation is already setup and enabled.
1314 */
1315 if (iommu->qi)
1316 return 0;
1317
Suresh Siddhafa4b57c2009-03-16 17:05:05 -07001318 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001319 if (!iommu->qi)
1320 return -ENOMEM;
1321
1322 qi = iommu->qi;
1323
Suresh Siddha751cafe2009-10-02 11:01:22 -07001324
1325 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1326 if (!desc_page) {
Suresh Siddhafe962e92008-07-10 11:16:42 -07001327 kfree(qi);
Jiang Liub707cb02014-01-06 14:18:26 +08001328 iommu->qi = NULL;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001329 return -ENOMEM;
1330 }
1331
Suresh Siddha751cafe2009-10-02 11:01:22 -07001332 qi->desc = page_address(desc_page);
1333
Hannes Reinecke37a40712013-02-06 09:50:10 +01001334 qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001335 if (!qi->desc_status) {
1336 free_page((unsigned long) qi->desc);
1337 kfree(qi);
Jiang Liub707cb02014-01-06 14:18:26 +08001338 iommu->qi = NULL;
Suresh Siddhafe962e92008-07-10 11:16:42 -07001339 return -ENOMEM;
1340 }
1341
1342 qi->free_head = qi->free_tail = 0;
1343 qi->free_cnt = QI_LENGTH;
1344
Thomas Gleixner3b8f4042011-07-19 17:02:07 +02001345 raw_spin_lock_init(&qi->q_lock);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001346
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001347 __dmar_enable_qi(iommu);
Suresh Siddhafe962e92008-07-10 11:16:42 -07001348
1349 return 0;
1350}
Suresh Siddha0ac24912009-03-16 17:04:54 -07001351
1352/* iommu interrupt handling. Most stuff are MSI-like. */
1353
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001354enum faulttype {
1355 DMA_REMAP,
1356 INTR_REMAP,
1357 UNKNOWN,
1358};
1359
1360static const char *dma_remap_fault_reasons[] =
Suresh Siddha0ac24912009-03-16 17:04:54 -07001361{
1362 "Software",
1363 "Present bit in root entry is clear",
1364 "Present bit in context entry is clear",
1365 "Invalid context entry",
1366 "Access beyond MGAW",
1367 "PTE Write access is not set",
1368 "PTE Read access is not set",
1369 "Next page table ptr is invalid",
1370 "Root table address invalid",
1371 "Context table ptr is invalid",
1372 "non-zero reserved fields in RTP",
1373 "non-zero reserved fields in CTP",
1374 "non-zero reserved fields in PTE",
Li, Zhen-Hua4ecccd92013-03-06 10:43:17 +08001375 "PCE for translation request specifies blocking",
Suresh Siddha0ac24912009-03-16 17:04:54 -07001376};
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001377
Suresh Siddha95a02e92012-03-30 11:47:07 -07001378static const char *irq_remap_fault_reasons[] =
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001379{
1380 "Detected reserved fields in the decoded interrupt-remapped request",
1381 "Interrupt index exceeded the interrupt-remapping table size",
1382 "Present field in the IRTE entry is clear",
1383 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1384 "Detected reserved fields in the IRTE entry",
1385 "Blocked a compatibility format interrupt request",
1386 "Blocked an interrupt request due to source-id verification failure",
1387};
1388
Rashika Kheria21004dc2013-12-18 12:01:46 +05301389static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
Suresh Siddha0ac24912009-03-16 17:04:54 -07001390{
Dan Carpenterfefe1ed2012-05-13 20:09:38 +03001391 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1392 ARRAY_SIZE(irq_remap_fault_reasons))) {
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001393 *fault_type = INTR_REMAP;
Suresh Siddha95a02e92012-03-30 11:47:07 -07001394 return irq_remap_fault_reasons[fault_reason - 0x20];
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001395 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1396 *fault_type = DMA_REMAP;
1397 return dma_remap_fault_reasons[fault_reason];
1398 } else {
1399 *fault_type = UNKNOWN;
Suresh Siddha0ac24912009-03-16 17:04:54 -07001400 return "Unknown";
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001401 }
Suresh Siddha0ac24912009-03-16 17:04:54 -07001402}
1403
Thomas Gleixner5c2837f2010-09-28 17:15:11 +02001404void dmar_msi_unmask(struct irq_data *data)
Suresh Siddha0ac24912009-03-16 17:04:54 -07001405{
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001406 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001407 unsigned long flag;
1408
1409 /* unmask it */
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001410 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001411 writel(0, iommu->reg + DMAR_FECTL_REG);
1412 /* Read a reg to force flush the post write */
1413 readl(iommu->reg + DMAR_FECTL_REG);
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001414 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001415}
1416
Thomas Gleixner5c2837f2010-09-28 17:15:11 +02001417void dmar_msi_mask(struct irq_data *data)
Suresh Siddha0ac24912009-03-16 17:04:54 -07001418{
1419 unsigned long flag;
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001420 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001421
1422 /* mask it */
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001423 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001424 writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
1425 /* Read a reg to force flush the post write */
1426 readl(iommu->reg + DMAR_FECTL_REG);
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001427 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001428}
1429
1430void dmar_msi_write(int irq, struct msi_msg *msg)
1431{
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001432 struct intel_iommu *iommu = irq_get_handler_data(irq);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001433 unsigned long flag;
1434
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001435 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001436 writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
1437 writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
1438 writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001439 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001440}
1441
1442void dmar_msi_read(int irq, struct msi_msg *msg)
1443{
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001444 struct intel_iommu *iommu = irq_get_handler_data(irq);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001445 unsigned long flag;
1446
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001447 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001448 msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
1449 msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
1450 msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001451 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001452}
1453
1454static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1455 u8 fault_reason, u16 source_id, unsigned long long addr)
1456{
1457 const char *reason;
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001458 int fault_type;
Suresh Siddha0ac24912009-03-16 17:04:54 -07001459
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001460 reason = dmar_get_fault_reason(fault_reason, &fault_type);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001461
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001462 if (fault_type == INTR_REMAP)
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001463 pr_err("INTR-REMAP: Request device [[%02x:%02x.%d] "
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001464 "fault index %llx\n"
1465 "INTR-REMAP:[fault reason %02d] %s\n",
1466 (source_id >> 8), PCI_SLOT(source_id & 0xFF),
1467 PCI_FUNC(source_id & 0xFF), addr >> 48,
1468 fault_reason, reason);
1469 else
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001470 pr_err("DMAR:[%s] Request device [%02x:%02x.%d] "
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001471 "fault addr %llx \n"
1472 "DMAR:[fault reason %02d] %s\n",
1473 (type ? "DMA Read" : "DMA Write"),
1474 (source_id >> 8), PCI_SLOT(source_id & 0xFF),
1475 PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001476 return 0;
1477}
1478
1479#define PRIMARY_FAULT_REG_LEN (16)
Suresh Siddha1531a6a2009-03-16 17:04:57 -07001480irqreturn_t dmar_fault(int irq, void *dev_id)
Suresh Siddha0ac24912009-03-16 17:04:54 -07001481{
1482 struct intel_iommu *iommu = dev_id;
1483 int reg, fault_index;
1484 u32 fault_status;
1485 unsigned long flag;
1486
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001487 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001488 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001489 if (fault_status)
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001490 pr_err("DRHD: handling fault status reg %x\n", fault_status);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001491
1492 /* TBD: ignore advanced fault log currently */
1493 if (!(fault_status & DMA_FSTS_PPF))
Li, Zhen-Huabd5cdad2013-03-25 16:20:52 +08001494 goto unlock_exit;
Suresh Siddha0ac24912009-03-16 17:04:54 -07001495
1496 fault_index = dma_fsts_fault_record_index(fault_status);
1497 reg = cap_fault_reg_offset(iommu->cap);
1498 while (1) {
1499 u8 fault_reason;
1500 u16 source_id;
1501 u64 guest_addr;
1502 int type;
1503 u32 data;
1504
1505 /* highest 32 bits */
1506 data = readl(iommu->reg + reg +
1507 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1508 if (!(data & DMA_FRCD_F))
1509 break;
1510
1511 fault_reason = dma_frcd_fault_reason(data);
1512 type = dma_frcd_type(data);
1513
1514 data = readl(iommu->reg + reg +
1515 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1516 source_id = dma_frcd_source_id(data);
1517
1518 guest_addr = dmar_readq(iommu->reg + reg +
1519 fault_index * PRIMARY_FAULT_REG_LEN);
1520 guest_addr = dma_frcd_page_addr(guest_addr);
1521 /* clear the fault */
1522 writel(DMA_FRCD_F, iommu->reg + reg +
1523 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1524
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001525 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001526
1527 dmar_fault_do_one(iommu, type, fault_reason,
1528 source_id, guest_addr);
1529
1530 fault_index++;
Troy Heber8211a7b2009-08-19 15:26:11 -06001531 if (fault_index >= cap_num_fault_regs(iommu->cap))
Suresh Siddha0ac24912009-03-16 17:04:54 -07001532 fault_index = 0;
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001533 raw_spin_lock_irqsave(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001534 }
Suresh Siddha0ac24912009-03-16 17:04:54 -07001535
Li, Zhen-Huabd5cdad2013-03-25 16:20:52 +08001536 writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);
1537
1538unlock_exit:
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +02001539 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001540 return IRQ_HANDLED;
1541}
1542
1543int dmar_set_interrupt(struct intel_iommu *iommu)
1544{
1545 int irq, ret;
1546
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001547 /*
1548 * Check if the fault interrupt is already initialized.
1549 */
1550 if (iommu->irq)
1551 return 0;
1552
Suresh Siddha0ac24912009-03-16 17:04:54 -07001553 irq = create_irq();
1554 if (!irq) {
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001555 pr_err("IOMMU: no free vectors\n");
Suresh Siddha0ac24912009-03-16 17:04:54 -07001556 return -EINVAL;
1557 }
1558
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001559 irq_set_handler_data(irq, iommu);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001560 iommu->irq = irq;
1561
1562 ret = arch_setup_dmar_msi(irq);
1563 if (ret) {
Thomas Gleixnerdced35a2011-03-28 17:49:12 +02001564 irq_set_handler_data(irq, NULL);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001565 iommu->irq = 0;
1566 destroy_irq(irq);
Chris Wrightdd726432009-05-13 15:55:52 -07001567 return ret;
Suresh Siddha0ac24912009-03-16 17:04:54 -07001568 }
1569
Thomas Gleixner477694e2011-07-19 16:25:42 +02001570 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
Suresh Siddha0ac24912009-03-16 17:04:54 -07001571 if (ret)
Donald Dutilebf947fcb2012-06-04 17:29:01 -04001572 pr_err("IOMMU: can't request irq\n");
Suresh Siddha0ac24912009-03-16 17:04:54 -07001573 return ret;
1574}
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001575
1576int __init enable_drhd_fault_handling(void)
1577{
1578 struct dmar_drhd_unit *drhd;
Jiang Liu7c919772014-01-06 14:18:18 +08001579 struct intel_iommu *iommu;
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001580
1581 /*
1582 * Enable fault control interrupt.
1583 */
Jiang Liu7c919772014-01-06 14:18:18 +08001584 for_each_iommu(iommu, drhd) {
Li, Zhen-Huabd5cdad2013-03-25 16:20:52 +08001585 u32 fault_status;
Jiang Liu7c919772014-01-06 14:18:18 +08001586 int ret = dmar_set_interrupt(iommu);
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001587
1588 if (ret) {
Donald Dutilee9071b02012-06-08 17:13:11 -04001589 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001590 (unsigned long long)drhd->reg_base_addr, ret);
1591 return -1;
1592 }
Suresh Siddha7f99d942010-11-30 22:22:29 -08001593
1594 /*
1595 * Clear any previous faults.
1596 */
1597 dmar_fault(iommu->irq, iommu);
Li, Zhen-Huabd5cdad2013-03-25 16:20:52 +08001598 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1599 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
Suresh Siddha9d783ba2009-03-16 17:04:55 -07001600 }
1601
1602 return 0;
1603}
Fenghua Yueb4a52b2009-03-27 14:22:43 -07001604
1605/*
1606 * Re-enable Queued Invalidation interface.
1607 */
1608int dmar_reenable_qi(struct intel_iommu *iommu)
1609{
1610 if (!ecap_qis(iommu->ecap))
1611 return -ENOENT;
1612
1613 if (!iommu->qi)
1614 return -ENOENT;
1615
1616 /*
1617 * First disable queued invalidation.
1618 */
1619 dmar_disable_qi(iommu);
1620 /*
1621 * Then enable queued invalidation again. Since there is no pending
1622 * invalidation requests now, it's safe to re-enable queued
1623 * invalidation.
1624 */
1625 __dmar_enable_qi(iommu);
1626
1627 return 0;
1628}
Youquan Song074835f2009-09-09 12:05:39 -04001629
1630/*
1631 * Check interrupt remapping support in DMAR table description.
1632 */
Luck, Tony0b8973a2009-12-16 22:59:29 +00001633int __init dmar_ir_support(void)
Youquan Song074835f2009-09-09 12:05:39 -04001634{
1635 struct acpi_table_dmar *dmar;
1636 dmar = (struct acpi_table_dmar *)dmar_tbl;
Arnaud Patard4f506e02010-03-25 18:02:58 +00001637 if (!dmar)
1638 return 0;
Youquan Song074835f2009-09-09 12:05:39 -04001639 return dmar->flags & 0x1;
1640}
Jiang Liu694835d2014-01-06 14:18:16 +08001641
Jiang Liua868e6b2014-01-06 14:18:20 +08001642static int __init dmar_free_unused_resources(void)
1643{
1644 struct dmar_drhd_unit *dmaru, *dmaru_n;
1645
1646 /* DMAR units are in use */
1647 if (irq_remapping_enabled || intel_iommu_enabled)
1648 return 0;
1649
Jiang Liu2e455282014-02-19 14:07:36 +08001650 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1651 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
Jiang Liu59ce0512014-02-19 14:07:35 +08001652
Jiang Liu3a5670e2014-02-19 14:07:33 +08001653 down_write(&dmar_global_lock);
Jiang Liua868e6b2014-01-06 14:18:20 +08001654 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1655 list_del(&dmaru->list);
1656 dmar_free_drhd(dmaru);
1657 }
Jiang Liu3a5670e2014-02-19 14:07:33 +08001658 up_write(&dmar_global_lock);
Jiang Liua868e6b2014-01-06 14:18:20 +08001659
1660 return 0;
1661}
1662
1663late_initcall(dmar_free_unused_resources);
Konrad Rzeszutek Wilk4db77ff2010-08-26 13:58:04 -04001664IOMMU_INIT_POST(detect_intel_iommu);