Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E |
| 3 | * |
| 4 | * Copyright (C) 2000 ARM Limited |
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 6 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * |
| 14 | * These are the low level assembler for performing cache and TLB |
| 15 | * functions on the ARM1022E. |
| 16 | */ |
| 17 | #include <linux/linkage.h> |
| 18 | #include <linux/config.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <asm/assembler.h> |
Sam Ravnborg | e6ae744 | 2005-09-09 21:08:59 +0200 | [diff] [blame] | 21 | #include <asm/asm-offsets.h> |
Russell King | 74945c8 | 2006-03-16 14:44:36 +0000 | [diff] [blame] | 22 | #include <asm/pgtable-hwdef.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <asm/pgtable.h> |
| 24 | #include <asm/procinfo.h> |
| 25 | #include <asm/ptrace.h> |
| 26 | |
| 27 | /* |
| 28 | * This is the maximum size of an area which will be invalidated |
| 29 | * using the single invalidate entry instructions. Anything larger |
| 30 | * than this, and we go for the whole cache. |
| 31 | * |
| 32 | * This value should be chosen such that we choose the cheapest |
| 33 | * alternative. |
| 34 | */ |
| 35 | #define MAX_AREA_SIZE 32768 |
| 36 | |
| 37 | /* |
| 38 | * The size of one data cache line. |
| 39 | */ |
| 40 | #define CACHE_DLINESIZE 32 |
| 41 | |
| 42 | /* |
| 43 | * The number of data cache segments. |
| 44 | */ |
| 45 | #define CACHE_DSEGMENTS 16 |
| 46 | |
| 47 | /* |
| 48 | * The number of lines in a cache segment. |
| 49 | */ |
| 50 | #define CACHE_DENTRIES 64 |
| 51 | |
| 52 | /* |
| 53 | * This is the size at which it becomes more efficient to |
| 54 | * clean the whole cache, rather than using the individual |
| 55 | * cache line maintainence instructions. |
| 56 | */ |
| 57 | #define CACHE_DLIMIT 32768 |
| 58 | |
| 59 | .text |
| 60 | /* |
| 61 | * cpu_arm1022_proc_init() |
| 62 | */ |
| 63 | ENTRY(cpu_arm1022_proc_init) |
| 64 | mov pc, lr |
| 65 | |
| 66 | /* |
| 67 | * cpu_arm1022_proc_fin() |
| 68 | */ |
| 69 | ENTRY(cpu_arm1022_proc_fin) |
| 70 | stmfd sp!, {lr} |
| 71 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE |
| 72 | msr cpsr_c, ip |
| 73 | bl arm1022_flush_kern_cache_all |
| 74 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
| 75 | bic r0, r0, #0x1000 @ ...i............ |
| 76 | bic r0, r0, #0x000e @ ............wca. |
| 77 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
| 78 | ldmfd sp!, {pc} |
| 79 | |
| 80 | /* |
| 81 | * cpu_arm1022_reset(loc) |
| 82 | * |
| 83 | * Perform a soft reset of the system. Put the CPU into the |
| 84 | * same state as it would be if it had been reset, and branch |
| 85 | * to what would be the reset vector. |
| 86 | * |
| 87 | * loc: location to jump to for soft reset |
| 88 | */ |
| 89 | .align 5 |
| 90 | ENTRY(cpu_arm1022_reset) |
| 91 | mov ip, #0 |
| 92 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
| 93 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 94 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 96 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
| 98 | bic ip, ip, #0x000f @ ............wcam |
| 99 | bic ip, ip, #0x1100 @ ...i...s........ |
| 100 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
| 101 | mov pc, r0 |
| 102 | |
| 103 | /* |
| 104 | * cpu_arm1022_do_idle() |
| 105 | */ |
| 106 | .align 5 |
| 107 | ENTRY(cpu_arm1022_do_idle) |
| 108 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt |
| 109 | mov pc, lr |
| 110 | |
| 111 | /* ================================= CACHE ================================ */ |
| 112 | |
| 113 | .align 5 |
| 114 | /* |
| 115 | * flush_user_cache_all() |
| 116 | * |
| 117 | * Invalidate all cache entries in a particular address |
| 118 | * space. |
| 119 | */ |
| 120 | ENTRY(arm1022_flush_user_cache_all) |
| 121 | /* FALLTHROUGH */ |
| 122 | /* |
| 123 | * flush_kern_cache_all() |
| 124 | * |
| 125 | * Clean and invalidate the entire cache. |
| 126 | */ |
| 127 | ENTRY(arm1022_flush_kern_cache_all) |
| 128 | mov r2, #VM_EXEC |
| 129 | mov ip, #0 |
| 130 | __flush_whole_cache: |
| 131 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 132 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments |
| 133 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
| 134 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index |
| 135 | subs r3, r3, #1 << 26 |
| 136 | bcs 2b @ entries 63 to 0 |
| 137 | subs r1, r1, #1 << 5 |
| 138 | bcs 1b @ segments 15 to 0 |
| 139 | #endif |
| 140 | tst r2, #VM_EXEC |
| 141 | #ifndef CONFIG_CPU_ICACHE_DISABLE |
| 142 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
| 143 | #endif |
| 144 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
| 145 | mov pc, lr |
| 146 | |
| 147 | /* |
| 148 | * flush_user_cache_range(start, end, flags) |
| 149 | * |
| 150 | * Invalidate a range of cache entries in the specified |
| 151 | * address space. |
| 152 | * |
| 153 | * - start - start address (inclusive) |
| 154 | * - end - end address (exclusive) |
| 155 | * - flags - vm_flags for this space |
| 156 | */ |
| 157 | ENTRY(arm1022_flush_user_cache_range) |
| 158 | mov ip, #0 |
| 159 | sub r3, r1, r0 @ calculate total size |
| 160 | cmp r3, #CACHE_DLIMIT |
| 161 | bhs __flush_whole_cache |
| 162 | |
| 163 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 164 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
| 165 | add r0, r0, #CACHE_DLINESIZE |
| 166 | cmp r0, r1 |
| 167 | blo 1b |
| 168 | #endif |
| 169 | tst r2, #VM_EXEC |
| 170 | #ifndef CONFIG_CPU_ICACHE_DISABLE |
| 171 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
| 172 | #endif |
| 173 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
| 174 | mov pc, lr |
| 175 | |
| 176 | /* |
| 177 | * coherent_kern_range(start, end) |
| 178 | * |
| 179 | * Ensure coherency between the Icache and the Dcache in the |
| 180 | * region described by start. If you have non-snooping |
| 181 | * Harvard caches, you need to implement this function. |
| 182 | * |
| 183 | * - start - virtual start address |
| 184 | * - end - virtual end address |
| 185 | */ |
| 186 | ENTRY(arm1022_coherent_kern_range) |
| 187 | /* FALLTHROUGH */ |
| 188 | |
| 189 | /* |
| 190 | * coherent_user_range(start, end) |
| 191 | * |
| 192 | * Ensure coherency between the Icache and the Dcache in the |
| 193 | * region described by start. If you have non-snooping |
| 194 | * Harvard caches, you need to implement this function. |
| 195 | * |
| 196 | * - start - virtual start address |
| 197 | * - end - virtual end address |
| 198 | */ |
| 199 | ENTRY(arm1022_coherent_user_range) |
| 200 | mov ip, #0 |
| 201 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 202 | 1: |
| 203 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 204 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 205 | #endif |
| 206 | #ifndef CONFIG_CPU_ICACHE_DISABLE |
| 207 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry |
| 208 | #endif |
| 209 | add r0, r0, #CACHE_DLINESIZE |
| 210 | cmp r0, r1 |
| 211 | blo 1b |
| 212 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 213 | mov pc, lr |
| 214 | |
| 215 | /* |
| 216 | * flush_kern_dcache_page(void *page) |
| 217 | * |
| 218 | * Ensure no D cache aliasing occurs, either with itself or |
| 219 | * the I cache |
| 220 | * |
| 221 | * - page - page aligned address |
| 222 | */ |
| 223 | ENTRY(arm1022_flush_kern_dcache_page) |
| 224 | mov ip, #0 |
| 225 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 226 | add r1, r0, #PAGE_SZ |
| 227 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
| 228 | add r0, r0, #CACHE_DLINESIZE |
| 229 | cmp r0, r1 |
| 230 | blo 1b |
| 231 | #endif |
| 232 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 233 | mov pc, lr |
| 234 | |
| 235 | /* |
| 236 | * dma_inv_range(start, end) |
| 237 | * |
| 238 | * Invalidate (discard) the specified virtual address range. |
| 239 | * May not write back any entries. If 'start' or 'end' |
| 240 | * are not cache line aligned, those lines must be written |
| 241 | * back. |
| 242 | * |
| 243 | * - start - virtual start address |
| 244 | * - end - virtual end address |
| 245 | * |
| 246 | * (same as v4wb) |
| 247 | */ |
| 248 | ENTRY(arm1022_dma_inv_range) |
| 249 | mov ip, #0 |
| 250 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 251 | tst r0, #CACHE_DLINESIZE - 1 |
| 252 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 253 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
| 254 | tst r1, #CACHE_DLINESIZE - 1 |
| 255 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
| 256 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
| 257 | add r0, r0, #CACHE_DLINESIZE |
| 258 | cmp r0, r1 |
| 259 | blo 1b |
| 260 | #endif |
| 261 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 262 | mov pc, lr |
| 263 | |
| 264 | /* |
| 265 | * dma_clean_range(start, end) |
| 266 | * |
| 267 | * Clean the specified virtual address range. |
| 268 | * |
| 269 | * - start - virtual start address |
| 270 | * - end - virtual end address |
| 271 | * |
| 272 | * (same as v4wb) |
| 273 | */ |
| 274 | ENTRY(arm1022_dma_clean_range) |
| 275 | mov ip, #0 |
| 276 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 277 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 278 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 279 | add r0, r0, #CACHE_DLINESIZE |
| 280 | cmp r0, r1 |
| 281 | blo 1b |
| 282 | #endif |
| 283 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 284 | mov pc, lr |
| 285 | |
| 286 | /* |
| 287 | * dma_flush_range(start, end) |
| 288 | * |
| 289 | * Clean and invalidate the specified virtual address range. |
| 290 | * |
| 291 | * - start - virtual start address |
| 292 | * - end - virtual end address |
| 293 | */ |
| 294 | ENTRY(arm1022_dma_flush_range) |
| 295 | mov ip, #0 |
| 296 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 297 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 298 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
| 299 | add r0, r0, #CACHE_DLINESIZE |
| 300 | cmp r0, r1 |
| 301 | blo 1b |
| 302 | #endif |
| 303 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 304 | mov pc, lr |
| 305 | |
| 306 | ENTRY(arm1022_cache_fns) |
| 307 | .long arm1022_flush_kern_cache_all |
| 308 | .long arm1022_flush_user_cache_all |
| 309 | .long arm1022_flush_user_cache_range |
| 310 | .long arm1022_coherent_kern_range |
| 311 | .long arm1022_coherent_user_range |
| 312 | .long arm1022_flush_kern_dcache_page |
| 313 | .long arm1022_dma_inv_range |
| 314 | .long arm1022_dma_clean_range |
| 315 | .long arm1022_dma_flush_range |
| 316 | |
| 317 | .align 5 |
| 318 | ENTRY(cpu_arm1022_dcache_clean_area) |
| 319 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 320 | mov ip, #0 |
| 321 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 322 | add r0, r0, #CACHE_DLINESIZE |
| 323 | subs r1, r1, #CACHE_DLINESIZE |
| 324 | bhi 1b |
| 325 | #endif |
| 326 | mov pc, lr |
| 327 | |
| 328 | /* =============================== PageTable ============================== */ |
| 329 | |
| 330 | /* |
| 331 | * cpu_arm1022_switch_mm(pgd) |
| 332 | * |
| 333 | * Set the translation base pointer to be as described by pgd. |
| 334 | * |
| 335 | * pgd: new page tables |
| 336 | */ |
| 337 | .align 5 |
| 338 | ENTRY(cpu_arm1022_switch_mm) |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 339 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 341 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments |
| 342 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
| 343 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index |
| 344 | subs r3, r3, #1 << 26 |
| 345 | bcs 2b @ entries 63 to 0 |
| 346 | subs r1, r1, #1 << 5 |
| 347 | bcs 1b @ segments 15 to 0 |
| 348 | #endif |
| 349 | mov r1, #0 |
| 350 | #ifndef CONFIG_CPU_ICACHE_DISABLE |
| 351 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache |
| 352 | #endif |
| 353 | mcr p15, 0, r1, c7, c10, 4 @ drain WB |
| 354 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
| 355 | mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 356 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | mov pc, lr |
| 358 | |
| 359 | /* |
| 360 | * cpu_arm1022_set_pte(ptep, pte) |
| 361 | * |
| 362 | * Set a PTE and flush it out |
| 363 | */ |
| 364 | .align 5 |
| 365 | ENTRY(cpu_arm1022_set_pte) |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 366 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | str r1, [r0], #-2048 @ linux version |
| 368 | |
| 369 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY |
| 370 | |
| 371 | bic r2, r1, #PTE_SMALL_AP_MASK |
| 372 | bic r2, r2, #PTE_TYPE_MASK |
| 373 | orr r2, r2, #PTE_TYPE_SMALL |
| 374 | |
| 375 | tst r1, #L_PTE_USER @ User? |
| 376 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW |
| 377 | |
| 378 | tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? |
| 379 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW |
| 380 | |
| 381 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? |
| 382 | movne r2, #0 |
| 383 | |
| 384 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
| 385 | eor r3, r1, #0x0a @ C & small page? |
| 386 | tst r3, #0x0b |
| 387 | biceq r2, r2, #4 |
| 388 | #endif |
| 389 | str r2, [r0] @ hardware version |
| 390 | mov r0, r0 |
| 391 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
| 392 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 393 | #endif |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 394 | #endif /* CONFIG_MMU */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | mov pc, lr |
| 396 | |
| 397 | __INIT |
| 398 | |
| 399 | .type __arm1022_setup, #function |
| 400 | __arm1022_setup: |
| 401 | mov r0, #0 |
| 402 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 |
| 403 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 404 | #ifdef CONFIG_MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
Hyok S. Choi | d090ddd | 2006-06-28 14:10:01 +0100 | [diff] [blame] | 406 | #endif |
Russell King | 22b19086 | 2006-06-29 15:09:57 +0100 | [diff] [blame^] | 407 | adr r5, arm1022_crval |
| 408 | ldmia r5, {r5, r6} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | bic r0, r0, r5 |
Russell King | 22b19086 | 2006-06-29 15:09:57 +0100 | [diff] [blame^] | 411 | orr r0, r0, r6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN |
| 413 | orr r0, r0, #0x4000 @ .R.............. |
| 414 | #endif |
| 415 | mov pc, lr |
| 416 | .size __arm1022_setup, . - __arm1022_setup |
| 417 | |
| 418 | /* |
| 419 | * R |
| 420 | * .RVI ZFRS BLDP WCAM |
| 421 | * .011 1001 ..11 0101 |
| 422 | * |
| 423 | */ |
Russell King | 22b19086 | 2006-06-29 15:09:57 +0100 | [diff] [blame^] | 424 | .type arm1022_crval, #object |
| 425 | arm1022_crval: |
| 426 | crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | |
| 428 | __INITDATA |
| 429 | |
| 430 | /* |
| 431 | * Purpose : Function pointers used to access above functions - all calls |
| 432 | * come through these |
| 433 | */ |
| 434 | .type arm1022_processor_functions, #object |
| 435 | arm1022_processor_functions: |
| 436 | .word v4t_early_abort |
| 437 | .word cpu_arm1022_proc_init |
| 438 | .word cpu_arm1022_proc_fin |
| 439 | .word cpu_arm1022_reset |
| 440 | .word cpu_arm1022_do_idle |
| 441 | .word cpu_arm1022_dcache_clean_area |
| 442 | .word cpu_arm1022_switch_mm |
| 443 | .word cpu_arm1022_set_pte |
| 444 | .size arm1022_processor_functions, . - arm1022_processor_functions |
| 445 | |
| 446 | .section ".rodata" |
| 447 | |
| 448 | .type cpu_arch_name, #object |
| 449 | cpu_arch_name: |
| 450 | .asciz "armv5te" |
| 451 | .size cpu_arch_name, . - cpu_arch_name |
| 452 | |
| 453 | .type cpu_elf_name, #object |
| 454 | cpu_elf_name: |
| 455 | .asciz "v5" |
| 456 | .size cpu_elf_name, . - cpu_elf_name |
| 457 | |
| 458 | .type cpu_arm1022_name, #object |
| 459 | cpu_arm1022_name: |
Russell King | 264edb3 | 2006-06-29 15:03:09 +0100 | [diff] [blame] | 460 | .asciz "ARM1022" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | .size cpu_arm1022_name, . - cpu_arm1022_name |
| 462 | |
| 463 | .align |
| 464 | |
Ben Dooks | 02b7dd1 | 2005-09-20 16:35:03 +0100 | [diff] [blame] | 465 | .section ".proc.info.init", #alloc, #execinstr |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | |
| 467 | .type __arm1022_proc_info,#object |
| 468 | __arm1022_proc_info: |
| 469 | .long 0x4105a220 @ ARM 1022E (v5TE) |
| 470 | .long 0xff0ffff0 |
| 471 | .long PMD_TYPE_SECT | \ |
| 472 | PMD_BIT4 | \ |
| 473 | PMD_SECT_AP_WRITE | \ |
| 474 | PMD_SECT_AP_READ |
| 475 | b __arm1022_setup |
| 476 | .long cpu_arch_name |
| 477 | .long cpu_elf_name |
| 478 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP |
| 479 | .long cpu_arm1022_name |
| 480 | .long arm1022_processor_functions |
| 481 | .long v4wbi_tlb_fns |
| 482 | .long v4wb_user_fns |
| 483 | .long arm1022_cache_fns |
| 484 | .size __arm1022_proc_info, . - __arm1022_proc_info |