blob: 3b7f3ab116e3a102b04dd7fac889e1fb0759fd23 [file] [log] [blame]
Shawn Guo4dce82c2012-04-04 10:50:52 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/slab.h>
Shawn Guo01bf32e2012-06-26 16:58:09 +080022#include <linux/stmp_device.h>
Shawn Guo4dce82c2012-04-04 10:50:52 +080023
24#define SET 0x4
25#define CLR 0x8
26#define TOG 0xc
27
28#define PWM_CTRL 0x0
29#define PWM_ACTIVE0 0x10
30#define PWM_PERIOD0 0x20
31#define PERIOD_PERIOD(p) ((p) & 0xffff)
32#define PERIOD_PERIOD_MAX 0x10000
33#define PERIOD_ACTIVE_HIGH (3 << 16)
34#define PERIOD_INACTIVE_LOW (2 << 18)
35#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
36#define PERIOD_CDIV_MAX 8
37
38struct mxs_pwm_chip {
39 struct pwm_chip chip;
40 struct device *dev;
41 struct clk *clk;
42 void __iomem *base;
43};
44
45#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
46
47static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
48 int duty_ns, int period_ns)
49{
50 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
51 int ret, div = 0;
52 unsigned int period_cycles, duty_cycles;
53 unsigned long rate;
54 unsigned long long c;
55
56 rate = clk_get_rate(mxs->clk);
57 while (1) {
58 c = rate / (1 << div);
59 c = c * period_ns;
60 do_div(c, 1000000000);
61 if (c < PERIOD_PERIOD_MAX)
62 break;
63 div++;
64 if (div > PERIOD_CDIV_MAX)
65 return -EINVAL;
66 }
67
68 period_cycles = c;
69 c *= duty_ns;
70 do_div(c, period_ns);
71 duty_cycles = c;
72
73 /*
74 * If the PWM channel is disabled, make sure to turn on the clock
75 * before writing the register. Otherwise, keep it enabled.
76 */
77 if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
78 ret = clk_prepare_enable(mxs->clk);
79 if (ret)
80 return ret;
81 }
82
83 writel(duty_cycles << 16,
84 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
85 writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
86 PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
87 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
88
89 /*
90 * If the PWM is not enabled, turn the clock off again to save power.
91 */
92 if (!test_bit(PWMF_ENABLED, &pwm->flags))
93 clk_disable_unprepare(mxs->clk);
94
95 return 0;
96}
97
98static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
99{
100 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
101 int ret;
102
103 ret = clk_prepare_enable(mxs->clk);
104 if (ret)
105 return ret;
106
107 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
108
109 return 0;
110}
111
112static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
113{
114 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
115
116 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
117
118 clk_disable_unprepare(mxs->clk);
119}
120
121static const struct pwm_ops mxs_pwm_ops = {
122 .config = mxs_pwm_config,
123 .enable = mxs_pwm_enable,
124 .disable = mxs_pwm_disable,
125 .owner = THIS_MODULE,
126};
127
128static int mxs_pwm_probe(struct platform_device *pdev)
129{
130 struct device_node *np = pdev->dev.of_node;
131 struct mxs_pwm_chip *mxs;
Shawn Guo22d260b2012-06-26 16:58:10 +0800132 struct resource *res;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800133 int ret;
134
135 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
136 if (!mxs)
137 return -ENOMEM;
138
Shawn Guo22d260b2012-06-26 16:58:10 +0800139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
140 mxs->base = devm_request_and_ioremap(&pdev->dev, res);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800141 if (!mxs->base)
142 return -EADDRNOTAVAIL;
143
Shawn Guo22d260b2012-06-26 16:58:10 +0800144 mxs->clk = devm_clk_get(&pdev->dev, NULL);
145 if (IS_ERR(mxs->clk))
146 return PTR_ERR(mxs->clk);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800147
148 mxs->chip.dev = &pdev->dev;
149 mxs->chip.ops = &mxs_pwm_ops;
150 mxs->chip.base = -1;
151 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
152 if (ret < 0) {
153 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
Shawn Guo22d260b2012-06-26 16:58:10 +0800154 return ret;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800155 }
156
157 ret = pwmchip_add(&mxs->chip);
158 if (ret < 0) {
159 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
Shawn Guo22d260b2012-06-26 16:58:10 +0800160 return ret;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800161 }
162
163 mxs->dev = &pdev->dev;
164 platform_set_drvdata(pdev, mxs);
165
Shawn Guo01bf32e2012-06-26 16:58:09 +0800166 stmp_reset_block(mxs->base);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800167
168 return 0;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800169}
170
171static int __devexit mxs_pwm_remove(struct platform_device *pdev)
172{
173 struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
174
175 pwmchip_remove(&mxs->chip);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800176
177 return 0;
178}
179
180static struct of_device_id mxs_pwm_dt_ids[] = {
Shawn Guo071407e2012-06-26 16:58:08 +0800181 { .compatible = "fsl,imx23-pwm", },
Shawn Guo4dce82c2012-04-04 10:50:52 +0800182 { /* sentinel */ }
183};
184MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
185
186static struct platform_driver mxs_pwm_driver = {
187 .driver = {
188 .name = "mxs-pwm",
189 .of_match_table = of_match_ptr(mxs_pwm_dt_ids),
190 },
191 .probe = mxs_pwm_probe,
192 .remove = __devexit_p(mxs_pwm_remove),
193};
194module_platform_driver(mxs_pwm_driver);
195
196MODULE_ALIAS("platform:mxs-pwm");
197MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
198MODULE_DESCRIPTION("Freescale MXS PWM Driver");
199MODULE_LICENSE("GPL v2");