blob: 38a65c3e62fc247c39ecaff4853cfd45c3148168 [file] [log] [blame]
Soren Brinkmann0ee52b12013-05-13 10:46:37 -07001/*
2 * Zynq clock controller
3 *
4 * Copyright (C) 2012 - 2013 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License v2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/clk/zynq.h>
Stephen Boyd54024942015-06-19 15:00:46 -070022#include <linux/clk.h>
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070023#include <linux/clk-provider.h>
24#include <linux/of.h>
Michal Simekb0504e32013-11-18 16:48:19 +010025#include <linux/of_address.h>
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070026#include <linux/slab.h>
27#include <linux/string.h>
28#include <linux/io.h>
29
Michal Simekb0504e32013-11-18 16:48:19 +010030static void __iomem *zynq_clkc_base;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070031
Michal Simekb0504e32013-11-18 16:48:19 +010032#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
33#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
34#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
35#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
36#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
37#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
38#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
39#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
40#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
41#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
42#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
43#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
44#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
45#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
46#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
47#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
48#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
49#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
50#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
51#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
52#define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
53#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070054
55#define NUM_MIO_PINS 54
56
Soren Brinkmann9268beb2014-04-17 11:40:52 -070057#define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
58#define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
59
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070060enum zynq_clk {
61 armpll, ddrpll, iopll,
62 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
63 ddr2x, ddr3x, dci,
64 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
65 sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
66 usb0_aper, usb1_aper, gem0_aper, gem1_aper,
67 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
68 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
69 smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
70
71static struct clk *ps_clk;
72static struct clk *clks[clk_max];
73static struct clk_onecell_data clk_data;
74
75static DEFINE_SPINLOCK(armpll_lock);
76static DEFINE_SPINLOCK(ddrpll_lock);
77static DEFINE_SPINLOCK(iopll_lock);
78static DEFINE_SPINLOCK(armclk_lock);
Soren Brinkmann252957c2013-06-17 15:03:46 -070079static DEFINE_SPINLOCK(swdtclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070080static DEFINE_SPINLOCK(ddrclk_lock);
81static DEFINE_SPINLOCK(dciclk_lock);
82static DEFINE_SPINLOCK(gem0clk_lock);
83static DEFINE_SPINLOCK(gem1clk_lock);
84static DEFINE_SPINLOCK(canclk_lock);
85static DEFINE_SPINLOCK(canmioclk_lock);
86static DEFINE_SPINLOCK(dbgclk_lock);
87static DEFINE_SPINLOCK(aperclk_lock);
88
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +020089static const char *const armpll_parents[] __initconst = {"armpll_int",
90 "ps_clk"};
91static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
92 "ps_clk"};
93static const char *const iopll_parents[] __initconst = {"iopll_int",
94 "ps_clk"};
Uwe Kleine-König692d8322015-02-18 10:59:45 +010095static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
96static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +020097static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
Soren Brinkmann0ee52b12013-05-13 10:46:37 -070098 "can0_mio_mux"};
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +020099static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700100 "can1_mio_mux"};
Uwe Kleine-König692d8322015-02-18 10:59:45 +0100101static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
Soren Brinkmann8eaf5032014-09-02 16:02:09 -0700102 "dummy_name"};
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700103
Uwe Kleine-König4a1caed2015-05-28 10:45:51 +0200104static const char *const dbgtrc_emio_input_names[] __initconst = {
105 "trace_emio_clk"};
106static const char *const gem0_emio_input_names[] __initconst = {
107 "gem0_emio_clk"};
108static const char *const gem1_emio_input_names[] __initconst = {
109 "gem1_emio_clk"};
110static const char *const swdt_ext_clk_input_names[] __initconst = {
111 "swdt_ext_clk"};
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700112
113static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
114 const char *clk_name, void __iomem *fclk_ctrl_reg,
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800115 const char **parents, int enable)
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700116{
117 struct clk *clk;
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800118 u32 enable_reg;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700119 char *mux_name;
120 char *div0_name;
121 char *div1_name;
122 spinlock_t *fclk_lock;
123 spinlock_t *fclk_gate_lock;
124 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
125
126 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
127 if (!fclk_lock)
128 goto err;
129 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
130 if (!fclk_gate_lock)
Felipe Penaf8fe36f2013-10-07 23:25:44 -0300131 goto err_fclk_gate_lock;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700132 spin_lock_init(fclk_lock);
133 spin_lock_init(fclk_gate_lock);
134
135 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
Felipe Penaf8fe36f2013-10-07 23:25:44 -0300136 if (!mux_name)
137 goto err_mux_name;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700138 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
Felipe Penaf8fe36f2013-10-07 23:25:44 -0300139 if (!div0_name)
140 goto err_div0_name;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700141 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
Felipe Penaf8fe36f2013-10-07 23:25:44 -0300142 if (!div1_name)
143 goto err_div1_name;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700144
James Hogan819c1de2013-07-29 12:25:01 +0100145 clk = clk_register_mux(NULL, mux_name, parents, 4,
146 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
147 fclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700148
149 clk = clk_register_divider(NULL, div0_name, mux_name,
150 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
151 CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
152
153 clk = clk_register_divider(NULL, div1_name, div0_name,
154 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
155 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
156 fclk_lock);
157
158 clks[fclk] = clk_register_gate(NULL, clk_name,
159 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
160 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
Michal Simek2c97ec52014-02-20 09:55:46 +0100161 enable_reg = clk_readl(fclk_gate_reg) & 1;
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800162 if (enable && !enable_reg) {
163 if (clk_prepare_enable(clks[fclk]))
164 pr_warn("%s: FCLK%u enable failed\n", __func__,
165 fclk - fclk0);
166 }
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700167 kfree(mux_name);
168 kfree(div0_name);
169 kfree(div1_name);
170
171 return;
172
Felipe Penaf8fe36f2013-10-07 23:25:44 -0300173err_div1_name:
174 kfree(div0_name);
175err_div0_name:
176 kfree(mux_name);
177err_mux_name:
178 kfree(fclk_gate_lock);
179err_fclk_gate_lock:
180 kfree(fclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700181err:
182 clks[fclk] = ERR_PTR(-ENOMEM);
183}
184
185static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
186 enum zynq_clk clk1, const char *clk_name0,
187 const char *clk_name1, void __iomem *clk_ctrl,
188 const char **parents, unsigned int two_gates)
189{
190 struct clk *clk;
191 char *mux_name;
192 char *div_name;
193 spinlock_t *lock;
194
195 lock = kmalloc(sizeof(*lock), GFP_KERNEL);
196 if (!lock)
197 goto err;
198 spin_lock_init(lock);
199
200 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
201 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
202
James Hogan819c1de2013-07-29 12:25:01 +0100203 clk = clk_register_mux(NULL, mux_name, parents, 4,
204 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700205
206 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
207 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
208
209 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
210 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
211 if (two_gates)
212 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
213 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
214
215 kfree(mux_name);
216 kfree(div_name);
217
218 return;
219
220err:
221 clks[clk0] = ERR_PTR(-ENOMEM);
222 if (two_gates)
223 clks[clk1] = ERR_PTR(-ENOMEM);
224}
225
226static void __init zynq_clk_setup(struct device_node *np)
227{
228 int i;
229 u32 tmp;
230 int ret;
231 struct clk *clk;
232 char *clk_name;
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800233 unsigned int fclk_enable = 0;
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700234 const char *clk_output_name[clk_max];
235 const char *cpu_parents[4];
236 const char *periph_parents[4];
237 const char *swdt_ext_clk_mux_parents[2];
238 const char *can_mio_mux_parents[NUM_MIO_PINS];
Soren Brinkmann8eaf5032014-09-02 16:02:09 -0700239 const char *dummy_nm = "dummy_name";
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700240
241 pr_info("Zynq clock init\n");
242
243 /* get clock output names from DT */
244 for (i = 0; i < clk_max; i++) {
245 if (of_property_read_string_index(np, "clock-output-names",
246 i, &clk_output_name[i])) {
247 pr_err("%s: clock output name not in DT\n", __func__);
248 BUG();
249 }
250 }
251 cpu_parents[0] = clk_output_name[armpll];
252 cpu_parents[1] = clk_output_name[armpll];
253 cpu_parents[2] = clk_output_name[ddrpll];
254 cpu_parents[3] = clk_output_name[iopll];
255 periph_parents[0] = clk_output_name[iopll];
256 periph_parents[1] = clk_output_name[iopll];
257 periph_parents[2] = clk_output_name[armpll];
258 periph_parents[3] = clk_output_name[ddrpll];
259
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800260 of_property_read_u32(np, "fclk-enable", &fclk_enable);
261
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700262 /* ps_clk */
263 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
264 if (ret) {
265 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
266 tmp = 33333333;
267 }
268 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
269 tmp);
270
271 /* PLLs */
272 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
273 SLCR_PLL_STATUS, 0, &armpll_lock);
274 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
James Hogan819c1de2013-07-29 12:25:01 +0100275 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
276 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700277
278 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
279 SLCR_PLL_STATUS, 1, &ddrpll_lock);
280 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
James Hogan819c1de2013-07-29 12:25:01 +0100281 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
282 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700283
284 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
285 SLCR_PLL_STATUS, 2, &iopll_lock);
286 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
James Hogan819c1de2013-07-29 12:25:01 +0100287 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
288 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700289
290 /* CPU clocks */
Michal Simek2c97ec52014-02-20 09:55:46 +0100291 tmp = clk_readl(SLCR_621_TRUE) & 1;
James Hogan819c1de2013-07-29 12:25:01 +0100292 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
293 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
294 &armclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700295 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
296 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
297 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
298
299 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
300 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
301 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
302
303 clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
304 1, 2);
305 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
306 "cpu_3or2x_div", CLK_IGNORE_UNUSED,
307 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
308
309 clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
310 2 + tmp);
311 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
312 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
313 26, 0, &armclk_lock);
Soren Brinkmann3dccfec2015-01-27 11:05:27 -0800314 clk_prepare_enable(clks[cpu_2x]);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700315
316 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
317 4 + 2 * tmp);
318 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
319 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
320 0, &armclk_lock);
321
322 /* Timers */
323 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
324 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
325 int idx = of_property_match_string(np, "clock-names",
326 swdt_ext_clk_input_names[i]);
327 if (idx >= 0)
328 swdt_ext_clk_mux_parents[i + 1] =
329 of_clk_get_parent_name(np, idx);
330 else
331 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
332 }
333 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
James Hogan819c1de2013-07-29 12:25:01 +0100334 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
335 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700336 &swdtclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700337
338 /* DDR clocks */
339 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
340 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
341 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
342 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
343 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
344 clk_prepare_enable(clks[ddr2x]);
345 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
346 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
347 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
348 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
349 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
350 clk_prepare_enable(clks[ddr3x]);
351
352 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
353 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
354 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
355 clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
356 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
357 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
358 &dciclk_lock);
359 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
360 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
361 &dciclk_lock);
362 clk_prepare_enable(clks[dci]);
363
364 /* Peripheral clocks */
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800365 for (i = fclk0; i <= fclk3; i++) {
366 int enable = !!(fclk_enable & BIT(i - fclk0));
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700367 zynq_clk_register_fclk(i, clk_output_name[i],
368 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
Soren Brinkmannba52f8a2013-11-27 12:16:23 -0800369 periph_parents, enable);
370 }
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700371
372 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
373 SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
374
375 zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
376 SLCR_SMC_CLK_CTRL, periph_parents, 0);
377
378 zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
379 SLCR_PCAP_CLK_CTRL, periph_parents, 0);
380
381 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
382 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
383 periph_parents, 1);
384
385 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
386 clk_output_name[uart1], SLCR_UART_CLK_CTRL,
387 periph_parents, 1);
388
389 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
390 clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
391 periph_parents, 1);
392
393 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
394 int idx = of_property_match_string(np, "clock-names",
395 gem0_emio_input_names[i]);
396 if (idx >= 0)
397 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
398 idx);
399 }
James Hogan819c1de2013-07-29 12:25:01 +0100400 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
401 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
402 &gem0clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700403 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
404 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
405 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
406 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
407 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
408 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
409 &gem0clk_lock);
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700410 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700411 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
412 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700413 &gem0clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700414 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
415 "gem0_emio_mux", CLK_SET_RATE_PARENT,
416 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
417
418 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
419 int idx = of_property_match_string(np, "clock-names",
420 gem1_emio_input_names[i]);
421 if (idx >= 0)
422 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
423 idx);
424 }
James Hogan819c1de2013-07-29 12:25:01 +0100425 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
426 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
427 &gem1clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700428 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
429 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
430 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
431 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
432 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
433 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
434 &gem1clk_lock);
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700435 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
Linus Torvaldsbef4a0a2013-09-09 15:49:04 -0700436 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
437 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
Soren Brinkmann765b7d42013-06-17 15:47:40 -0700438 &gem1clk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700439 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
440 "gem1_emio_mux", CLK_SET_RATE_PARENT,
441 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
442
443 tmp = strlen("mio_clk_00x");
444 clk_name = kmalloc(tmp, GFP_KERNEL);
445 for (i = 0; i < NUM_MIO_PINS; i++) {
446 int idx;
447
448 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
449 idx = of_property_match_string(np, "clock-names", clk_name);
450 if (idx >= 0)
451 can_mio_mux_parents[i] = of_clk_get_parent_name(np,
452 idx);
453 else
454 can_mio_mux_parents[i] = dummy_nm;
455 }
456 kfree(clk_name);
James Hogan819c1de2013-07-29 12:25:01 +0100457 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
458 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
459 &canclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700460 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
461 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
462 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
463 clk = clk_register_divider(NULL, "can_div1", "can_div0",
464 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
465 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
466 &canclk_lock);
467 clk = clk_register_gate(NULL, "can0_gate", "can_div1",
468 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
469 &canclk_lock);
470 clk = clk_register_gate(NULL, "can1_gate", "can_div1",
471 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
472 &canclk_lock);
473 clk = clk_register_mux(NULL, "can0_mio_mux",
James Hogan819c1de2013-07-29 12:25:01 +0100474 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
475 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
476 &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700477 clk = clk_register_mux(NULL, "can1_mio_mux",
James Hogan819c1de2013-07-29 12:25:01 +0100478 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
479 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
480 0, &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700481 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
James Hogan819c1de2013-07-29 12:25:01 +0100482 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
483 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
484 &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700485 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
James Hogan819c1de2013-07-29 12:25:01 +0100486 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
487 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
488 0, &canmioclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700489
490 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
491 int idx = of_property_match_string(np, "clock-names",
492 dbgtrc_emio_input_names[i]);
493 if (idx >= 0)
494 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
495 idx);
496 }
James Hogan819c1de2013-07-29 12:25:01 +0100497 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
498 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
499 &dbgclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700500 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
501 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
502 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
James Hogan819c1de2013-07-29 12:25:01 +0100503 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
504 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
505 &dbgclk_lock);
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700506 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
507 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
508 0, 0, &dbgclk_lock);
509 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
510 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
511 &dbgclk_lock);
512
Soren Brinkmann9268beb2014-04-17 11:40:52 -0700513 /* leave debug clocks in the state the bootloader set them up to */
514 tmp = clk_readl(SLCR_DBG_CLK_CTRL);
515 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
516 if (clk_prepare_enable(clks[dbg_trc]))
517 pr_warn("%s: trace clk enable failed\n", __func__);
518 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
519 if (clk_prepare_enable(clks[dbg_apb]))
520 pr_warn("%s: debug APB clk enable failed\n", __func__);
521
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700522 /* One gated clock for all APER clocks. */
523 clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
524 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
525 &aperclk_lock);
526 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
527 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
528 &aperclk_lock);
529 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
530 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
531 &aperclk_lock);
532 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
533 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
534 &aperclk_lock);
535 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
536 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
537 &aperclk_lock);
538 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
539 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
540 &aperclk_lock);
541 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
542 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
543 &aperclk_lock);
544 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
545 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
546 &aperclk_lock);
547 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
548 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
549 &aperclk_lock);
550 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
551 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
552 &aperclk_lock);
553 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
554 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
555 &aperclk_lock);
556 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
557 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
558 &aperclk_lock);
559 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
560 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
561 &aperclk_lock);
562 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
563 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
564 &aperclk_lock);
565 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
566 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
567 &aperclk_lock);
568 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
569 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
570 &aperclk_lock);
571 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
572 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
573 &aperclk_lock);
574 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
575 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
576 &aperclk_lock);
577
578 for (i = 0; i < ARRAY_SIZE(clks); i++) {
579 if (IS_ERR(clks[i])) {
580 pr_err("Zynq clk %d: register failed with %ld\n",
581 i, PTR_ERR(clks[i]));
582 BUG();
583 }
584 }
585
586 clk_data.clks = clks;
587 clk_data.clk_num = ARRAY_SIZE(clks);
588 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
589}
590
591CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
592
Michal Simekb0504e32013-11-18 16:48:19 +0100593void __init zynq_clock_init(void)
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700594{
Michal Simekb0504e32013-11-18 16:48:19 +0100595 struct device_node *np;
596 struct device_node *slcr;
597 struct resource res;
598
599 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
600 if (!np) {
601 pr_err("%s: clkc node not found\n", __func__);
602 goto np_err;
603 }
604
605 if (of_address_to_resource(np, 0, &res)) {
606 pr_err("%s: failed to get resource\n", np->name);
607 goto np_err;
608 }
609
610 slcr = of_get_parent(np);
611
612 if (slcr->data) {
613 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
614 } else {
615 pr_err("%s: Unable to get I/O memory\n", np->name);
616 of_node_put(slcr);
617 goto np_err;
618 }
619
620 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
621
622 of_node_put(slcr);
623 of_node_put(np);
624
Michal Simekb0504e32013-11-18 16:48:19 +0100625 return;
626
627np_err:
628 of_node_put(np);
629 BUG();
Soren Brinkmann0ee52b12013-05-13 10:46:37 -0700630}