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Eric Miao5bf3df32009-01-20 11:04:16 +08001#ifndef __ASM_MACH_REGS_INTC_H
2#define __ASM_MACH_REGS_INTC_H
3
4#include <mach/hardware.h>
5
6/*
7 * Interrupt Controller
8 */
9
10#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
11#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
12#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
13#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
Haojian Zhuang6ba39282009-08-19 19:30:24 +080016#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
Eric Miao5bf3df32009-01-20 11:04:16 +080017
18#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
19#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
20#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
21#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
22#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
23
Haojian Zhuang6ba39282009-08-19 19:30:24 +080024#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
25#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
26#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
27#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
28#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
29
Eric Miao5bf3df32009-01-20 11:04:16 +080030#endif /* __ASM_MACH_REGS_INTC_H */