| Paul Mundt | f151749 | 2006-09-27 16:01:12 +0900 | [diff] [blame] | 1 | Notes on register bank usage in the kernel |
| 2 | ========================================== |
| 3 | |
| 4 | Introduction |
| 5 | ------------ |
| 6 | |
| 7 | The SH-3 and SH-4 CPU families traditionally include a single partial register |
| 8 | bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families |
| 9 | may have more full-featured banking or simply no such capabilities at all. |
| 10 | |
| 11 | SR.RB banking |
| 12 | ------------- |
| 13 | |
| 14 | In the case of this type of banking, banked registers are mapped directly to |
| 15 | r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc |
| 16 | can still be used to reference the banked registers (as r0_bank ... r7_bank) |
| 17 | when in the context of another bank. The developer must keep the SR.RB value |
| 18 | in mind when writing code that utilizes these banked registers, for obvious |
| 19 | reasons. Userspace is also not able to poke at the bank1 values, so these can |
| 20 | be used rather effectively as scratch registers by the kernel. |
| 21 | |
| 22 | Presently the kernel uses several of these registers. |
| 23 | |
| 24 | - r0_bank, r1_bank (referenced as k0 and k1, used for scratch |
| 25 | registers when doing exception handling). |
| 26 | - r2_bank (used to track the EXPEVT/INTEVT code) |
| 27 | - Used by do_IRQ() and friends for doing irq mapping based off |
| 28 | of the interrupt exception vector jump table offset |
| 29 | - r6_bank (global interrupt mask) |
| 30 | - The SR.IMASK interrupt handler makes use of this to set the |
| 31 | interrupt priority level (used by local_irq_enable()) |
| 32 | - r7_bank (current) |
| 33 | |