Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | Device Tree Clock bindings for arch-sunxi |
| 2 | |
| 3 | This binding uses the common clock binding[1]. |
| 4 | |
| 5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible : shall be one of the following: |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 9 | "allwinner,sun4i-osc-clk" - for a gatable oscillator |
| 10 | "allwinner,sun4i-pll1-clk" - for the main PLL clock |
| 11 | "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock |
| 12 | "allwinner,sun4i-axi-clk" - for the AXI clock |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 13 | "allwinner,sun4i-axi-gates-clk" - for the AXI gates |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 14 | "allwinner,sun4i-ahb-clk" - for the AHB clock |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 15 | "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 |
| 16 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame^] | 17 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 18 | "allwinner,sun4i-apb0-clk" - for the APB0 clock |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 19 | "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 |
| 20 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame^] | 21 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 22 | "allwinner,sun4i-apb1-clk" - for the APB1 clock |
| 23 | "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 24 | "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 |
| 25 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame^] | 26 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 27 | |
| 28 | Required properties for all clocks: |
| 29 | - reg : shall be the control register address for the clock. |
| 30 | - clocks : shall be the input parent clock(s) phandle for the clock |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 31 | - #clock-cells : from common clock binding; shall be set to 0 except for |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 32 | "allwinner,*-gates-clk" where it shall be set to 1 |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 33 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 34 | Additionally, "allwinner,*-gates-clk" clocks require: |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 35 | - clock-output-names : the corresponding gate names that the clock controls |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 36 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 37 | Clock consumers should specify the desired clocks they use with a |
| 38 | "clocks" phandle cell. Consumers that are using a gated clock should |
| 39 | provide an additional ID in their clock property. The values of this |
| 40 | ID are documented in sunxi/<soc>-gates.txt. |
| 41 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 42 | For example: |
| 43 | |
| 44 | osc24M: osc24M@01c20050 { |
| 45 | #clock-cells = <0>; |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 46 | compatible = "allwinner,sun4i-osc-clk"; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 47 | reg = <0x01c20050 0x4>; |
| 48 | clocks = <&osc24M_fixed>; |
| 49 | }; |
| 50 | |
| 51 | pll1: pll1@01c20000 { |
| 52 | #clock-cells = <0>; |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 53 | compatible = "allwinner,sun4i-pll1-clk"; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 54 | reg = <0x01c20000 0x4>; |
| 55 | clocks = <&osc24M>; |
| 56 | }; |
| 57 | |
| 58 | cpu: cpu@01c20054 { |
| 59 | #clock-cells = <0>; |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 60 | compatible = "allwinner,sun4i-cpu-clk"; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 61 | reg = <0x01c20054 0x4>; |
| 62 | clocks = <&osc32k>, <&osc24M>, <&pll1>; |
| 63 | }; |