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gerrit-public.fairphone.software / kernel / msm-4.9 / 2377feb4ce1cd42b7c1d266f466d69597d9dac7f / . / arch / blackfin / include / asm / mem_init.h
blob: 3cbc0f81ebf3aa6cb55dadb087e3cb58c0516e55 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]2 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]3 *
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]4 * Copyright 2004-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]5 *
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]6 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]7 */
8
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]9#if defined(EBIU_SDGCTL)
10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
16 defined(CONFIG_MEM_MT48LC32M16A2TG_75)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]17#if (CONFIG_SCLK_HZ > 119402985)
18#define SDRAM_tRP TRP_2
19#define SDRAM_tRP_num 2
20#define SDRAM_tRAS TRAS_7
21#define SDRAM_tRAS_num 7
22#define SDRAM_tRCD TRCD_2
23#define SDRAM_tWR TWR_2
24#endif
25#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
26#define SDRAM_tRP TRP_2
27#define SDRAM_tRP_num 2
28#define SDRAM_tRAS TRAS_6
29#define SDRAM_tRAS_num 6
30#define SDRAM_tRCD TRCD_2
31#define SDRAM_tWR TWR_2
32#endif
33#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_5
37#define SDRAM_tRAS_num 5
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_4
45#define SDRAM_tRAS_num 4
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_3
53#define SDRAM_tRAS_num 3
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
58#define SDRAM_tRP TRP_1
59#define SDRAM_tRP_num 1
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 3
62#define SDRAM_tRCD TRCD_1
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
66#define SDRAM_tRP TRP_1
67#define SDRAM_tRP_num 1
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_1
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_2
77#define SDRAM_tRAS_num 2
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ <= 29850746)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_1
85#define SDRAM_tRAS_num 1
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#endif
90
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]91#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
92 defined(CONFIG_MEM_MT48LC8M32B2B5_7)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]93 /*SDRAM INFORMATION: */
94#define SDRAM_Tref 64 /* Refresh period in milliseconds */
95#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
96#define SDRAM_CL CL_3
97#endif
98
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]99#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
100 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
101 defined(CONFIG_MEM_GENERIC_BOARD) || \
102 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
103 defined(CONFIG_MEM_MT48LC16M16A2TG_75)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]104 /*SDRAM INFORMATION: */
105#define SDRAM_Tref 64 /* Refresh period in milliseconds */
106#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
107#define SDRAM_CL CL_3
108#endif
109
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]110
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]111#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]112/* Equation from section 17 (p17-46) of BF533 HRM */
113#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
114
115/* Enable SCLK Out */
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]116#define mem_SDGCTL (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
117#else
118#define mem_SDRRC CONFIG_MEM_SDRRC
119#define mem_SDGCTL CONFIG_MEM_SDGCTL
120#endif
121#endif
122
123
124#if defined(EBIU_DDRCTL0)
125#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
126#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
127#define DDR_CLK_HZ(x) (1000*1000*1000/x)
128
129#if defined(CONFIG_MEM_MT46V32M16_6T)
130#define DDR_SIZE DEVSZ_512
131#define DDR_WIDTH DEVWD_16
132#define DDR_MAX_tCK 13
133
134#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
135#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
136#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
137#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
138#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
139
140#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
141#define DDR_tWTR DDR_TWTR(1)
142#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
143#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
144#endif
145
146#if defined(CONFIG_MEM_MT46V32M16_5B)
147#define DDR_SIZE DEVSZ_512
148#define DDR_WIDTH DEVWD_16
149#define DDR_MAX_tCK 13
150
151#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
152#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
153#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
154#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
155#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
156
157#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
158#define DDR_tWTR DDR_TWTR(2)
159#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
160#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
161#endif
162
163#if defined(CONFIG_MEM_GENERIC_BOARD)
164#define DDR_SIZE DEVSZ_512
165#define DDR_WIDTH DEVWD_16
166#define DDR_MAX_tCK 13
167
168#define DDR_tRCD DDR_TRCD(3)
169#define DDR_tWTR DDR_TWTR(2)
170#define DDR_tWR DDR_TWR(2)
171#define DDR_tMRD DDR_TMRD(2)
172#define DDR_tRP DDR_TRP(3)
173#define DDR_tRAS DDR_TRAS(7)
174#define DDR_tRC DDR_TRC(10)
175#define DDR_tRFC DDR_TRFC(12)
176#define DDR_tREFI DDR_TREFI(1288)
177#endif
178
179#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
180# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
181#elif(CONFIG_SCLK_HZ <= 133333333)
182# define DDR_CL CL_2
183#else
184# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
185#endif
186
187#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
188#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
189#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
190 | DDR_tMRD | DDR_tWR | DDR_tRCD)
191#define mem_DDRCTL2 DDR_CL
192#else
193#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
194#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
195#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
196#endif
197#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]198
199#if defined CONFIG_CLKIN_HALF
200#define CLKIN_HALF 1
201#else
202#define CLKIN_HALF 0
203#endif
204
205#if defined CONFIG_PLL_BYPASS
206#define PLL_BYPASS 1
207#else
208#define PLL_BYPASS 0
209#endif
210
211/***************************************Currently Not Being Used *********************************/
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]212
213#if defined(CONFIG_FLASH_SPEED_BWAT) && \
214defined(CONFIG_FLASH_SPEED_BRAT) && \
215defined(CONFIG_FLASH_SPEED_BHT) && \
216defined(CONFIG_FLASH_SPEED_BST) && \
217defined(CONFIG_FLASH_SPEED_BTT)
218
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]219#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
220#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
221#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
222#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
223#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
224
225#if (flash_EBIU_AMBCTL_TT > 3)
226#define flash_EBIU_AMBCTL0_TT B0TT_4
227#endif
228#if (flash_EBIU_AMBCTL_TT == 3)
229#define flash_EBIU_AMBCTL0_TT B0TT_3
230#endif
231#if (flash_EBIU_AMBCTL_TT == 2)
232#define flash_EBIU_AMBCTL0_TT B0TT_2
233#endif
234#if (flash_EBIU_AMBCTL_TT < 2)
235#define flash_EBIU_AMBCTL0_TT B0TT_1
236#endif
237
238#if (flash_EBIU_AMBCTL_ST > 3)
239#define flash_EBIU_AMBCTL0_ST B0ST_4
240#endif
241#if (flash_EBIU_AMBCTL_ST == 3)
242#define flash_EBIU_AMBCTL0_ST B0ST_3
243#endif
244#if (flash_EBIU_AMBCTL_ST == 2)
245#define flash_EBIU_AMBCTL0_ST B0ST_2
246#endif
247#if (flash_EBIU_AMBCTL_ST < 2)
248#define flash_EBIU_AMBCTL0_ST B0ST_1
249#endif
250
251#if (flash_EBIU_AMBCTL_HT > 2)
252#define flash_EBIU_AMBCTL0_HT B0HT_3
253#endif
254#if (flash_EBIU_AMBCTL_HT == 2)
255#define flash_EBIU_AMBCTL0_HT B0HT_2
256#endif
257#if (flash_EBIU_AMBCTL_HT == 1)
258#define flash_EBIU_AMBCTL0_HT B0HT_1
259#endif
260#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
261#define flash_EBIU_AMBCTL0_HT B0HT_0
262#endif
263#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
264#define flash_EBIU_AMBCTL0_HT B0HT_1
265#endif
266
267#if (flash_EBIU_AMBCTL_WAT > 14)
268#define flash_EBIU_AMBCTL0_WAT B0WAT_15
269#endif
270#if (flash_EBIU_AMBCTL_WAT == 14)
271#define flash_EBIU_AMBCTL0_WAT B0WAT_14
272#endif
273#if (flash_EBIU_AMBCTL_WAT == 13)
274#define flash_EBIU_AMBCTL0_WAT B0WAT_13
275#endif
276#if (flash_EBIU_AMBCTL_WAT == 12)
277#define flash_EBIU_AMBCTL0_WAT B0WAT_12
278#endif
279#if (flash_EBIU_AMBCTL_WAT == 11)
280#define flash_EBIU_AMBCTL0_WAT B0WAT_11
281#endif
282#if (flash_EBIU_AMBCTL_WAT == 10)
283#define flash_EBIU_AMBCTL0_WAT B0WAT_10
284#endif
285#if (flash_EBIU_AMBCTL_WAT == 9)
286#define flash_EBIU_AMBCTL0_WAT B0WAT_9
287#endif
288#if (flash_EBIU_AMBCTL_WAT == 8)
289#define flash_EBIU_AMBCTL0_WAT B0WAT_8
290#endif
291#if (flash_EBIU_AMBCTL_WAT == 7)
292#define flash_EBIU_AMBCTL0_WAT B0WAT_7
293#endif
294#if (flash_EBIU_AMBCTL_WAT == 6)
295#define flash_EBIU_AMBCTL0_WAT B0WAT_6
296#endif
297#if (flash_EBIU_AMBCTL_WAT == 5)
298#define flash_EBIU_AMBCTL0_WAT B0WAT_5
299#endif
300#if (flash_EBIU_AMBCTL_WAT == 4)
301#define flash_EBIU_AMBCTL0_WAT B0WAT_4
302#endif
303#if (flash_EBIU_AMBCTL_WAT == 3)
304#define flash_EBIU_AMBCTL0_WAT B0WAT_3
305#endif
306#if (flash_EBIU_AMBCTL_WAT == 2)
307#define flash_EBIU_AMBCTL0_WAT B0WAT_2
308#endif
309#if (flash_EBIU_AMBCTL_WAT == 1)
310#define flash_EBIU_AMBCTL0_WAT B0WAT_1
311#endif
312
313#if (flash_EBIU_AMBCTL_RAT > 14)
314#define flash_EBIU_AMBCTL0_RAT B0RAT_15
315#endif
316#if (flash_EBIU_AMBCTL_RAT == 14)
317#define flash_EBIU_AMBCTL0_RAT B0RAT_14
318#endif
319#if (flash_EBIU_AMBCTL_RAT == 13)
320#define flash_EBIU_AMBCTL0_RAT B0RAT_13
321#endif
322#if (flash_EBIU_AMBCTL_RAT == 12)
323#define flash_EBIU_AMBCTL0_RAT B0RAT_12
324#endif
325#if (flash_EBIU_AMBCTL_RAT == 11)
326#define flash_EBIU_AMBCTL0_RAT B0RAT_11
327#endif
328#if (flash_EBIU_AMBCTL_RAT == 10)
329#define flash_EBIU_AMBCTL0_RAT B0RAT_10
330#endif
331#if (flash_EBIU_AMBCTL_RAT == 9)
332#define flash_EBIU_AMBCTL0_RAT B0RAT_9
333#endif
334#if (flash_EBIU_AMBCTL_RAT == 8)
335#define flash_EBIU_AMBCTL0_RAT B0RAT_8
336#endif
337#if (flash_EBIU_AMBCTL_RAT == 7)
338#define flash_EBIU_AMBCTL0_RAT B0RAT_7
339#endif
340#if (flash_EBIU_AMBCTL_RAT == 6)
341#define flash_EBIU_AMBCTL0_RAT B0RAT_6
342#endif
343#if (flash_EBIU_AMBCTL_RAT == 5)
344#define flash_EBIU_AMBCTL0_RAT B0RAT_5
345#endif
346#if (flash_EBIU_AMBCTL_RAT == 4)
347#define flash_EBIU_AMBCTL0_RAT B0RAT_4
348#endif
349#if (flash_EBIU_AMBCTL_RAT == 3)
350#define flash_EBIU_AMBCTL0_RAT B0RAT_3
351#endif
352#if (flash_EBIU_AMBCTL_RAT == 2)
353#define flash_EBIU_AMBCTL0_RAT B0RAT_2
354#endif
355#if (flash_EBIU_AMBCTL_RAT == 1)
356#define flash_EBIU_AMBCTL0_RAT B0RAT_1
357#endif
358
359#define flash_EBIU_AMBCTL0 \
360 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
361 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]362#endif