blob: c8753da4c156ee9e2fa1b3b5ddfde63561733d30 [file] [log] [blame]
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +08001/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/irq.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040016#include <linux/irqchip.h>
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +080017#include <linux/irqdomain.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +080025struct mtk_sysirq_chip_data {
26 spinlock_t lock;
27 void __iomem *intpol_base;
28};
29
30static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
31{
32 irq_hw_number_t hwirq = data->hwirq;
33 struct mtk_sysirq_chip_data *chip_data = data->chip_data;
34 u32 offset, reg_index, value;
35 unsigned long flags;
36 int ret;
37
38 offset = hwirq & 0x1f;
39 reg_index = hwirq >> 5;
40
41 spin_lock_irqsave(&chip_data->lock, flags);
42 value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
43 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
44 if (type == IRQ_TYPE_LEVEL_LOW)
45 type = IRQ_TYPE_LEVEL_HIGH;
46 else
47 type = IRQ_TYPE_EDGE_RISING;
48 value |= (1 << offset);
49 } else {
50 value &= ~(1 << offset);
51 }
52 writel(value, chip_data->intpol_base + reg_index * 4);
53
54 data = data->parent_data;
55 ret = data->chip->irq_set_type(data, type);
56 spin_unlock_irqrestore(&chip_data->lock, flags);
57 return ret;
58}
59
60static struct irq_chip mtk_sysirq_chip = {
61 .name = "MT_SYSIRQ",
62 .irq_mask = irq_chip_mask_parent,
63 .irq_unmask = irq_chip_unmask_parent,
64 .irq_eoi = irq_chip_eoi_parent,
65 .irq_set_type = mtk_sysirq_set_type,
66 .irq_retrigger = irq_chip_retrigger_hierarchy,
67 .irq_set_affinity = irq_chip_set_affinity_parent,
68};
69
70static int mtk_sysirq_domain_xlate(struct irq_domain *d,
71 struct device_node *controller,
72 const u32 *intspec, unsigned int intsize,
73 unsigned long *out_hwirq,
74 unsigned int *out_type)
75{
76 if (intsize != 3)
77 return -EINVAL;
78
79 /* sysirq doesn't support PPI */
80 if (intspec[0])
81 return -EINVAL;
82
83 *out_hwirq = intspec[1];
84 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
85 return 0;
86}
87
88static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
89 unsigned int nr_irqs, void *arg)
90{
91 int i;
92 irq_hw_number_t hwirq;
93 struct of_phandle_args *irq_data = arg;
94 struct of_phandle_args gic_data = *irq_data;
95
96 if (irq_data->args_count != 3)
97 return -EINVAL;
98
99 /* sysirq doesn't support PPI */
100 if (irq_data->args[0])
101 return -EINVAL;
102
103 hwirq = irq_data->args[1];
104 for (i = 0; i < nr_irqs; i++)
105 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
106 &mtk_sysirq_chip,
107 domain->host_data);
108
109 gic_data.np = domain->parent->of_node;
110 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
111}
112
Krzysztof Kozlowski96009732015-04-27 21:54:24 +0900113static const struct irq_domain_ops sysirq_domain_ops = {
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800114 .xlate = mtk_sysirq_domain_xlate,
115 .alloc = mtk_sysirq_domain_alloc,
116 .free = irq_domain_free_irqs_common,
117};
118
119static int __init mtk_sysirq_of_init(struct device_node *node,
120 struct device_node *parent)
121{
122 struct irq_domain *domain, *domain_parent;
123 struct mtk_sysirq_chip_data *chip_data;
Yingjoe Chencdb647a2015-01-12 17:14:31 +0800124 int ret, size, intpol_num;
125 struct resource res;
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800126
127 domain_parent = irq_find_host(parent);
128 if (!domain_parent) {
129 pr_err("mtk_sysirq: interrupt-parent not found\n");
130 return -EINVAL;
131 }
132
Yingjoe Chencdb647a2015-01-12 17:14:31 +0800133 ret = of_address_to_resource(node, 0, &res);
134 if (ret)
135 return ret;
136
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800137 chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
138 if (!chip_data)
139 return -ENOMEM;
140
Yingjoe Chencdb647a2015-01-12 17:14:31 +0800141 size = resource_size(&res);
142 intpol_num = size * 8;
143 chip_data->intpol_base = ioremap(res.start, size);
144 if (!chip_data->intpol_base) {
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800145 pr_err("mtk_sysirq: unable to map sysirq register\n");
Axel Line1a96fb2015-05-21 22:57:34 +0800146 ret = -ENXIO;
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800147 goto out_free;
148 }
149
Yingjoe Chencdb647a2015-01-12 17:14:31 +0800150 domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
Yingjoe Chen5fe3bba2014-11-25 16:04:20 +0800151 &sysirq_domain_ops, chip_data);
152 if (!domain) {
153 ret = -ENOMEM;
154 goto out_unmap;
155 }
156 spin_lock_init(&chip_data->lock);
157
158 return 0;
159
160out_unmap:
161 iounmap(chip_data->intpol_base);
162out_free:
163 kfree(chip_data);
164 return ret;
165}
166IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);