blob: 5126f9e77a9883ceb4f8af0f24a46d17096e084c [file] [log] [blame]
Scott Brandenc9ad7bc2014-10-14 16:42:25 -07001/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34#include <dt-bindings/interrupt-controller/irq.h>
35
36#include "skeleton.dtsi"
37
38/ {
39 compatible = "brcm,cygnus";
40 model = "Broadcom Cygnus SoC";
41 interrupt-parent = <&gic>;
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x0>;
52 };
53 };
54
55 /include/ "bcm-cygnus-clock.dtsi"
56
57 amba {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "arm,amba-bus", "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges;
63
64 wdt@18009000 {
65 compatible = "arm,sp805" , "arm,primecell";
66 reg = <0x18009000 0x1000>;
67 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&axi81_clk>;
69 clock-names = "apb_pclk";
70 };
71 };
72
73 uart0: serial@18020000 {
74 compatible = "snps,dw-apb-uart";
75 reg = <0x18020000 0x100>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&axi81_clk>;
80 clock-frequency = <100000000>;
81 status = "disabled";
82 };
83
84 uart1: serial@18021000 {
85 compatible = "snps,dw-apb-uart";
86 reg = <0x18021000 0x100>;
87 reg-shift = <2>;
88 reg-io-width = <4>;
89 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&axi81_clk>;
91 clock-frequency = <100000000>;
92 status = "disabled";
93 };
94
95 uart2: serial@18022000 {
96 compatible = "snps,dw-apb-uart";
97 reg = <0x18020000 0x100>;
98 reg-shift = <2>;
99 reg-io-width = <4>;
100 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&axi81_clk>;
102 clock-frequency = <100000000>;
103 status = "disabled";
104 };
105
106 uart3: serial@18023000 {
107 compatible = "snps,dw-apb-uart";
108 reg = <0x18023000 0x100>;
109 reg-shift = <2>;
110 reg-io-width = <4>;
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&axi81_clk>;
113 clock-frequency = <100000000>;
114 status = "disabled";
115 };
116
117 gic: interrupt-controller@19021000 {
118 compatible = "arm,cortex-a9-gic";
119 #interrupt-cells = <3>;
120 #address-cells = <0>;
121 interrupt-controller;
122 reg = <0x19021000 0x1000>,
123 <0x19020100 0x100>;
124 };
125
126 L2: l2-cache {
127 compatible = "arm,pl310-cache";
128 reg = <0x19022000 0x1000>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 timer@19020200 {
134 compatible = "arm,cortex-a9-global-timer";
135 reg = <0x19020200 0x100>;
136 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&periph_clk>;
138 };
139
140};