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R Sricharan6e58b8f2013-08-14 19:08:20 +05301/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Rajendra Nayak38b248d2014-04-29 16:35:10 +053010#include "dra74x.dtsi"
Lokesh Vutlac7cc9ba2014-09-04 08:23:28 -050011#include <dt-bindings/gpio/gpio.h>
R Sricharan6e58b8f2013-08-14 19:08:20 +053012
13/ {
Rajendra Nayak38b248d2014-04-29 16:35:10 +053014 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
R Sricharan6e58b8f2013-08-14 19:08:20 +053016
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
Balaji T K6cf02db2013-10-07 21:55:04 +053021
22 mmc2_3v3: fixedregulator-mmc2 {
23 compatible = "regulator-fixed";
24 regulator-name = "mmc2_3v3";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 };
Lokesh Vutlac7cc9ba2014-09-04 08:23:28 -050028
29 vtt_fixed: fixedregulator-vtt {
30 compatible = "regulator-fixed";
31 regulator-name = "vtt_fixed";
32 regulator-min-microvolt = <1350000>;
33 regulator-max-microvolt = <1350000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
38 };
R Sricharan6e58b8f2013-08-14 19:08:20 +053039};
40
41&dra7_pmx_core {
Lokesh Vutlac7cc9ba2014-09-04 08:23:28 -050042 pinctrl-names = "default";
43 pinctrl-0 = <&vtt_pin>;
44
45 vtt_pin: pinmux_vtt_pin {
46 pinctrl-single,pins = <
47 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
48 >;
49 };
50
R Sricharan6e58b8f2013-08-14 19:08:20 +053051 i2c1_pins: pinmux_i2c1_pins {
52 pinctrl-single,pins = <
53 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
54 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
55 >;
56 };
57
58 i2c2_pins: pinmux_i2c2_pins {
59 pinctrl-single,pins = <
60 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
61 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
62 >;
63 };
64
65 i2c3_pins: pinmux_i2c3_pins {
66 pinctrl-single,pins = <
Roger Quadros544d63d2014-09-03 14:17:31 +030067 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
68 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
R Sricharan6e58b8f2013-08-14 19:08:20 +053069 >;
70 };
71
72 mcspi1_pins: pinmux_mcspi1_pins {
73 pinctrl-single,pins = <
Nishanth Menon68e4d9e2014-09-04 08:33:37 -050074 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
75 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
76 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
77 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
Nishanth Menon68e4d9e2014-09-04 08:33:37 -050078 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
79 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
R Sricharan6e58b8f2013-08-14 19:08:20 +053080 >;
81 };
82
83 mcspi2_pins: pinmux_mcspi2_pins {
84 pinctrl-single,pins = <
85 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
86 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
87 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
88 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
89 >;
90 };
91
92 uart1_pins: pinmux_uart1_pins {
93 pinctrl-single,pins = <
94 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
95 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
96 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
97 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
98 >;
99 };
100
101 uart2_pins: pinmux_uart2_pins {
102 pinctrl-single,pins = <
103 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
104 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
105 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
106 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
107 >;
108 };
109
110 uart3_pins: pinmux_uart3_pins {
111 pinctrl-single,pins = <
112 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
113 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
114 >;
115 };
Sourav Poddardc2dd5b2014-05-06 16:37:24 +0530116
117 qspi1_pins: pinmux_qspi1_pins {
118 pinctrl-single,pins = <
119 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
120 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
121 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
122 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
123 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
124 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
125 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
126 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
127 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
128 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
129 >;
130 };
Roger Quadros4b4437c2014-05-14 10:58:13 +0300131
132 usb1_pins: pinmux_usb1_pins {
133 pinctrl-single,pins = <
134 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
135 >;
136 };
137
138 usb2_pins: pinmux_usb2_pins {
139 pinctrl-single,pins = <
140 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
141 >;
142 };
Minal Shahff66a3c2014-05-19 14:45:47 +0530143
144 nand_flash_x16: nand_flash_x16 {
145 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
146 * So NAND flash requires following switch settings:
147 * SW5.9 (GPMC_WPN) = LOW
148 * SW5.1 (NAND_BOOTn) = HIGH */
149 pinctrl-single,pins = <
150 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
151 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
152 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
153 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
154 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
155 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
156 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
157 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
158 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
159 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
160 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
161 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
162 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
163 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
164 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
165 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
166 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
167 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
168 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
169 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
170 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
172 >;
173 };
Mugunthan V N8d039292014-10-21 15:31:01 +0530174
175 cpsw_default: cpsw_default {
176 pinctrl-single,pins = <
177 /* Slave 1 */
178 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190
191 /* Slave 2 */
192 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204 >;
205
206 };
207
208 cpsw_sleep: cpsw_sleep {
209 pinctrl-single,pins = <
210 /* Slave 1 */
211 0x250 (MUX_MODE15)
212 0x254 (MUX_MODE15)
213 0x258 (MUX_MODE15)
214 0x25c (MUX_MODE15)
215 0x260 (MUX_MODE15)
216 0x264 (MUX_MODE15)
217 0x268 (MUX_MODE15)
218 0x26c (MUX_MODE15)
219 0x270 (MUX_MODE15)
220 0x274 (MUX_MODE15)
221 0x278 (MUX_MODE15)
222 0x27c (MUX_MODE15)
223
224 /* Slave 2 */
225 0x198 (MUX_MODE15)
226 0x19c (MUX_MODE15)
227 0x1a0 (MUX_MODE15)
228 0x1a4 (MUX_MODE15)
229 0x1a8 (MUX_MODE15)
230 0x1ac (MUX_MODE15)
231 0x1b0 (MUX_MODE15)
232 0x1b4 (MUX_MODE15)
233 0x1b8 (MUX_MODE15)
234 0x1bc (MUX_MODE15)
235 0x1c0 (MUX_MODE15)
236 0x1c4 (MUX_MODE15)
237 >;
238 };
239
240 davinci_mdio_default: davinci_mdio_default {
241 pinctrl-single,pins = <
242 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
243 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
244 >;
245 };
246
247 davinci_mdio_sleep: davinci_mdio_sleep {
248 pinctrl-single,pins = <
249 0x23c (MUX_MODE15)
250 0x240 (MUX_MODE15)
251 >;
252 };
253
Roger Quadrosb41502e2014-08-15 16:09:19 +0300254 dcan1_pins_default: dcan1_pins_default {
255 pinctrl-single,pins = <
256 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
257 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
258 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
259 >;
260 };
261
262 dcan1_pins_sleep: dcan1_pins_sleep {
263 pinctrl-single,pins = <
264 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
265 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
266 0x418 (MUX_MODE15) /* wakeup0.off */
267 >;
268 };
R Sricharan6e58b8f2013-08-14 19:08:20 +0530269};
270
271&i2c1 {
272 status = "okay";
273 pinctrl-names = "default";
274 pinctrl-0 = <&i2c1_pins>;
275 clock-frequency = <400000>;
Keerthyc56a8312013-08-26 11:06:51 +0530276
277 tps659038: tps659038@58 {
278 compatible = "ti,tps659038";
279 reg = <0x58>;
280
281 tps659038_pmic {
282 compatible = "ti,tps659038-pmic";
283
284 regulators {
285 smps123_reg: smps123 {
286 /* VDD_MPU */
287 regulator-name = "smps123";
288 regulator-min-microvolt = < 850000>;
289 regulator-max-microvolt = <1250000>;
290 regulator-always-on;
291 regulator-boot-on;
292 };
293
294 smps45_reg: smps45 {
295 /* VDD_DSPEVE */
296 regulator-name = "smps45";
297 regulator-min-microvolt = < 850000>;
298 regulator-max-microvolt = <1150000>;
Nishanth Menon395b23c2014-10-21 09:38:10 -0500299 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530300 regulator-boot-on;
301 };
302
303 smps6_reg: smps6 {
304 /* VDD_GPU - over VDD_SMPS6 */
305 regulator-name = "smps6";
306 regulator-min-microvolt = <850000>;
Ravikumar Kattekolad114e852014-12-03 17:33:56 +0530307 regulator-max-microvolt = <1250000>;
Nishanth Menon395b23c2014-10-21 09:38:10 -0500308 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530309 regulator-boot-on;
310 };
311
312 smps7_reg: smps7 {
313 /* CORE_VDD */
314 regulator-name = "smps7";
315 regulator-min-microvolt = <850000>;
Ravikumar Kattekola70fcaf92014-12-03 17:33:57 +0530316 regulator-max-microvolt = <1060000>;
Keerthyc56a8312013-08-26 11:06:51 +0530317 regulator-always-on;
318 regulator-boot-on;
319 };
320
321 smps8_reg: smps8 {
322 /* VDD_IVAHD */
323 regulator-name = "smps8";
324 regulator-min-microvolt = < 850000>;
325 regulator-max-microvolt = <1250000>;
Nishanth Menon395b23c2014-10-21 09:38:10 -0500326 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530327 regulator-boot-on;
328 };
329
330 smps9_reg: smps9 {
331 /* VDDS1V8 */
332 regulator-name = "smps9";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <1800000>;
335 regulator-always-on;
336 regulator-boot-on;
337 };
338
339 ldo1_reg: ldo1 {
340 /* LDO1_OUT --> SDIO */
341 regulator-name = "ldo1";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <3300000>;
344 regulator-boot-on;
345 };
346
347 ldo2_reg: ldo2 {
348 /* VDD_RTCIO */
349 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
350 regulator-name = "ldo2";
351 regulator-min-microvolt = <3300000>;
352 regulator-max-microvolt = <3300000>;
Nishanth Menon395b23c2014-10-21 09:38:10 -0500353 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530354 regulator-boot-on;
355 };
356
357 ldo3_reg: ldo3 {
358 /* VDDA_1V8_PHY */
359 regulator-name = "ldo3";
360 regulator-min-microvolt = <1800000>;
361 regulator-max-microvolt = <1800000>;
Roger Quadrose120fb42014-07-04 12:55:43 +0300362 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530363 regulator-boot-on;
364 };
365
366 ldo9_reg: ldo9 {
367 /* VDD_RTC */
368 regulator-name = "ldo9";
369 regulator-min-microvolt = <1050000>;
370 regulator-max-microvolt = <1050000>;
Nishanth Menon395b23c2014-10-21 09:38:10 -0500371 regulator-always-on;
Keerthyc56a8312013-08-26 11:06:51 +0530372 regulator-boot-on;
373 };
374
375 ldoln_reg: ldoln {
376 /* VDDA_1V8_PLL */
377 regulator-name = "ldoln";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 regulator-always-on;
381 regulator-boot-on;
382 };
383
384 ldousb_reg: ldousb {
385 /* VDDA_3V_USB: VDDA_USBHS33 */
386 regulator-name = "ldousb";
387 regulator-min-microvolt = <3300000>;
388 regulator-max-microvolt = <3300000>;
389 regulator-boot-on;
390 };
391 };
392 };
393 };
R Sricharan6e58b8f2013-08-14 19:08:20 +0530394};
395
396&i2c2 {
397 status = "okay";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c2_pins>;
400 clock-frequency = <400000>;
401};
402
403&i2c3 {
404 status = "okay";
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c3_pins>;
Roger Quadros544d63d2014-09-03 14:17:31 +0300407 clock-frequency = <400000>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530408};
409
410&mcspi1 {
411 status = "okay";
412 pinctrl-names = "default";
413 pinctrl-0 = <&mcspi1_pins>;
414};
415
416&mcspi2 {
417 status = "okay";
418 pinctrl-names = "default";
419 pinctrl-0 = <&mcspi2_pins>;
420};
421
422&uart1 {
423 status = "okay";
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart1_pins>;
Nishanth Menon66b04362014-06-06 20:53:22 -0500426 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
427 <&dra7_pmx_core 0x3e0>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530428};
429
430&uart2 {
431 status = "okay";
432 pinctrl-names = "default";
433 pinctrl-0 = <&uart2_pins>;
434};
435
436&uart3 {
437 status = "okay";
438 pinctrl-names = "default";
439 pinctrl-0 = <&uart3_pins>;
440};
Balaji T Kbf1788d2013-10-07 21:55:03 +0530441
442&mmc1 {
443 status = "okay";
444 vmmc-supply = <&ldo1_reg>;
445 bus-width = <4>;
446};
Balaji T K6cf02db2013-10-07 21:55:04 +0530447
448&mmc2 {
449 status = "okay";
450 vmmc-supply = <&mmc2_3v3>;
451 bus-width = <8>;
452};
J Keerthy22f1e7e2013-10-16 10:39:05 -0500453
454&cpu0 {
455 cpu0-supply = <&smps123_reg>;
456};
Sourav Poddardc2dd5b2014-05-06 16:37:24 +0530457
458&qspi {
459 status = "okay";
460 pinctrl-names = "default";
461 pinctrl-0 = <&qspi1_pins>;
462
463 spi-max-frequency = <48000000>;
464 m25p80@0 {
465 compatible = "s25fl256s1";
466 spi-max-frequency = <48000000>;
467 reg = <0>;
468 spi-tx-bus-width = <1>;
469 spi-rx-bus-width = <4>;
470 spi-cpol;
471 spi-cpha;
472 #address-cells = <1>;
473 #size-cells = <1>;
474
475 /* MTD partition table.
476 * The ROM checks the first four physical blocks
477 * for a valid file to boot and the flash here is
478 * 64KiB block size.
479 */
480 partition@0 {
481 label = "QSPI.SPL";
482 reg = <0x00000000 0x000010000>;
483 };
484 partition@1 {
485 label = "QSPI.SPL.backup1";
486 reg = <0x00010000 0x00010000>;
487 };
488 partition@2 {
489 label = "QSPI.SPL.backup2";
490 reg = <0x00020000 0x00010000>;
491 };
492 partition@3 {
493 label = "QSPI.SPL.backup3";
494 reg = <0x00030000 0x00010000>;
495 };
496 partition@4 {
497 label = "QSPI.u-boot";
498 reg = <0x00040000 0x00100000>;
499 };
500 partition@5 {
501 label = "QSPI.u-boot-spl-os";
502 reg = <0x00140000 0x00010000>;
503 };
504 partition@6 {
505 label = "QSPI.u-boot-env";
506 reg = <0x00150000 0x00010000>;
507 };
508 partition@7 {
509 label = "QSPI.u-boot-env.backup1";
510 reg = <0x00160000 0x0010000>;
511 };
512 partition@8 {
513 label = "QSPI.kernel";
514 reg = <0x00170000 0x0800000>;
515 };
516 partition@9 {
517 label = "QSPI.file-system";
518 reg = <0x00970000 0x01690000>;
519 };
520 };
521};
Roger Quadros4b4437c2014-05-14 10:58:13 +0300522
523&usb1 {
524 dr_mode = "peripheral";
525 pinctrl-names = "default";
526 pinctrl-0 = <&usb1_pins>;
527};
528
529&usb2 {
530 dr_mode = "host";
531 pinctrl-names = "default";
532 pinctrl-0 = <&usb2_pins>;
533};
Minal Shahff66a3c2014-05-19 14:45:47 +0530534
535&elm {
536 status = "okay";
537};
538
539&gpmc {
540 status = "okay";
541 pinctrl-names = "default";
542 pinctrl-0 = <&nand_flash_x16>;
543 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
544 nand@0,0 {
545 reg = <0 0 4>; /* device IO registers */
546 ti,nand-ecc-opt = "bch8";
547 ti,elm-id = <&elm>;
548 nand-bus-width = <16>;
549 gpmc,device-width = <2>;
550 gpmc,sync-clk-ps = <0>;
551 gpmc,cs-on-ns = <0>;
Roger Quadros59900472014-09-10 08:57:11 -0700552 gpmc,cs-rd-off-ns = <80>;
553 gpmc,cs-wr-off-ns = <80>;
Minal Shahff66a3c2014-05-19 14:45:47 +0530554 gpmc,adv-on-ns = <0>;
Roger Quadros59900472014-09-10 08:57:11 -0700555 gpmc,adv-rd-off-ns = <60>;
556 gpmc,adv-wr-off-ns = <60>;
557 gpmc,we-on-ns = <10>;
558 gpmc,we-off-ns = <50>;
559 gpmc,oe-on-ns = <4>;
560 gpmc,oe-off-ns = <40>;
561 gpmc,access-ns = <40>;
562 gpmc,wr-access-ns = <80>;
563 gpmc,rd-cycle-ns = <80>;
564 gpmc,wr-cycle-ns = <80>;
Minal Shahff66a3c2014-05-19 14:45:47 +0530565 gpmc,bus-turnaround-ns = <0>;
566 gpmc,cycle2cycle-delay-ns = <0>;
567 gpmc,clk-activation-ns = <0>;
568 gpmc,wait-monitoring-ns = <0>;
569 gpmc,wr-data-mux-bus-ns = <0>;
570 /* MTD partition table */
571 /* All SPL-* partitions are sized to minimal length
572 * which can be independently programmable. For
573 * NAND flash this is equal to size of erase-block */
574 #address-cells = <1>;
575 #size-cells = <1>;
576 partition@0 {
577 label = "NAND.SPL";
578 reg = <0x00000000 0x000020000>;
579 };
580 partition@1 {
581 label = "NAND.SPL.backup1";
582 reg = <0x00020000 0x00020000>;
583 };
584 partition@2 {
585 label = "NAND.SPL.backup2";
586 reg = <0x00040000 0x00020000>;
587 };
588 partition@3 {
589 label = "NAND.SPL.backup3";
590 reg = <0x00060000 0x00020000>;
591 };
592 partition@4 {
593 label = "NAND.u-boot-spl-os";
594 reg = <0x00080000 0x00040000>;
595 };
596 partition@5 {
597 label = "NAND.u-boot";
598 reg = <0x000c0000 0x00100000>;
599 };
600 partition@6 {
601 label = "NAND.u-boot-env";
602 reg = <0x001c0000 0x00020000>;
603 };
604 partition@7 {
Roger Quadrosf0e9fab2014-09-03 14:17:32 +0300605 label = "NAND.u-boot-env.backup1";
Minal Shahff66a3c2014-05-19 14:45:47 +0530606 reg = <0x001e0000 0x00020000>;
607 };
608 partition@8 {
609 label = "NAND.kernel";
610 reg = <0x00200000 0x00800000>;
611 };
612 partition@9 {
613 label = "NAND.file-system";
614 reg = <0x00a00000 0x0f600000>;
615 };
616 };
617};
Roger Quadrosae28ea82014-06-30 14:00:38 +0300618
619&usb2_phy1 {
620 phy-supply = <&ldousb_reg>;
621};
622
623&usb2_phy2 {
624 phy-supply = <&ldousb_reg>;
625};
Lokesh Vutlac7cc9ba2014-09-04 08:23:28 -0500626
627&gpio7 {
628 ti,no-reset-on-init;
629 ti,no-idle-on-init;
630};
Mugunthan V N8d039292014-10-21 15:31:01 +0530631
632&mac {
633 status = "okay";
634 pinctrl-names = "default", "sleep";
635 pinctrl-0 = <&cpsw_default>;
636 pinctrl-1 = <&cpsw_sleep>;
637 dual_emac;
638};
639
640&cpsw_emac0 {
641 phy_id = <&davinci_mdio>, <2>;
642 phy-mode = "rgmii";
643 dual_emac_res_vlan = <1>;
644};
645
646&cpsw_emac1 {
647 phy_id = <&davinci_mdio>, <3>;
648 phy-mode = "rgmii";
649 dual_emac_res_vlan = <2>;
650};
651
652&davinci_mdio {
653 pinctrl-names = "default", "sleep";
654 pinctrl-0 = <&davinci_mdio_default>;
655 pinctrl-1 = <&davinci_mdio_sleep>;
656};
Roger Quadrosb41502e2014-08-15 16:09:19 +0300657
658&dcan1 {
659 status = "ok";
660 pinctrl-names = "default", "sleep";
661 pinctrl-0 = <&dcan1_pins_default>;
662 pinctrl-1 = <&dcan1_pins_sleep>;
663};