Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __KGSL_GMU_H |
| 14 | #define __KGSL_GMU_H |
| 15 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 16 | #include "kgsl_hfi.h" |
| 17 | |
| 18 | #define FW_VER_MAJOR(ver) (((ver)>>28) & 0xFF) |
| 19 | #define FW_VER_MINOR(ver) (((ver)>>16) & 0xFFF) |
| 20 | #define FW_VERSION(major, minor) \ |
| 21 | (((major) << 28) | (((minor) & 0xFFF) << 16)) |
| 22 | |
| 23 | #define GMU_INT_WDOG_BITE BIT(0) |
| 24 | #define GMU_INT_RSCC_COMP BIT(1) |
| 25 | #define GMU_INT_DBD_WAKEUP BIT(4) |
| 26 | #define GMU_INT_HOST_AHB_BUS_ERR BIT(5) |
| 27 | #define GMU_AO_INT_MASK \ |
| 28 | (GMU_INT_WDOG_BITE | \ |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 29 | GMU_INT_HOST_AHB_BUS_ERR) |
| 30 | |
| 31 | #define MAX_GMUFW_SIZE 0x2000 /* in dwords */ |
| 32 | #define FENCE_RANGE_MASK ((0x1 << 31) | (0x0A << 18) | (0x8A0)) |
| 33 | |
| 34 | /* Bitmask for GPU low power mode enabling and hysterisis*/ |
| 35 | #define SPTP_ENABLE_MASK (BIT(2) | BIT(0)) |
| 36 | #define IFPC_ENABLE_MASK (BIT(1) | BIT(0)) |
| 37 | #define HW_NAP_ENABLE_MASK BIT(0) |
| 38 | #define MIN_BW_ENABLE_MASK BIT(12) |
| 39 | #define MIN_BW_HYST 0xFA0 |
| 40 | |
| 41 | /* Bitmask for RPMH capability enabling */ |
| 42 | #define RPMH_INTERFACE_ENABLE BIT(0) |
| 43 | #define LLC_VOTE_ENABLE BIT(4) |
| 44 | #define DDR_VOTE_ENABLE BIT(8) |
| 45 | #define MX_VOTE_ENABLE BIT(9) |
| 46 | #define CX_VOTE_ENABLE BIT(10) |
| 47 | #define GFX_VOTE_ENABLE BIT(11) |
| 48 | #define RPMH_ENABLE_MASK (RPMH_INTERFACE_ENABLE | \ |
| 49 | LLC_VOTE_ENABLE | \ |
| 50 | DDR_VOTE_ENABLE | \ |
| 51 | MX_VOTE_ENABLE | \ |
| 52 | CX_VOTE_ENABLE | \ |
| 53 | GFX_VOTE_ENABLE) |
| 54 | |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 55 | /* Bitmask for GPU idle status check */ |
| 56 | #define GPUBUSYIGNAHB BIT(23) |
| 57 | #define CXGXCPUBUSYIGNAHB BIT(30) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 58 | |
| 59 | /* Constants for GMU OOBs */ |
| 60 | #define OOB_BOOT_OPTION 0 |
| 61 | #define OOB_SLUMBER_OPTION 1 |
| 62 | |
| 63 | /* Bitmasks for GMU OOBs */ |
| 64 | #define OOB_BOOT_SLUMBER_SET_MASK BIT(22) |
| 65 | #define OOB_BOOT_SLUMBER_CHECK_MASK BIT(30) |
| 66 | #define OOB_BOOT_SLUMBER_CLEAR_MASK BIT(30) |
| 67 | #define OOB_DCVS_SET_MASK BIT(23) |
| 68 | #define OOB_DCVS_CHECK_MASK BIT(31) |
| 69 | #define OOB_DCVS_CLEAR_MASK BIT(31) |
| 70 | #define OOB_CPINIT_SET_MASK BIT(16) |
| 71 | #define OOB_CPINIT_CHECK_MASK BIT(24) |
| 72 | #define OOB_CPINIT_CLEAR_MASK BIT(24) |
Carter Cooper | 05f2a6b | 2017-03-20 11:43:11 -0600 | [diff] [blame] | 73 | #define OOB_PERFCNTR_SET_MASK BIT(17) |
| 74 | #define OOB_PERFCNTR_CHECK_MASK BIT(25) |
| 75 | #define OOB_PERFCNTR_CLEAR_MASK BIT(25) |
Carter Cooper | a2a1298 | 2017-05-02 08:43:15 -0600 | [diff] [blame] | 76 | #define OOB_GPUSTART_SET_MASK BIT(18) |
| 77 | #define OOB_GPUSTART_CHECK_MASK BIT(26) |
| 78 | #define OOB_GPUSTART_CLEAR_MASK BIT(26) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 79 | |
| 80 | /* Bits for the flags field in the gmu structure */ |
| 81 | enum gmu_flags { |
| 82 | GMU_BOOT_INIT_DONE = 0, |
| 83 | GMU_CLK_ON = 1, |
| 84 | GMU_HFI_ON = 2, |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 85 | GMU_FAULT = 3 |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | /** |
| 89 | * struct gmu_memdesc - Gmu shared memory object descriptor |
| 90 | * @hostptr: Kernel virtual address |
| 91 | * @gmuaddr: GPU virtual address |
| 92 | * @physaddr: Physical address of the memory object |
| 93 | * @size: Size of the memory object |
| 94 | * @attr: memory attributes for this memory |
| 95 | */ |
| 96 | struct gmu_memdesc { |
| 97 | void *hostptr; |
| 98 | uint64_t gmuaddr; |
| 99 | phys_addr_t physaddr; |
| 100 | uint64_t size; |
| 101 | uint32_t attr; |
| 102 | }; |
| 103 | |
| 104 | struct gmu_bw_votes { |
| 105 | uint32_t cmds_wait_bitmask; |
| 106 | uint32_t cmds_per_bw_vote; |
| 107 | uint32_t cmd_addrs[MAX_BW_CMDS]; |
| 108 | uint32_t cmd_data[MAX_GX_LEVELS][MAX_BW_CMDS]; |
| 109 | }; |
| 110 | |
| 111 | struct rpmh_votes_t { |
| 112 | struct arc_vote_desc gx_votes[MAX_GX_LEVELS]; |
| 113 | struct arc_vote_desc cx_votes[MAX_CX_LEVELS]; |
| 114 | struct gmu_bw_votes ddr_votes; |
| 115 | struct gmu_bw_votes cnoc_votes; |
| 116 | }; |
| 117 | |
| 118 | #define MAX_GMU_CLKS 6 |
| 119 | #define DEFAULT_GMU_FREQ_IDX 1 |
| 120 | |
| 121 | /* |
| 122 | * These are the different ways the GMU can boot. GMU_WARM_BOOT is waking up |
| 123 | * from slumber. GMU_COLD_BOOT is booting for the first time. GMU_RESET |
| 124 | * is a soft reset of the GMU. |
| 125 | */ |
| 126 | enum gmu_boot { |
| 127 | GMU_WARM_BOOT = 0, |
| 128 | GMU_COLD_BOOT = 1, |
| 129 | GMU_RESET = 2 |
| 130 | }; |
| 131 | |
| 132 | enum gmu_load_mode { |
| 133 | CACHED_LOAD_BOOT, |
| 134 | CACHED_BOOT, |
| 135 | TCM_BOOT, |
| 136 | TCM_LOAD_BOOT, |
| 137 | INVALID_LOAD |
| 138 | }; |
| 139 | |
| 140 | enum gmu_pwrctrl_mode { |
| 141 | GMU_FW_START, |
| 142 | GMU_FW_STOP, |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 143 | GMU_SUSPEND, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 144 | GMU_DCVS_NOHFI, |
| 145 | GMU_NOTIFY_SLUMBER, |
| 146 | INVALID_POWER_CTRL |
| 147 | }; |
| 148 | |
| 149 | enum gpu_idle_level { |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 150 | GPU_HW_ACTIVE = 0x0, |
| 151 | GPU_HW_SPTP_PC = 0x2, |
| 152 | GPU_HW_IFPC = 0x3, |
| 153 | GPU_HW_NAP = 0x4, |
| 154 | GPU_HW_MIN_VOLT = 0x5, |
| 155 | GPU_HW_MIN_DDR = 0x6, |
Kyle Piefer | c96ad95 | 2017-05-02 13:35:45 -0700 | [diff] [blame] | 156 | GPU_HW_SLUMBER = 0xF |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | /** |
| 160 | * struct gmu_device - GMU device structure |
| 161 | * @ver: GMU FW version, read from GMU |
| 162 | * @reg_phys: GMU CSR physical address |
| 163 | * @reg_virt: GMU CSR virtual address |
| 164 | * @reg_len: GMU CSR range |
| 165 | * @gmu2gpu_offset: address difference between GMU register set |
| 166 | * and GPU register set, the offset will be used when accessing |
| 167 | * gmu registers using offset defined in GPU register space. |
| 168 | * @pdc_reg_virt: starting kernel virtual address for RPMh PDC registers |
| 169 | * @gmu_interrupt_num: GMU interrupt number |
| 170 | * @fw_image: descriptor of GMU memory that has GMU image in it |
| 171 | * @hfi_mem: pointer to HFI shared memory |
| 172 | * @dump_mem: pointer to GMU debug dump memory |
| 173 | * @hfi: HFI controller |
| 174 | * @lm_config: GPU LM configuration data |
| 175 | * @lm_dcvs_level: Minimal DCVS level that enable LM. LM disable in |
| 176 | * lower levels |
| 177 | * @bcl_config: Battery Current Limit configuration data |
| 178 | * @gmu_freqs: GMU frequency table with lowest freq at index 0 |
| 179 | * @gpu_freqs: GPU frequency table with lowest freq at index 0 |
| 180 | * @num_gmupwrlevels: number GMU frequencies in GMU freq table |
| 181 | * @num_gpupwrlevels: number GPU frequencies in GPU freq table |
| 182 | * @num_bwlevel: number of GPU BW levels |
| 183 | * @num_cnocbwlevel: number CNOC BW levels |
| 184 | * @rpmh_votes: RPMh TCS command set for GPU, GMU voltage and bw scaling |
| 185 | * @cx_gdsc: CX headswitch that controls power of GMU and |
| 186 | subsystem peripherals |
| 187 | * @gx_gdsc: GX headswitch that controls power of GPU subsystem |
| 188 | * @clks: GPU subsystem clocks required for GMU functionality |
| 189 | * @load_mode: GMU FW load/boot mode |
| 190 | * @flags: GMU power control flags |
| 191 | * @wakeup_pwrlevel: GPU wake up power/DCVS level in case different |
| 192 | * than default power level |
| 193 | * @pcl: GPU BW scaling client |
| 194 | * @ccl: CNOC BW scaling client |
| 195 | * @idle_level: Minimal GPU idle power level |
| 196 | */ |
| 197 | struct gmu_device { |
| 198 | unsigned int ver; |
| 199 | struct platform_device *pdev; |
| 200 | unsigned long reg_phys; |
| 201 | void __iomem *reg_virt; |
| 202 | unsigned int reg_len; |
| 203 | unsigned int gmu2gpu_offset; |
| 204 | void __iomem *pdc_reg_virt; |
| 205 | unsigned int gmu_interrupt_num; |
| 206 | struct gmu_memdesc fw_image; |
| 207 | struct gmu_memdesc *hfi_mem; |
| 208 | struct gmu_memdesc *dump_mem; |
| 209 | struct kgsl_hfi hfi; |
| 210 | struct limits_config lm_config; |
| 211 | unsigned int lm_dcvs_level; |
| 212 | unsigned int bcl_config; |
| 213 | unsigned int gmu_freqs[MAX_CX_LEVELS]; |
| 214 | unsigned int gpu_freqs[MAX_GX_LEVELS]; |
| 215 | unsigned int num_gmupwrlevels; |
| 216 | unsigned int num_gpupwrlevels; |
| 217 | unsigned int num_bwlevels; |
| 218 | unsigned int num_cnocbwlevels; |
| 219 | struct rpmh_votes_t rpmh_votes; |
| 220 | struct regulator *cx_gdsc; |
| 221 | struct regulator *gx_gdsc; |
| 222 | struct clk *clks[MAX_GMU_CLKS]; |
| 223 | enum gmu_load_mode load_mode; |
| 224 | unsigned long flags; |
| 225 | unsigned int wakeup_pwrlevel; |
| 226 | unsigned int pcl; |
| 227 | unsigned int ccl; |
| 228 | unsigned int idle_level; |
| 229 | }; |
| 230 | |
Kyle Piefer | 11a48b6 | 2017-03-17 14:53:40 -0700 | [diff] [blame] | 231 | bool kgsl_gmu_isenabled(struct kgsl_device *device); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 232 | int gmu_probe(struct kgsl_device *device); |
| 233 | void gmu_remove(struct kgsl_device *device); |
| 234 | int allocate_gmu_image(struct gmu_device *gmu, unsigned int size); |
| 235 | int gmu_start(struct kgsl_device *device); |
| 236 | void gmu_stop(struct kgsl_device *device); |
| 237 | int gmu_dcvs_set(struct gmu_device *gmu, unsigned int gpu_pwrlevel, |
| 238 | unsigned int bus_level); |
| 239 | #endif /* __KGSL_GMU_H */ |