blob: 9393fd902f0d401a475db4f97646ee95e36220bb [file] [log] [blame]
Ruud Derwig2924cd12014-12-03 15:52:41 +01001/*
2 * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
11 */
12
13/ {
14 compatible = "snps,arc";
15 clock-frequency = <50000000>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 cpu_card {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 ranges = <0x00000000 0xf0000000 0x10000000>;
25
26 cpu_intc: archs-intc@cpu {
27 compatible = "snps,archs-intc";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 };
31
32 debug_uart: dw-apb-uart@0x5000 {
33 compatible = "snps,dw-apb-uart";
34 reg = <0x5000 0x100>;
35 clock-frequency = <2403200>;
36 interrupt-parent = <&cpu_intc>;
37 interrupts = <19>;
38 baud = <115200>;
39 reg-shift = <2>;
40 reg-io-width = <4>;
41 };
42
43 };
44
45 mb_intc: dw-apb-ictl@0xe0012000 {
46 #interrupt-cells = <1>;
47 compatible = "snps,dw-apb-ictl";
48 reg = < 0xe0012000 0x200 >;
49 interrupt-controller;
50 interrupt-parent = <&cpu_intc>;
51 interrupts = < 18 >;
52 };
53
54 memory {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges = <0x00000000 0x80000000 0x40000000>;
58 device_type = "memory";
59 reg = <0x00000000 0x20000000>; /* 512MiB */
60 };
61};