Vineet Gupta | 5793e27 | 2015-03-05 19:13:56 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of.h> |
| 13 | #include <linux/irqdomain.h> |
| 14 | #include <linux/irqchip.h> |
Vineet Gupta | 5793e27 | 2015-03-05 19:13:56 +0530 | [diff] [blame] | 15 | #include <asm/irq.h> |
| 16 | |
| 17 | /* |
| 18 | * Early Hardware specific Interrupt setup |
| 19 | * -Platform independent, needed for each CPU (not foldable into init_IRQ) |
| 20 | * -Called very early (start_kernel -> setup_arch -> setup_processor) |
| 21 | * |
| 22 | * what it does ? |
| 23 | * -Optionally, setup the High priority Interrupts as Level 2 IRQs |
| 24 | */ |
| 25 | void arc_init_IRQ(void) |
| 26 | { |
| 27 | int level_mask = 0; |
| 28 | |
| 29 | /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ |
| 30 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; |
| 31 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; |
| 32 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; |
| 33 | |
| 34 | /* |
| 35 | * Write to register, even if no LV2 IRQs configured to reset it |
| 36 | * in case bootloader had mucked with it |
| 37 | */ |
| 38 | write_aux_reg(AUX_IRQ_LEV, level_mask); |
| 39 | |
| 40 | if (level_mask) |
| 41 | pr_info("Level-2 interrupts bitset %x\n", level_mask); |
| 42 | } |
| 43 | |
| 44 | /* |
| 45 | * ARC700 core includes a simple on-chip intc supporting |
| 46 | * -per IRQ enable/disable |
| 47 | * -2 levels of interrupts (high/low) |
| 48 | * -all interrupts being level triggered |
| 49 | * |
| 50 | * To reduce platform code, we assume all IRQs directly hooked-up into intc. |
| 51 | * Platforms with external intc, hence cascaded IRQs, are free to over-ride |
| 52 | * below, per IRQ. |
| 53 | */ |
| 54 | |
| 55 | static void arc_irq_mask(struct irq_data *data) |
| 56 | { |
| 57 | unsigned int ienb; |
| 58 | |
| 59 | ienb = read_aux_reg(AUX_IENABLE); |
| 60 | ienb &= ~(1 << data->irq); |
| 61 | write_aux_reg(AUX_IENABLE, ienb); |
| 62 | } |
| 63 | |
| 64 | static void arc_irq_unmask(struct irq_data *data) |
| 65 | { |
| 66 | unsigned int ienb; |
| 67 | |
| 68 | ienb = read_aux_reg(AUX_IENABLE); |
| 69 | ienb |= (1 << data->irq); |
| 70 | write_aux_reg(AUX_IENABLE, ienb); |
| 71 | } |
| 72 | |
| 73 | static struct irq_chip onchip_intc = { |
| 74 | .name = "ARC In-core Intc", |
| 75 | .irq_mask = arc_irq_mask, |
| 76 | .irq_unmask = arc_irq_unmask, |
| 77 | }; |
| 78 | |
| 79 | static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, |
| 80 | irq_hw_number_t hw) |
| 81 | { |
| 82 | /* |
| 83 | * XXX: the IPI IRQ needs to be handled like TIMER too. However ARC core |
| 84 | * code doesn't own it (like TIMER0). ISS IDU / ezchip define it |
| 85 | * in platform header which can't be included here as it goes |
| 86 | * against multi-platform image philisophy |
| 87 | */ |
| 88 | if (irq == TIMER0_IRQ) |
| 89 | irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); |
| 90 | else |
| 91 | irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); |
| 92 | |
| 93 | return 0; |
| 94 | } |
| 95 | |
| 96 | static const struct irq_domain_ops arc_intc_domain_ops = { |
| 97 | .xlate = irq_domain_xlate_onecell, |
| 98 | .map = arc_intc_domain_map, |
| 99 | }; |
| 100 | |
| 101 | static struct irq_domain *root_domain; |
| 102 | |
| 103 | static int __init |
| 104 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) |
| 105 | { |
| 106 | if (parent) |
| 107 | panic("DeviceTree incore intc not a root irq controller\n"); |
| 108 | |
| 109 | root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, |
| 110 | &arc_intc_domain_ops, NULL); |
| 111 | |
| 112 | if (!root_domain) |
| 113 | panic("root irq domain not avail\n"); |
| 114 | |
| 115 | /* with this we don't need to export root_domain */ |
| 116 | irq_set_default_host(root_domain); |
| 117 | |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); |
| 122 | |
| 123 | /* |
| 124 | * arch_local_irq_enable - Enable interrupts. |
| 125 | * |
| 126 | * 1. Explicitly called to re-enable interrupts |
| 127 | * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc |
| 128 | * which maybe in hard ISR itself |
| 129 | * |
| 130 | * Semantics of this function change depending on where it is called from: |
| 131 | * |
| 132 | * -If called from hard-ISR, it must not invert interrupt priorities |
| 133 | * e.g. suppose TIMER is high priority (Level 2) IRQ |
| 134 | * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. |
| 135 | * Here local_irq_enable( ) shd not re-enable lower priority interrupts |
| 136 | * -If called from soft-ISR, it must re-enable all interrupts |
| 137 | * soft ISR are low prioity jobs which can be very slow, thus all IRQs |
| 138 | * must be enabled while they run. |
| 139 | * Now hardware context wise we may still be in L2 ISR (not done rtie) |
| 140 | * still we must re-enable both L1 and L2 IRQs |
| 141 | * Another twist is prev scenario with flow being |
| 142 | * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR |
| 143 | * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get |
| 144 | * over-written (this is deficiency in ARC700 Interrupt mechanism) |
| 145 | */ |
| 146 | |
| 147 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ |
| 148 | |
| 149 | void arch_local_irq_enable(void) |
| 150 | { |
| 151 | |
| 152 | unsigned long flags = arch_local_save_flags(); |
| 153 | |
| 154 | /* Allow both L1 and L2 at the onset */ |
| 155 | flags |= (STATUS_E1_MASK | STATUS_E2_MASK); |
| 156 | |
| 157 | /* Called from hard ISR (between irq_enter and irq_exit) */ |
| 158 | if (in_irq()) { |
| 159 | |
| 160 | /* If in L2 ISR, don't re-enable any further IRQs as this can |
| 161 | * cause IRQ priorities to get upside down. e.g. it could allow |
| 162 | * L1 be taken while in L2 hard ISR which is wrong not only in |
| 163 | * theory, it can also cause the dreaded L1-L2-L1 scenario |
| 164 | */ |
| 165 | if (flags & STATUS_A2_MASK) |
| 166 | flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); |
| 167 | |
| 168 | /* Even if in L1 ISR, allowe Higher prio L2 IRQs */ |
| 169 | else if (flags & STATUS_A1_MASK) |
| 170 | flags &= ~(STATUS_E1_MASK); |
| 171 | } |
| 172 | |
| 173 | /* called from soft IRQ, ideally we want to re-enable all levels */ |
| 174 | |
| 175 | else if (in_softirq()) { |
| 176 | |
| 177 | /* However if this is case of L1 interrupted by L2, |
| 178 | * re-enabling both may cause whaco L1-L2-L1 scenario |
| 179 | * because ARC700 allows level 1 to interrupt an active L2 ISR |
| 180 | * Thus we disable both |
| 181 | * However some code, executing in soft ISR wants some IRQs |
| 182 | * to be enabled so we re-enable L2 only |
| 183 | * |
| 184 | * How do we determine L1 intr by L2 |
| 185 | * -A2 is set (means in L2 ISR) |
| 186 | * -E1 is set in this ISR's pt_regs->status32 which is |
| 187 | * saved copy of status32_l2 when l2 ISR happened |
| 188 | */ |
| 189 | struct pt_regs *pt = get_irq_regs(); |
| 190 | |
| 191 | if ((flags & STATUS_A2_MASK) && pt && |
| 192 | (pt->status32 & STATUS_A1_MASK)) { |
| 193 | /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */ |
| 194 | flags &= ~(STATUS_E1_MASK); |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | arch_local_irq_restore(flags); |
| 199 | } |
| 200 | |
| 201 | #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */ |
| 202 | |
| 203 | /* |
| 204 | * Simpler version for only 1 level of interrupt |
| 205 | * Here we only Worry about Level 1 Bits |
| 206 | */ |
| 207 | void arch_local_irq_enable(void) |
| 208 | { |
| 209 | unsigned long flags; |
| 210 | |
| 211 | /* |
| 212 | * ARC IDE Drivers tries to re-enable interrupts from hard-isr |
| 213 | * context which is simply wrong |
| 214 | */ |
| 215 | if (in_irq()) { |
| 216 | WARN_ONCE(1, "IRQ enabled from hard-isr"); |
| 217 | return; |
| 218 | } |
| 219 | |
| 220 | flags = arch_local_save_flags(); |
| 221 | flags |= (STATUS_E1_MASK | STATUS_E2_MASK); |
| 222 | arch_local_irq_restore(flags); |
| 223 | } |
| 224 | #endif |
| 225 | EXPORT_SYMBOL(arch_local_irq_enable); |