Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/of.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/slab.h> |
| 16 | |
| 17 | #include "mc.h" |
| 18 | |
| 19 | #define MC_INTSTATUS 0x000 |
| 20 | #define MC_INT_DECERR_MTS (1 << 16) |
| 21 | #define MC_INT_SECERR_SEC (1 << 13) |
| 22 | #define MC_INT_DECERR_VPR (1 << 12) |
| 23 | #define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) |
| 24 | #define MC_INT_INVALID_SMMU_PAGE (1 << 10) |
| 25 | #define MC_INT_ARBITRATION_EMEM (1 << 9) |
| 26 | #define MC_INT_SECURITY_VIOLATION (1 << 8) |
| 27 | #define MC_INT_DECERR_EMEM (1 << 6) |
| 28 | |
| 29 | #define MC_INTMASK 0x004 |
| 30 | |
| 31 | #define MC_ERR_STATUS 0x08 |
| 32 | #define MC_ERR_STATUS_TYPE_SHIFT 28 |
| 33 | #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) |
| 34 | #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) |
| 35 | #define MC_ERR_STATUS_READABLE (1 << 27) |
| 36 | #define MC_ERR_STATUS_WRITABLE (1 << 26) |
| 37 | #define MC_ERR_STATUS_NONSECURE (1 << 25) |
| 38 | #define MC_ERR_STATUS_ADR_HI_SHIFT 20 |
| 39 | #define MC_ERR_STATUS_ADR_HI_MASK 0x3 |
| 40 | #define MC_ERR_STATUS_SECURITY (1 << 17) |
| 41 | #define MC_ERR_STATUS_RW (1 << 16) |
| 42 | #define MC_ERR_STATUS_CLIENT_MASK 0x7f |
| 43 | |
| 44 | #define MC_ERR_ADR 0x0c |
| 45 | |
| 46 | #define MC_EMEM_ARB_CFG 0x90 |
| 47 | #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) |
| 48 | #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff |
| 49 | #define MC_EMEM_ARB_MISC0 0xd8 |
| 50 | |
| 51 | static const struct of_device_id tegra_mc_of_match[] = { |
| 52 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
| 53 | { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, |
| 54 | #endif |
| 55 | #ifdef CONFIG_ARCH_TEGRA_114_SOC |
| 56 | { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, |
| 57 | #endif |
| 58 | #ifdef CONFIG_ARCH_TEGRA_124_SOC |
| 59 | { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, |
| 60 | #endif |
Thierry Reding | 242b1d7 | 2014-11-07 16:10:41 +0100 | [diff] [blame^] | 61 | #ifdef CONFIG_ARCH_TEGRA_132_SOC |
| 62 | { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, |
| 63 | #endif |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 64 | { } |
| 65 | }; |
| 66 | MODULE_DEVICE_TABLE(of, tegra_mc_of_match); |
| 67 | |
| 68 | static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) |
| 69 | { |
| 70 | unsigned long long tick; |
| 71 | unsigned int i; |
| 72 | u32 value; |
| 73 | |
| 74 | /* compute the number of MC clock cycles per tick */ |
| 75 | tick = mc->tick * clk_get_rate(mc->clk); |
| 76 | do_div(tick, NSEC_PER_SEC); |
| 77 | |
| 78 | value = readl(mc->regs + MC_EMEM_ARB_CFG); |
| 79 | value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; |
| 80 | value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); |
| 81 | writel(value, mc->regs + MC_EMEM_ARB_CFG); |
| 82 | |
| 83 | /* write latency allowance defaults */ |
| 84 | for (i = 0; i < mc->soc->num_clients; i++) { |
| 85 | const struct tegra_mc_la *la = &mc->soc->clients[i].la; |
| 86 | u32 value; |
| 87 | |
| 88 | value = readl(mc->regs + la->reg); |
| 89 | value &= ~(la->mask << la->shift); |
| 90 | value |= (la->def & la->mask) << la->shift; |
| 91 | writel(value, mc->regs + la->reg); |
| 92 | } |
| 93 | |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | static const char *const status_names[32] = { |
| 98 | [ 1] = "External interrupt", |
| 99 | [ 6] = "EMEM address decode error", |
| 100 | [ 8] = "Security violation", |
| 101 | [ 9] = "EMEM arbitration error", |
| 102 | [10] = "Page fault", |
| 103 | [11] = "Invalid APB ASID update", |
| 104 | [12] = "VPR violation", |
| 105 | [13] = "Secure carveout violation", |
| 106 | [16] = "MTS carveout violation", |
| 107 | }; |
| 108 | |
| 109 | static const char *const error_names[8] = { |
| 110 | [2] = "EMEM decode error", |
| 111 | [3] = "TrustZone violation", |
| 112 | [4] = "Carveout violation", |
| 113 | [6] = "SMMU translation error", |
| 114 | }; |
| 115 | |
| 116 | static irqreturn_t tegra_mc_irq(int irq, void *data) |
| 117 | { |
| 118 | struct tegra_mc *mc = data; |
| 119 | unsigned long status, mask; |
| 120 | unsigned int bit; |
| 121 | |
| 122 | /* mask all interrupts to avoid flooding */ |
| 123 | status = mc_readl(mc, MC_INTSTATUS); |
| 124 | mask = mc_readl(mc, MC_INTMASK); |
| 125 | |
| 126 | for_each_set_bit(bit, &status, 32) { |
| 127 | const char *error = status_names[bit] ?: "unknown"; |
| 128 | const char *client = "unknown", *desc; |
| 129 | const char *direction, *secure; |
| 130 | phys_addr_t addr = 0; |
| 131 | unsigned int i; |
| 132 | char perm[7]; |
| 133 | u8 id, type; |
| 134 | u32 value; |
| 135 | |
| 136 | value = mc_readl(mc, MC_ERR_STATUS); |
| 137 | |
| 138 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
| 139 | if (mc->soc->num_address_bits > 32) { |
| 140 | addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & |
| 141 | MC_ERR_STATUS_ADR_HI_MASK); |
| 142 | addr <<= 32; |
| 143 | } |
| 144 | #endif |
| 145 | |
| 146 | if (value & MC_ERR_STATUS_RW) |
| 147 | direction = "write"; |
| 148 | else |
| 149 | direction = "read"; |
| 150 | |
| 151 | if (value & MC_ERR_STATUS_SECURITY) |
| 152 | secure = "secure "; |
| 153 | else |
| 154 | secure = ""; |
| 155 | |
| 156 | id = value & MC_ERR_STATUS_CLIENT_MASK; |
| 157 | |
| 158 | for (i = 0; i < mc->soc->num_clients; i++) { |
| 159 | if (mc->soc->clients[i].id == id) { |
| 160 | client = mc->soc->clients[i].name; |
| 161 | break; |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | type = (value & MC_ERR_STATUS_TYPE_MASK) >> |
| 166 | MC_ERR_STATUS_TYPE_SHIFT; |
| 167 | desc = error_names[type]; |
| 168 | |
| 169 | switch (value & MC_ERR_STATUS_TYPE_MASK) { |
| 170 | case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: |
| 171 | perm[0] = ' '; |
| 172 | perm[1] = '['; |
| 173 | |
| 174 | if (value & MC_ERR_STATUS_READABLE) |
| 175 | perm[2] = 'R'; |
| 176 | else |
| 177 | perm[2] = '-'; |
| 178 | |
| 179 | if (value & MC_ERR_STATUS_WRITABLE) |
| 180 | perm[3] = 'W'; |
| 181 | else |
| 182 | perm[3] = '-'; |
| 183 | |
| 184 | if (value & MC_ERR_STATUS_NONSECURE) |
| 185 | perm[4] = '-'; |
| 186 | else |
| 187 | perm[4] = 'S'; |
| 188 | |
| 189 | perm[5] = ']'; |
| 190 | perm[6] = '\0'; |
| 191 | break; |
| 192 | |
| 193 | default: |
| 194 | perm[0] = '\0'; |
| 195 | break; |
| 196 | } |
| 197 | |
| 198 | value = mc_readl(mc, MC_ERR_ADR); |
| 199 | addr |= value; |
| 200 | |
| 201 | dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", |
| 202 | client, secure, direction, &addr, error, |
| 203 | desc, perm); |
| 204 | } |
| 205 | |
| 206 | /* clear interrupts */ |
| 207 | mc_writel(mc, status, MC_INTSTATUS); |
| 208 | |
| 209 | return IRQ_HANDLED; |
| 210 | } |
| 211 | |
| 212 | static int tegra_mc_probe(struct platform_device *pdev) |
| 213 | { |
| 214 | const struct of_device_id *match; |
| 215 | struct resource *res; |
| 216 | struct tegra_mc *mc; |
| 217 | u32 value; |
| 218 | int err; |
| 219 | |
| 220 | match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); |
| 221 | if (!match) |
| 222 | return -ENODEV; |
| 223 | |
| 224 | mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); |
| 225 | if (!mc) |
| 226 | return -ENOMEM; |
| 227 | |
| 228 | platform_set_drvdata(pdev, mc); |
| 229 | mc->soc = match->data; |
| 230 | mc->dev = &pdev->dev; |
| 231 | |
| 232 | /* length of MC tick in nanoseconds */ |
| 233 | mc->tick = 30; |
| 234 | |
| 235 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 236 | mc->regs = devm_ioremap_resource(&pdev->dev, res); |
| 237 | if (IS_ERR(mc->regs)) |
| 238 | return PTR_ERR(mc->regs); |
| 239 | |
| 240 | mc->clk = devm_clk_get(&pdev->dev, "mc"); |
| 241 | if (IS_ERR(mc->clk)) { |
| 242 | dev_err(&pdev->dev, "failed to get MC clock: %ld\n", |
| 243 | PTR_ERR(mc->clk)); |
| 244 | return PTR_ERR(mc->clk); |
| 245 | } |
| 246 | |
| 247 | err = tegra_mc_setup_latency_allowance(mc); |
| 248 | if (err < 0) { |
| 249 | dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", |
| 250 | err); |
| 251 | return err; |
| 252 | } |
| 253 | |
| 254 | if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { |
| 255 | mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); |
| 256 | if (IS_ERR(mc->smmu)) { |
| 257 | dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", |
| 258 | PTR_ERR(mc->smmu)); |
| 259 | return PTR_ERR(mc->smmu); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | mc->irq = platform_get_irq(pdev, 0); |
| 264 | if (mc->irq < 0) { |
| 265 | dev_err(&pdev->dev, "interrupt not specified\n"); |
| 266 | return mc->irq; |
| 267 | } |
| 268 | |
| 269 | err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED, |
| 270 | dev_name(&pdev->dev), mc); |
| 271 | if (err < 0) { |
| 272 | dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, |
| 273 | err); |
| 274 | return err; |
| 275 | } |
| 276 | |
| 277 | value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | |
| 278 | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | |
| 279 | MC_INT_ARBITRATION_EMEM | MC_INT_SECURITY_VIOLATION | |
| 280 | MC_INT_DECERR_EMEM; |
| 281 | mc_writel(mc, value, MC_INTMASK); |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static struct platform_driver tegra_mc_driver = { |
| 287 | .driver = { |
| 288 | .name = "tegra-mc", |
| 289 | .of_match_table = tegra_mc_of_match, |
| 290 | .suppress_bind_attrs = true, |
| 291 | }, |
| 292 | .prevent_deferred_probe = true, |
| 293 | .probe = tegra_mc_probe, |
| 294 | }; |
| 295 | |
| 296 | static int tegra_mc_init(void) |
| 297 | { |
| 298 | return platform_driver_register(&tegra_mc_driver); |
| 299 | } |
| 300 | arch_initcall(tegra_mc_init); |
| 301 | |
| 302 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); |
| 303 | MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); |
| 304 | MODULE_LICENSE("GPL v2"); |