blob: d24488bf564492d82429fae78a7fea4f73a2182f [file] [log] [blame]
Alan Cox7e45b0e2006-09-29 18:30:05 +01001/*
2 * pata_winbond.c - Winbond VLB ATA controllers
3 * (C) 2006 Red Hat <alan@redhat.com>
4 *
5 * Support for the Winbond 83759A when operating in advanced mode.
6 * Multichip mode is not currently supported.
7 */
Jeff Garzikf20b16f2006-12-11 11:14:06 -05008
Alan Cox7e45b0e2006-09-29 18:30:05 +01009#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/init.h>
13#include <linux/blkdev.h>
14#include <linux/delay.h>
15#include <scsi/scsi_host.h>
16#include <linux/libata.h>
17#include <linux/platform_device.h>
18
19#define DRV_NAME "pata_winbond"
20#define DRV_VERSION "0.0.1"
21
22#define NR_HOST 4 /* Two winbond controllers, two channels each */
23
24struct winbond_data {
25 unsigned long config;
26 struct platform_device *platform_dev;
27};
28
29static struct ata_host *winbond_host[NR_HOST];
30static struct winbond_data winbond_data[NR_HOST];
31static int nr_winbond_host;
32
33#ifdef MODULE
34static int probe_winbond = 1;
35#else
36static int probe_winbond;
37#endif
38
39static spinlock_t winbond_lock = SPIN_LOCK_UNLOCKED;
40
41static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
42{
43 unsigned long flags;
44 spin_lock_irqsave(&winbond_lock, flags);
45 outb(reg, port + 0x01);
46 outb(val, port + 0x02);
47 spin_unlock_irqrestore(&winbond_lock, flags);
48}
49
50static u8 winbond_readcfg(unsigned long port, u8 reg)
51{
52 u8 val;
53
54 unsigned long flags;
55 spin_lock_irqsave(&winbond_lock, flags);
56 outb(reg, port + 0x01);
57 val = inb(port + 0x02);
58 spin_unlock_irqrestore(&winbond_lock, flags);
59
60 return val;
61}
62
63static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
64{
65 struct ata_timing t;
66 struct winbond_data *winbond = ap->host->private_data;
67 int active, recovery;
68 u8 reg;
69 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
70
71 reg = winbond_readcfg(winbond->config, 0x81);
Jeff Garzikf20b16f2006-12-11 11:14:06 -050072
Alan Cox7e45b0e2006-09-29 18:30:05 +010073 /* Get the timing data in cycles */
74 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
75 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
76 else
77 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
78
79 active = (FIT(t.active, 3, 17) - 1) & 0x0F;
80 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F;
81 timing = (active << 4) | recovery;
82 winbond_writecfg(winbond->config, timing, reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -050083
Alan Cox7e45b0e2006-09-29 18:30:05 +010084 /* Load the setup timing */
Jeff Garzikf20b16f2006-12-11 11:14:06 -050085
Alan Cox7e45b0e2006-09-29 18:30:05 +010086 reg = 0x35;
87 if (adev->class != ATA_DEV_ATA)
88 reg |= 0x08; /* FIFO off */
89 if (!ata_pio_need_iordy(adev))
90 reg |= 0x02; /* IORDY off */
91 reg |= (FIT(t.setup, 0, 3) << 6);
92 winbond_writecfg(winbond->config, timing + 1, reg);
93}
94
95
96static void winbond_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
97{
98 struct ata_port *ap = adev->ap;
99 int slop = buflen & 3;
100
101 if (ata_id_has_dword_io(adev->id)) {
102 if (write_data)
Tejun Heo0d5ff562007-02-01 15:06:36 +0900103 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100104 else
Tejun Heo0d5ff562007-02-01 15:06:36 +0900105 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100106
107 if (unlikely(slop)) {
108 u32 pad;
109 if (write_data) {
110 memcpy(&pad, buf + buflen - slop, slop);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900111 pad = le32_to_cpu(pad);
112 iowrite32(pad, ap->ioaddr.data_addr);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100113 } else {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900114 pad = ioread32(ap->ioaddr.data_addr);
115 pad = cpu_to_le16(pad);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100116 memcpy(buf + buflen - slop, &pad, slop);
117 }
118 }
119 } else
Tejun Heo0d5ff562007-02-01 15:06:36 +0900120 ata_data_xfer(adev, buf, buflen, write_data);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100121}
122
123static struct scsi_host_template winbond_sht = {
124 .module = THIS_MODULE,
125 .name = DRV_NAME,
126 .ioctl = ata_scsi_ioctl,
127 .queuecommand = ata_scsi_queuecmd,
128 .can_queue = ATA_DEF_QUEUE,
129 .this_id = ATA_SHT_THIS_ID,
130 .sg_tablesize = LIBATA_MAX_PRD,
Alan Cox7e45b0e2006-09-29 18:30:05 +0100131 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
132 .emulated = ATA_SHT_EMULATED,
133 .use_clustering = ATA_SHT_USE_CLUSTERING,
134 .proc_name = DRV_NAME,
135 .dma_boundary = ATA_DMA_BOUNDARY,
136 .slave_configure = ata_scsi_slave_config,
Tejun Heoc972b602006-11-29 12:10:46 +0900137 .slave_destroy = ata_scsi_slave_destroy,
Alan Cox7e45b0e2006-09-29 18:30:05 +0100138 .bios_param = ata_std_bios_param,
139};
140
141static struct ata_port_operations winbond_port_ops = {
142 .port_disable = ata_port_disable,
143 .set_piomode = winbond_set_piomode,
144
145 .tf_load = ata_tf_load,
146 .tf_read = ata_tf_read,
147 .check_status = ata_check_status,
148 .exec_command = ata_exec_command,
149 .dev_select = ata_std_dev_select,
150
151 .freeze = ata_bmdma_freeze,
152 .thaw = ata_bmdma_thaw,
153 .error_handler = ata_bmdma_error_handler,
154 .post_internal_cmd = ata_bmdma_post_internal_cmd,
155
156 .qc_prep = ata_qc_prep,
157 .qc_issue = ata_qc_issue_prot,
158
159 .data_xfer = winbond_data_xfer,
160
161 .irq_handler = ata_interrupt,
162 .irq_clear = ata_bmdma_irq_clear,
163
164 .port_start = ata_port_start,
Alan Cox7e45b0e2006-09-29 18:30:05 +0100165};
166
167/**
168 * winbond_init_one - attach a winbond interface
169 * @type: Type to display
170 * @io: I/O port start
171 * @irq: interrupt line
172 * @fast: True if on a > 33Mhz VLB
173 *
174 * Register a VLB bus IDE interface. Such interfaces are PIO and we
175 * assume do not support IRQ sharing.
176 */
177
178static __init int winbond_init_one(unsigned long port)
179{
180 struct ata_probe_ent ae;
181 struct platform_device *pdev;
182 int ret;
183 u8 reg;
184 int i;
185
186 reg = winbond_readcfg(port, 0x81);
187 reg |= 0x80; /* jumpered mode off */
188 winbond_writecfg(port, 0x81, reg);
189 reg = winbond_readcfg(port, 0x83);
190 reg |= 0xF0; /* local control */
191 winbond_writecfg(port, 0x83, reg);
192 reg = winbond_readcfg(port, 0x85);
193 reg |= 0xF0; /* programmable timing */
194 winbond_writecfg(port, 0x85, reg);
195
196 reg = winbond_readcfg(port, 0x81);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500197
Alan Cox7e45b0e2006-09-29 18:30:05 +0100198 if (!(reg & 0x03)) /* Disabled */
199 return 0;
200
201 for (i = 0; i < 2 ; i ++) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900202 unsigned long cmd_port = 0x1F0 - (0x80 * i);
203 void __iomem *cmd_addr, *ctl_addr;
Alan Cox7e45b0e2006-09-29 18:30:05 +0100204
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500205 if (reg & (1 << i)) {
Alan Cox7e45b0e2006-09-29 18:30:05 +0100206 /*
207 * Fill in a probe structure first of all
208 */
209
210 pdev = platform_device_register_simple(DRV_NAME, nr_winbond_host, NULL, 0);
Akinobu Mita9825d732006-12-15 13:08:51 -0800211 if (IS_ERR(pdev))
212 return PTR_ERR(pdev);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100213
Tejun Heo0d5ff562007-02-01 15:06:36 +0900214 cmd_addr = devm_ioport_map(&pdev->dev, cmd_port, 8);
215 ctl_addr = devm_ioport_map(&pdev->dev, cmd_port + 0x0206, 1);
216 if (!cmd_addr || !ctl_addr) {
217 platform_device_unregister(pdev);
218 return -ENOMEM;
219 }
220
Alan Cox7e45b0e2006-09-29 18:30:05 +0100221 memset(&ae, 0, sizeof(struct ata_probe_ent));
222 INIT_LIST_HEAD(&ae.node);
223 ae.dev = &pdev->dev;
224
225 ae.port_ops = &winbond_port_ops;
226 ae.pio_mask = 0x1F;
227
228 ae.sht = &winbond_sht;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500229
Alan Cox7e45b0e2006-09-29 18:30:05 +0100230 ae.n_ports = 1;
231 ae.irq = 14 + i;
232 ae.irq_flags = 0;
233 ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900234 ae.port[0].cmd_addr = cmd_addr;
235 ae.port[0].altstatus_addr = ctl_addr;
236 ae.port[0].ctl_addr = ctl_addr;
Alan Cox7e45b0e2006-09-29 18:30:05 +0100237 ata_std_ports(&ae.port[0]);
238 /*
239 * Hook in a private data structure per channel
240 */
241 ae.private_data = &winbond_data[nr_winbond_host];
242 winbond_data[nr_winbond_host].config = port;
243 winbond_data[nr_winbond_host].platform_dev = pdev;
244
245 ret = ata_device_add(&ae);
246 if (ret == 0) {
247 platform_device_unregister(pdev);
248 return -ENODEV;
249 }
250 winbond_host[nr_winbond_host++] = dev_get_drvdata(&pdev->dev);
251 }
252 }
253
254 return 0;
255}
256
257/**
258 * winbond_init - attach winbond interfaces
259 *
260 * Attach winbond IDE interfaces by scanning the ports it may occupy.
261 */
262
263static __init int winbond_init(void)
264{
265 static const unsigned long config[2] = { 0x130, 0x1B0 };
266
267 int ct = 0;
268 int i;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500269
Alan Cox7e45b0e2006-09-29 18:30:05 +0100270 if (probe_winbond == 0)
271 return -ENODEV;
272
273 /*
274 * Check both base addresses
275 */
276
277 for (i = 0; i < 2; i++) {
278 if (probe_winbond & (1<<i)) {
279 int ret = 0;
280 unsigned long port = config[i];
281
282 if (request_region(port, 2, "pata_winbond")) {
283 ret = winbond_init_one(port);
284 if(ret <= 0)
285 release_region(port, 2);
286 else ct+= ret;
287 }
288 }
289 }
290 if (ct != 0)
291 return 0;
292 return -ENODEV;
293}
294
295static __exit void winbond_exit(void)
296{
297 int i;
298
299 for (i = 0; i < nr_winbond_host; i++) {
Tejun Heo24dc5f32007-01-20 16:00:28 +0900300 ata_host_detach(winbond_host[i]);
Alan Cox7e45b0e2006-09-29 18:30:05 +0100301 release_region(winbond_data[i].config, 2);
302 platform_device_unregister(winbond_data[i].platform_dev);
303 }
304}
305
306MODULE_AUTHOR("Alan Cox");
307MODULE_DESCRIPTION("low-level driver for Winbond VL ATA");
308MODULE_LICENSE("GPL");
309MODULE_VERSION(DRV_VERSION);
310
311module_init(winbond_init);
312module_exit(winbond_exit);
313
314module_param(probe_winbond, int, 0);
315