blob: 77497be042a8625da04a5da104b9ea6e1a9f4053 [file] [log] [blame]
Zhiwu Song1cc2df92012-02-13 17:45:38 +08001/*
2 * SPI bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/of_gpio.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
Barry Song71422f92012-05-15 10:21:00 +080022#include <linux/pinctrl/consumer.h>
Zhiwu Song1cc2df92012-02-13 17:45:38 +080023
24#define DRIVER_NAME "sirfsoc_spi"
25
26#define SIRFSOC_SPI_CTRL 0x0000
27#define SIRFSOC_SPI_CMD 0x0004
28#define SIRFSOC_SPI_TX_RX_EN 0x0008
29#define SIRFSOC_SPI_INT_EN 0x000C
30#define SIRFSOC_SPI_INT_STATUS 0x0010
31#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
32#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
33#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
34#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
35#define SIRFSOC_SPI_TXFIFO_OP 0x0110
36#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
37#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
38#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
39#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
40#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
41#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
42#define SIRFSOC_SPI_RXFIFO_OP 0x0130
43#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
44#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
45#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
46
47/* SPI CTRL register defines */
48#define SIRFSOC_SPI_SLV_MODE BIT(16)
49#define SIRFSOC_SPI_CMD_MODE BIT(17)
50#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
51#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
52#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
53#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
54#define SIRFSOC_SPI_TRAN_MSB BIT(22)
55#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
56#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
57#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
58#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
59#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
60#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
62#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
63#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
64#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
65
66/* Interrupt Enable */
67#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
68#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
69#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
70#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
71#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
72#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
73#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
74#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
75#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
76#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
77#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
78
79#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
80
81/* Interrupt status */
82#define SIRFSOC_SPI_RX_DONE BIT(0)
83#define SIRFSOC_SPI_TX_DONE BIT(1)
84#define SIRFSOC_SPI_RX_OFLOW BIT(2)
85#define SIRFSOC_SPI_TX_UFLOW BIT(3)
86#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
87#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
88#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
89#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
90#define SIRFSOC_SPI_FRM_END BIT(10)
91
92/* TX RX enable */
93#define SIRFSOC_SPI_RX_EN BIT(0)
94#define SIRFSOC_SPI_TX_EN BIT(1)
95#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
96
97#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
98#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
99
100/* FIFO OPs */
101#define SIRFSOC_SPI_FIFO_RESET BIT(0)
102#define SIRFSOC_SPI_FIFO_START BIT(1)
103
104/* FIFO CTRL */
105#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
106#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
107#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
108
109/* FIFO Status */
110#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
111#define SIRFSOC_SPI_FIFO_FULL BIT(8)
112#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
113
114/* 256 bytes rx/tx FIFO */
115#define SIRFSOC_SPI_FIFO_SIZE 256
116#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
117
118#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
119#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
120#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
121#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
122
123struct sirfsoc_spi {
124 struct spi_bitbang bitbang;
125 struct completion done;
126
127 void __iomem *base;
128 u32 ctrl_freq; /* SPI controller clock speed */
129 struct clk *clk;
Barry Song71422f92012-05-15 10:21:00 +0800130 struct pinctrl *p;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800131
132 /* rx & tx bufs from the spi_transfer */
133 const void *tx;
134 void *rx;
135
136 /* place received word into rx buffer */
137 void (*rx_word) (struct sirfsoc_spi *);
138 /* get word from tx buffer for sending */
139 void (*tx_word) (struct sirfsoc_spi *);
140
141 /* number of words left to be tranmitted/received */
142 unsigned int left_tx_cnt;
143 unsigned int left_rx_cnt;
144
145 /* tasklet to push tx msg into FIFO */
146 struct tasklet_struct tasklet_tx;
147
148 int chipselect[0];
149};
150
151static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
152{
153 u32 data;
154 u8 *rx = sspi->rx;
155
156 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
157
158 if (rx) {
159 *rx++ = (u8) data;
160 sspi->rx = rx;
161 }
162
163 sspi->left_rx_cnt--;
164}
165
166static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
167{
168 u32 data = 0;
169 const u8 *tx = sspi->tx;
170
171 if (tx) {
172 data = *tx++;
173 sspi->tx = tx;
174 }
175
176 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
177 sspi->left_tx_cnt--;
178}
179
180static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
181{
182 u32 data;
183 u16 *rx = sspi->rx;
184
185 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
186
187 if (rx) {
188 *rx++ = (u16) data;
189 sspi->rx = rx;
190 }
191
192 sspi->left_rx_cnt--;
193}
194
195static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
196{
197 u32 data = 0;
198 const u16 *tx = sspi->tx;
199
200 if (tx) {
201 data = *tx++;
202 sspi->tx = tx;
203 }
204
205 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
206 sspi->left_tx_cnt--;
207}
208
209static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
210{
211 u32 data;
212 u32 *rx = sspi->rx;
213
214 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
215
216 if (rx) {
217 *rx++ = (u32) data;
218 sspi->rx = rx;
219 }
220
221 sspi->left_rx_cnt--;
222
223}
224
225static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
226{
227 u32 data = 0;
228 const u32 *tx = sspi->tx;
229
230 if (tx) {
231 data = *tx++;
232 sspi->tx = tx;
233 }
234
235 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
236 sspi->left_tx_cnt--;
237}
238
239static void spi_sirfsoc_tasklet_tx(unsigned long arg)
240{
241 struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
242
243 /* Fill Tx FIFO while there are left words to be transmitted */
244 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
245 SIRFSOC_SPI_FIFO_FULL)) &&
246 sspi->left_tx_cnt)
247 sspi->tx_word(sspi);
248}
249
250static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
251{
252 struct sirfsoc_spi *sspi = dev_id;
253 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
254
255 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
256
257 /* Error Conditions */
258 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
259 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
260 complete(&sspi->done);
261 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
262 }
263
264 if (spi_stat & SIRFSOC_SPI_FRM_END) {
265 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
266 & SIRFSOC_SPI_FIFO_EMPTY)) &&
267 sspi->left_rx_cnt)
268 sspi->rx_word(sspi);
269
270 /* Received all words */
271 if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
272 complete(&sspi->done);
273 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
274 }
275 }
276
277 if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
278 spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
279 spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
280 spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
281 tasklet_schedule(&sspi->tasklet_tx);
282
283 return IRQ_HANDLED;
284}
285
286static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
287{
288 struct sirfsoc_spi *sspi;
289 int timeout = t->len * 10;
290 sspi = spi_master_get_devdata(spi->master);
291
292 sspi->tx = t->tx_buf;
293 sspi->rx = t->rx_buf;
294 sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
295 INIT_COMPLETION(sspi->done);
296
297 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
298
299 if (t->len == 1) {
300 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
301 SIRFSOC_SPI_ENA_AUTO_CLR,
302 sspi->base + SIRFSOC_SPI_CTRL);
303 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
304 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
305 } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
306 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
307 SIRFSOC_SPI_MUL_DAT_MODE |
308 SIRFSOC_SPI_ENA_AUTO_CLR,
309 sspi->base + SIRFSOC_SPI_CTRL);
310 writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
311 writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
312 } else {
313 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
314 sspi->base + SIRFSOC_SPI_CTRL);
315 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
316 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
317 }
318
319 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
320 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
321 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
322 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
323
324 /* Send the first word to trigger the whole tx/rx process */
325 sspi->tx_word(sspi);
326
327 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
328 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
329 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
330 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
331 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
332
333 if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
334 dev_err(&spi->dev, "transfer timeout\n");
335
336 /* TX, RX FIFO stop */
337 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
338 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
339 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
340 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
341
342 return t->len - sspi->left_rx_cnt;
343}
344
345static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
346{
347 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
348
349 if (sspi->chipselect[spi->chip_select] == 0) {
350 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
351 regval |= SIRFSOC_SPI_CS_IO_OUT;
352 switch (value) {
353 case BITBANG_CS_ACTIVE:
354 if (spi->mode & SPI_CS_HIGH)
355 regval |= SIRFSOC_SPI_CS_IO_OUT;
356 else
357 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
358 break;
359 case BITBANG_CS_INACTIVE:
360 if (spi->mode & SPI_CS_HIGH)
361 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
362 else
363 regval |= SIRFSOC_SPI_CS_IO_OUT;
364 break;
365 }
366 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
367 } else {
368 int gpio = sspi->chipselect[spi->chip_select];
369 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
370 }
371}
372
373static int
374spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
375{
376 struct sirfsoc_spi *sspi;
377 u8 bits_per_word = 0;
378 int hz = 0;
379 u32 regval;
380 u32 txfifo_ctrl, rxfifo_ctrl;
381 u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
382
383 sspi = spi_master_get_devdata(spi->master);
384
Laxman Dewangan766ed702012-12-18 14:25:43 +0530385 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800386 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
387
388 /* Enable IO mode for RX, TX */
389 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
390 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
391 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
392
393 if (regval > 0xFFFF || regval < 0) {
394 dev_err(&spi->dev, "Speed %d not supported\n", hz);
395 return -EINVAL;
396 }
397
398 switch (bits_per_word) {
399 case 8:
400 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
401 sspi->rx_word = spi_sirfsoc_rx_word_u8;
402 sspi->tx_word = spi_sirfsoc_tx_word_u8;
403 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
404 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
405 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
406 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
407 break;
408 case 12:
409 case 16:
410 regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
411 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
412 sspi->rx_word = spi_sirfsoc_rx_word_u16;
413 sspi->tx_word = spi_sirfsoc_tx_word_u16;
414 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
415 SIRFSOC_SPI_FIFO_WIDTH_WORD;
416 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
417 SIRFSOC_SPI_FIFO_WIDTH_WORD;
418 break;
419 case 32:
420 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
421 sspi->rx_word = spi_sirfsoc_rx_word_u32;
422 sspi->tx_word = spi_sirfsoc_tx_word_u32;
423 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
424 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
425 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
426 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
427 break;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800428 }
429
430 if (!(spi->mode & SPI_CS_HIGH))
431 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
432 if (!(spi->mode & SPI_LSB_FIRST))
433 regval |= SIRFSOC_SPI_TRAN_MSB;
434 if (spi->mode & SPI_CPOL)
435 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
436
437 /*
438 * Data should be driven at least 1/2 cycle before the fetch edge to make
439 * sure that data gets stable at the fetch edge.
440 */
441 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
442 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
443 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
444 else
445 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
446
447 writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
448 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
449 SIRFSOC_SPI_FIFO_HC(2),
450 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
451 writel(SIRFSOC_SPI_FIFO_SC(2) |
452 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
453 SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
454 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
455 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
456 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
457
458 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
459 return 0;
460}
461
462static int spi_sirfsoc_setup(struct spi_device *spi)
463{
464 struct sirfsoc_spi *sspi;
465
466 if (!spi->max_speed_hz)
467 return -EINVAL;
468
469 sspi = spi_master_get_devdata(spi->master);
470
471 if (!spi->bits_per_word)
472 spi->bits_per_word = 8;
473
474 return spi_sirfsoc_setup_transfer(spi, NULL);
475}
476
Grant Likelyfd4a3192012-12-07 16:57:14 +0000477static int spi_sirfsoc_probe(struct platform_device *pdev)
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800478{
479 struct sirfsoc_spi *sspi;
480 struct spi_master *master;
481 struct resource *mem_res;
482 int num_cs, cs_gpio, irq;
483 int i;
484 int ret;
485
486 ret = of_property_read_u32(pdev->dev.of_node,
487 "sirf,spi-num-chipselects", &num_cs);
488 if (ret < 0) {
489 dev_err(&pdev->dev, "Unable to get chip select number\n");
490 goto err_cs;
491 }
492
493 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
494 if (!master) {
495 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
496 return -ENOMEM;
497 }
498 platform_set_drvdata(pdev, master);
499 sspi = spi_master_get_devdata(master);
500
501 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
502 if (!mem_res) {
503 dev_err(&pdev->dev, "Unable to get IO resource\n");
504 ret = -ENODEV;
505 goto free_master;
506 }
507 master->num_chipselect = num_cs;
508
509 for (i = 0; i < master->num_chipselect; i++) {
510 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
511 if (cs_gpio < 0) {
512 dev_err(&pdev->dev, "can't get cs gpio from DT\n");
513 ret = -ENODEV;
514 goto free_master;
515 }
516
517 sspi->chipselect[i] = cs_gpio;
518 if (cs_gpio == 0)
519 continue; /* use cs from spi controller */
520
521 ret = gpio_request(cs_gpio, DRIVER_NAME);
522 if (ret) {
523 while (i > 0) {
524 i--;
525 if (sspi->chipselect[i] > 0)
526 gpio_free(sspi->chipselect[i]);
527 }
528 dev_err(&pdev->dev, "fail to request cs gpios\n");
529 goto free_master;
530 }
531 }
532
Thierry Redingb0ee5602013-01-21 11:09:18 +0100533 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
534 if (IS_ERR(sspi->base)) {
535 ret = PTR_ERR(sspi->base);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800536 goto free_master;
537 }
538
539 irq = platform_get_irq(pdev, 0);
540 if (irq < 0) {
541 ret = -ENXIO;
542 goto free_master;
543 }
544 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
545 DRIVER_NAME, sspi);
546 if (ret)
547 goto free_master;
548
549 sspi->bitbang.master = spi_master_get(master);
550 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
551 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
552 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
553 sspi->bitbang.master->setup = spi_sirfsoc_setup;
554 master->bus_num = pdev->id;
Stephen Warren24778be2013-05-21 20:36:35 -0600555 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
556 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800557 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
558
Barry Song71422f92012-05-15 10:21:00 +0800559 sspi->p = pinctrl_get_select_default(&pdev->dev);
560 ret = IS_ERR(sspi->p);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800561 if (ret)
562 goto free_master;
563
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800564 sspi->clk = clk_get(&pdev->dev, NULL);
565 if (IS_ERR(sspi->clk)) {
566 ret = -EINVAL;
Barry Song71422f92012-05-15 10:21:00 +0800567 goto free_pin;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800568 }
Barry Songe5118cd2012-12-26 10:48:33 +0800569 clk_prepare_enable(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800570 sspi->ctrl_freq = clk_get_rate(sspi->clk);
571
572 init_completion(&sspi->done);
573
574 tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
575 (unsigned long)sspi);
576
577 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
578 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
579 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
580 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
581 /* We are not using dummy delay between command and data */
582 writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
583
584 ret = spi_bitbang_start(&sspi->bitbang);
585 if (ret)
586 goto free_clk;
587
588 dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
589
590 return 0;
591
592free_clk:
Barry Songe5118cd2012-12-26 10:48:33 +0800593 clk_disable_unprepare(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800594 clk_put(sspi->clk);
Barry Song71422f92012-05-15 10:21:00 +0800595free_pin:
596 pinctrl_put(sspi->p);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800597free_master:
598 spi_master_put(master);
599err_cs:
600 return ret;
601}
602
Grant Likelyfd4a3192012-12-07 16:57:14 +0000603static int spi_sirfsoc_remove(struct platform_device *pdev)
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800604{
605 struct spi_master *master;
606 struct sirfsoc_spi *sspi;
607 int i;
608
609 master = platform_get_drvdata(pdev);
610 sspi = spi_master_get_devdata(master);
611
612 spi_bitbang_stop(&sspi->bitbang);
613 for (i = 0; i < master->num_chipselect; i++) {
614 if (sspi->chipselect[i] > 0)
615 gpio_free(sspi->chipselect[i]);
616 }
Barry Songe5118cd2012-12-26 10:48:33 +0800617 clk_disable_unprepare(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800618 clk_put(sspi->clk);
Barry Song71422f92012-05-15 10:21:00 +0800619 pinctrl_put(sspi->p);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800620 spi_master_put(master);
621 return 0;
622}
623
624#ifdef CONFIG_PM
625static int spi_sirfsoc_suspend(struct device *dev)
626{
627 struct platform_device *pdev = to_platform_device(dev);
628 struct spi_master *master = platform_get_drvdata(pdev);
629 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
630
631 clk_disable(sspi->clk);
632 return 0;
633}
634
635static int spi_sirfsoc_resume(struct device *dev)
636{
637 struct platform_device *pdev = to_platform_device(dev);
638 struct spi_master *master = platform_get_drvdata(pdev);
639 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
640
641 clk_enable(sspi->clk);
642 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
643 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
644 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
645 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
646
647 return 0;
648}
649
650static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
651 .suspend = spi_sirfsoc_suspend,
652 .resume = spi_sirfsoc_resume,
653};
654#endif
655
656static const struct of_device_id spi_sirfsoc_of_match[] = {
657 { .compatible = "sirf,prima2-spi", },
Barry Songf3b8a8e2012-12-26 10:48:34 +0800658 { .compatible = "sirf,marco-spi", },
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800659 {}
660};
Arnd Bergmann3af4ed72013-04-23 18:30:41 +0200661MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800662
663static struct platform_driver spi_sirfsoc_driver = {
664 .driver = {
665 .name = DRIVER_NAME,
666 .owner = THIS_MODULE,
667#ifdef CONFIG_PM
668 .pm = &spi_sirfsoc_pm_ops,
669#endif
670 .of_match_table = spi_sirfsoc_of_match,
671 },
672 .probe = spi_sirfsoc_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000673 .remove = spi_sirfsoc_remove,
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800674};
675module_platform_driver(spi_sirfsoc_driver);
676
677MODULE_DESCRIPTION("SiRF SoC SPI master driver");
678MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
679 "Barry Song <Baohua.Song@csr.com>");
680MODULE_LICENSE("GPL v2");