Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Daniel Vetter <daniel.vetter@ffwll.ch> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "i915_drv.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 31 | /** |
| 32 | * DOC: fifo underrun handling |
| 33 | * |
| 34 | * The i915 driver checks for display fifo underruns using the interrupt signals |
| 35 | * provided by the hardware. This is enabled by default and fairly useful to |
| 36 | * debug display issues, especially watermark settings. |
| 37 | * |
| 38 | * If an underrun is detected this is logged into dmesg. To avoid flooding logs |
| 39 | * and occupying the cpu underrun interrupts are disabled after the first |
| 40 | * occurrence until the next modeset on a given pipe. |
| 41 | * |
| 42 | * Note that underrun detection on gmch platforms is a bit more ugly since there |
| 43 | * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe |
| 44 | * interrupt register). Also on some other platforms underrun interrupts are |
| 45 | * shared, which means that if we detect an underrun we need to disable underrun |
| 46 | * reporting on all pipes. |
| 47 | * |
| 48 | * The code also supports underrun detection on the PCH transcoder. |
| 49 | */ |
| 50 | |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 51 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
| 52 | { |
| 53 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 54 | struct intel_crtc *crtc; |
| 55 | enum pipe pipe; |
| 56 | |
| 57 | assert_spin_locked(&dev_priv->irq_lock); |
| 58 | |
| 59 | for_each_pipe(dev_priv, pipe) { |
| 60 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 61 | |
| 62 | if (crtc->cpu_fifo_underrun_disabled) |
| 63 | return false; |
| 64 | } |
| 65 | |
| 66 | return true; |
| 67 | } |
| 68 | |
| 69 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
| 70 | { |
| 71 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 72 | enum pipe pipe; |
| 73 | struct intel_crtc *crtc; |
| 74 | |
| 75 | assert_spin_locked(&dev_priv->irq_lock); |
| 76 | |
| 77 | for_each_pipe(dev_priv, pipe) { |
| 78 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 79 | |
| 80 | if (crtc->pch_fifo_underrun_disabled) |
| 81 | return false; |
| 82 | } |
| 83 | |
| 84 | return true; |
| 85 | } |
| 86 | |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 87 | /** |
| 88 | * i9xx_check_fifo_underruns - check for fifo underruns |
| 89 | * @dev_priv: i915 device instance |
| 90 | * |
| 91 | * This function checks for fifo underruns on GMCH platforms. This needs to be |
| 92 | * done manually on modeset to make sure that we catch all underruns since they |
| 93 | * do not generate an interrupt by themselves on these platforms. |
| 94 | */ |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 95 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv) |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 96 | { |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 97 | struct intel_crtc *crtc; |
| 98 | |
| 99 | spin_lock_irq(&dev_priv->irq_lock); |
| 100 | |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 101 | for_each_intel_crtc(dev_priv->dev, crtc) { |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 102 | u32 reg = PIPESTAT(crtc->pipe); |
| 103 | u32 pipestat; |
| 104 | |
| 105 | if (crtc->cpu_fifo_underrun_disabled) |
| 106 | continue; |
| 107 | |
| 108 | pipestat = I915_READ(reg) & 0xffff0000; |
| 109 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) |
| 110 | continue; |
| 111 | |
| 112 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
| 113 | POSTING_READ(reg); |
| 114 | |
| 115 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); |
| 116 | } |
| 117 | |
| 118 | spin_unlock_irq(&dev_priv->irq_lock); |
| 119 | } |
| 120 | |
| 121 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 122 | enum pipe pipe, |
| 123 | bool enable, bool old) |
| 124 | { |
| 125 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 126 | u32 reg = PIPESTAT(pipe); |
| 127 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
| 128 | |
| 129 | assert_spin_locked(&dev_priv->irq_lock); |
| 130 | |
| 131 | if (enable) { |
| 132 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
| 133 | POSTING_READ(reg); |
| 134 | } else { |
| 135 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) |
| 136 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
| 141 | enum pipe pipe, bool enable) |
| 142 | { |
| 143 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 144 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
| 145 | DE_PIPEB_FIFO_UNDERRUN; |
| 146 | |
| 147 | if (enable) |
| 148 | ironlake_enable_display_irq(dev_priv, bit); |
| 149 | else |
| 150 | ironlake_disable_display_irq(dev_priv, bit); |
| 151 | } |
| 152 | |
| 153 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
| 154 | enum pipe pipe, |
| 155 | bool enable, bool old) |
| 156 | { |
| 157 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 158 | if (enable) { |
| 159 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
| 160 | |
| 161 | if (!ivb_can_enable_err_int(dev)) |
| 162 | return; |
| 163 | |
| 164 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 165 | } else { |
| 166 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 167 | |
| 168 | if (old && |
| 169 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { |
| 170 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
| 171 | pipe_name(pipe)); |
| 172 | } |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
| 177 | enum pipe pipe, bool enable) |
| 178 | { |
| 179 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 180 | |
| 181 | assert_spin_locked(&dev_priv->irq_lock); |
| 182 | |
| 183 | if (enable) |
| 184 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; |
| 185 | else |
| 186 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; |
| 187 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 188 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
| 189 | } |
| 190 | |
| 191 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 192 | enum transcoder pch_transcoder, |
| 193 | bool enable) |
| 194 | { |
| 195 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 196 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
| 197 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
| 198 | |
| 199 | if (enable) |
| 200 | ibx_enable_display_interrupt(dev_priv, bit); |
| 201 | else |
| 202 | ibx_disable_display_interrupt(dev_priv, bit); |
| 203 | } |
| 204 | |
| 205 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
| 206 | enum transcoder pch_transcoder, |
| 207 | bool enable, bool old) |
| 208 | { |
| 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 210 | |
| 211 | if (enable) { |
| 212 | I915_WRITE(SERR_INT, |
| 213 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
| 214 | |
| 215 | if (!cpt_can_enable_serr_int(dev)) |
| 216 | return; |
| 217 | |
| 218 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
| 219 | } else { |
| 220 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
| 221 | |
| 222 | if (old && I915_READ(SERR_INT) & |
| 223 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { |
| 224 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
| 225 | transcoder_name(pch_transcoder)); |
| 226 | } |
| 227 | } |
| 228 | } |
| 229 | |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 230 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 231 | enum pipe pipe, bool enable) |
| 232 | { |
| 233 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 234 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 236 | bool old; |
| 237 | |
| 238 | assert_spin_locked(&dev_priv->irq_lock); |
| 239 | |
| 240 | old = !intel_crtc->cpu_fifo_underrun_disabled; |
| 241 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
| 242 | |
| 243 | if (HAS_GMCH_DISPLAY(dev)) |
| 244 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
| 245 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
| 246 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
| 247 | else if (IS_GEN7(dev)) |
| 248 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
| 249 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
| 250 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
| 251 | |
| 252 | return old; |
| 253 | } |
| 254 | |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 255 | /** |
| 256 | * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state |
| 257 | * @dev_priv: i915 device instance |
| 258 | * @pipe: (CPU) pipe to set state for |
| 259 | * @enable: whether underruns should be reported or not |
| 260 | * |
| 261 | * This function sets the fifo underrun state for @pipe. It is used in the |
| 262 | * modeset code to avoid false positives since on many platforms underruns are |
| 263 | * expected when disabling or enabling the pipe. |
| 264 | * |
| 265 | * Notice that on some platforms disabling underrun reports for one pipe |
| 266 | * disables for all due to shared interrupts. Actual reporting is still per-pipe |
| 267 | * though. |
| 268 | * |
| 269 | * Returns the previous state of underrun reporting. |
| 270 | */ |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 271 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 272 | enum pipe pipe, bool enable) |
| 273 | { |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 274 | unsigned long flags; |
| 275 | bool ret; |
| 276 | |
| 277 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 278 | ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe, |
| 279 | enable); |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 280 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 281 | |
| 282 | return ret; |
| 283 | } |
| 284 | |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 285 | /** |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 286 | * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state |
| 287 | * @dev_priv: i915 device instance |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 288 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 289 | * @enable: whether underruns should be reported or not |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 290 | * |
| 291 | * This function makes us disable or enable PCH fifo underruns for a specific |
| 292 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
| 293 | * underrun reporting for one transcoder may also disable all the other PCH |
| 294 | * error interruts for the other transcoders, due to the fact that there's just |
| 295 | * one interrupt mask/enable bit for all the transcoders. |
| 296 | * |
| 297 | * Returns the previous state of underrun reporting. |
| 298 | */ |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 299 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 300 | enum transcoder pch_transcoder, |
| 301 | bool enable) |
| 302 | { |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 303 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
| 304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 305 | unsigned long flags; |
| 306 | bool old; |
| 307 | |
| 308 | /* |
| 309 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
| 310 | * has only one pch transcoder A that all pipes can use. To avoid racy |
| 311 | * pch transcoder -> pipe lookups from interrupt code simply store the |
| 312 | * underrun statistics in crtc A. Since we never expose this anywhere |
| 313 | * nor use it outside of the fifo underrun code here using the "wrong" |
| 314 | * crtc on LPT won't cause issues. |
| 315 | */ |
| 316 | |
| 317 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 318 | |
| 319 | old = !intel_crtc->pch_fifo_underrun_disabled; |
| 320 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
| 321 | |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 322 | if (HAS_PCH_IBX(dev_priv->dev)) |
| 323 | ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, |
| 324 | enable); |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 325 | else |
Daniel Vetter | a72e4c9 | 2014-09-30 10:56:47 +0200 | [diff] [blame] | 326 | cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, |
| 327 | enable, old); |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 328 | |
| 329 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 330 | return old; |
| 331 | } |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 332 | |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 333 | /** |
Kumar Amit Mehta | cea3bf8 | 2015-01-26 17:47:32 +0100 | [diff] [blame] | 334 | * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 335 | * @dev_priv: i915 device instance |
| 336 | * @pipe: (CPU) pipe to set state for |
| 337 | * |
| 338 | * This handles a CPU fifo underrun interrupt, generating an underrun warning |
| 339 | * into dmesg if underrun reporting is enabled and then disables the underrun |
| 340 | * interrupt to avoid an irq storm. |
| 341 | */ |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 342 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 343 | enum pipe pipe) |
| 344 | { |
Chris Wilson | 54fc7c1 | 2015-02-26 15:53:02 +0000 | [diff] [blame] | 345 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 346 | |
| 347 | /* We may be called too early in init, thanks BIOS! */ |
| 348 | if (crtc == NULL) |
| 349 | return; |
| 350 | |
Daniel Vetter | 0f239f4 | 2014-09-30 10:56:49 +0200 | [diff] [blame] | 351 | /* GMCH can't disable fifo underruns, filter them. */ |
| 352 | if (HAS_GMCH_DISPLAY(dev_priv->dev) && |
Chris Wilson | 54fc7c1 | 2015-02-26 15:53:02 +0000 | [diff] [blame] | 353 | to_intel_crtc(crtc)->cpu_fifo_underrun_disabled) |
Daniel Vetter | 0f239f4 | 2014-09-30 10:56:49 +0200 | [diff] [blame] | 354 | return; |
| 355 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 356 | if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) |
| 357 | DRM_ERROR("CPU pipe %c FIFO underrun\n", |
| 358 | pipe_name(pipe)); |
| 359 | } |
| 360 | |
Daniel Vetter | ef07388 | 2014-09-30 10:56:50 +0200 | [diff] [blame] | 361 | /** |
| 362 | * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt |
| 363 | * @dev_priv: i915 device instance |
| 364 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
| 365 | * |
| 366 | * This handles a PCH fifo underrun interrupt, generating an underrun warning |
| 367 | * into dmesg if underrun reporting is enabled and then disables the underrun |
| 368 | * interrupt to avoid an irq storm. |
| 369 | */ |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 370 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 371 | enum transcoder pch_transcoder) |
| 372 | { |
| 373 | if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, |
| 374 | false)) |
| 375 | DRM_ERROR("PCH transcoder %c FIFO underrun\n", |
| 376 | transcoder_name(pch_transcoder)); |
| 377 | } |