Srinivas Ramana | 24aa41b | 2017-09-13 14:18:19 +0530 | [diff] [blame^] | 1 | Qualcomm MSM8953 TLMM block |
| 2 | |
| 3 | This binding describes the Top Level Mode Multiplexer block found in the |
| 4 | MSM8953 platform. |
| 5 | |
| 6 | - compatible: |
| 7 | Usage: required |
| 8 | Value type: <string> |
| 9 | Definition: must be "qcom,msm8953-pinctrl" |
| 10 | |
| 11 | - reg: |
| 12 | Usage: required |
| 13 | Value type: <prop-encoded-array> |
| 14 | Definition: the base address and size of the TLMM register space. |
| 15 | |
| 16 | - interrupts: |
| 17 | Usage: required |
| 18 | Value type: <prop-encoded-array> |
| 19 | Definition: should specify the TLMM summary IRQ. |
| 20 | |
| 21 | - interrupt-controller: |
| 22 | Usage: required |
| 23 | Value type: <none> |
| 24 | Definition: identifies this node as an interrupt controller |
| 25 | |
| 26 | - #interrupt-cells: |
| 27 | Usage: required |
| 28 | Value type: <u32> |
| 29 | Definition: must be 2. Specifying the pin number and flags, as defined |
| 30 | in <dt-bindings/interrupt-controller/irq.h> |
| 31 | |
| 32 | - gpio-controller: |
| 33 | Usage: required |
| 34 | Value type: <none> |
| 35 | Definition: identifies this node as a gpio controller |
| 36 | |
| 37 | - #gpio-cells: |
| 38 | Usage: required |
| 39 | Value type: <u32> |
| 40 | Definition: must be 2. Specifying the pin number and flags, as defined |
| 41 | in <dt-bindings/gpio/gpio.h> |
| 42 | |
| 43 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for |
| 44 | a general description of GPIO and interrupt bindings. |
| 45 | |
| 46 | Please refer to pinctrl-bindings.txt in this directory for details of the |
| 47 | common pinctrl bindings used by client devices, including the meaning of the |
| 48 | phrase "pin configuration node". |
| 49 | |
| 50 | The pin configuration nodes act as a container for an arbitrary number of |
| 51 | subnodes. Each of these subnodes represents some desired configuration for a |
| 52 | pin, a group, or a list of pins or groups. This configuration can include the |
| 53 | mux function to select on those pin(s)/group(s), and various pin configuration |
| 54 | parameters, such as pull-up, drive strength, etc. |
| 55 | |
| 56 | |
| 57 | PIN CONFIGURATION NODES: |
| 58 | |
| 59 | The name of each subnode is not important; all subnodes should be enumerated |
| 60 | and processed purely based on their content. |
| 61 | |
| 62 | Each subnode only affects those parameters that are explicitly listed. In |
| 63 | other words, a subnode that lists a mux function but no pin configuration |
| 64 | parameters implies no information about any pin configuration parameters. |
| 65 | Similarly, a pin subnode that describes a pullup parameter implies no |
| 66 | information about e.g. the mux function. |
| 67 | |
| 68 | |
| 69 | The following generic properties as defined in pinctrl-bindings.txt are valid |
| 70 | to specify in a pin configuration subnode: |
| 71 | |
| 72 | - pins: |
| 73 | Usage: required |
| 74 | Value type: <string-array> |
| 75 | Definition: List of gpio pins affected by the properties specified in |
| 76 | this subnode. |
| 77 | Valid pins are: |
| 78 | gpio0-gpio141, |
| 79 | sdc1_clk, |
| 80 | sdc1_cmd, |
| 81 | sdc1_data, |
| 82 | sdc1_rclk, |
| 83 | sdc2_clk, |
| 84 | sdc2_cmd, |
| 85 | sdc2_data, |
| 86 | qdsd_cmd, |
| 87 | qdsd_data0, |
| 88 | qdsd_data1, |
| 89 | qdsd_data2, |
| 90 | qdsd_data3 |
| 91 | |
| 92 | - function: |
| 93 | Usage: required |
| 94 | Value type: <string> |
| 95 | Definition: Specify the alternative function to be configured for the |
| 96 | specified pins. Functions are only valid for gpio pins. |
| 97 | Valid values are: |
| 98 | gpio, blsp_spi1, smb_int, adsp_ext, prng_rosc, blsp_i2c1, |
| 99 | qdss_cti_trig_out_b0, qdss_cti_trig_out_a1, blsp_spi2, blsp_uart2, |
| 100 | ldo_update, dac_calib0, ldo_en, blsp_i2c2, gcc_gp1_clk_b, |
| 101 | atest_gpsadc_dtest0_native, blsp_spi3, qdss_tracedata_b, |
| 102 | pwr_modem_enabled_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b, hall_int, |
| 103 | blsp_spi4, blsp_uart4, pwr_nav_enabled_b, dac_calib1, cap_int, |
| 104 | pwr_crypto_enabled_b, dac_calib2, blsp_i2c4, nfc_disable, blsp_spi5, |
| 105 | blsp_uart5, qdss_traceclk_a, atest_bbrx1, nfc_irq, m_voc, |
| 106 | qdss_cti_trig_in_a0, atest_bbrx0, blsp_i2c5, qdss_tracectl_a, |
| 107 | atest_gpsadc_dtest1_native, qdss_tracedata_a, blsp_spi6, blsp_uart6, |
| 108 | qdss_tracectl_b, dac_calib15, qdss_cti_trig_in_b0, dac_calib16, blsp_i2c6, |
| 109 | qdss_traceclk_b, atest_wlan0, atest_wlan1, mdp_vsync, pri_mi2s_mclk_a, |
| 110 | sec_mi2s_mclk_a, qdss_cti_trig_out_b1, cam_mclk, dac_calib3, cci_i2c, |
| 111 | pwr_modem_enabled_a, dac_calib4, dac_calib19, flash_strobe, cci_timer0, |
| 112 | cci_timer1, cam_irq, cci_timer2, blsp1_spi, pwr_nav_enabled_a, ois_sync, |
| 113 | cci_timer3, cci_timer4, blsp3_spi, qdss_cti_trig_out_a0, dac_calib7, |
| 114 | accel_int, gcc_gp1_clk_a, dac_calib8, alsp_int, gcc_gp2_clk_a, dac_calib9, |
| 115 | mag_int, gcc_gp3_clk_a, pwr_crypto_enabled_a, cci_async, cam1_standby, |
| 116 | dac_calib5, cam1_rst, dac_calib6, dac_calib10, gyro_int, dac_calib11, |
| 117 | pressure_int, dac_calib12, blsp6_spi, dac_calib13, fp_int, |
| 118 | qdss_cti_trig_in_b1, dac_calib14, uim_batt, cam0_ldo, sd_write, uim1_data, |
| 119 | uim1_clk, uim1_reset, uim1_present, uim2_data, uim2_clk, uim2_reset, |
| 120 | uim2_present, ts_xvdd, mipi_dsi0, nfc_dwl, us_euro, atest_char3, dbg_out, |
| 121 | bimc_dte0, ts_resout, ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset, |
| 122 | cdc_pdm0, atest_char1, ebi_cdc, dac_calib17, us_emitter, atest_char0, |
| 123 | pri_mi2s_mclk_b, lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1, |
| 124 | codec_int2, wcss_bt, atest_char2, ebi_ch0, wcss_wlan2, wcss_wlan1, |
| 125 | wcss_wlan0, wcss_wlan, wcss_fm, ext_lpass, mss_lte, key_volp, pbs0, |
| 126 | cri_trng0, key_snapshot, pbs1, cri_trng1, key_focus, pbs2, cri_trng, |
| 127 | gcc_tlmm, key_home, pwr_down, dmic0_clk, blsp7_spi, hdmi_int, dmic0_data, |
| 128 | qdss_cti_trig_in_a1, pri_mi2s_ws, wsa_io, wsa_en, blsp_spi8, wsa_irq, |
| 129 | blsp_i2c8, gcc_plltest, nav_pps_in_a, pa_indicator, nav_pps_in_b, nav_pps, |
| 130 | modem_tsync, nav_tsync, ssbi_wtr1, gsm1_tx, dac_calib18, gsm0_tx, |
| 131 | atest_char, atest_tsens, bimc_dte1, dac_calib20, cam2_rst, ddr_bist, |
| 132 | dac_calib21, cam2_standby, dac_calib22, cam3_rst, dac_calib23, |
| 133 | cam3_standby, dac_calib24, sdcard_det, dac_calib25, cam1_ldo, sec_mi2s, |
| 134 | blsp_spi7, blsp_i2c7, ss_switch, tsens_max |
| 135 | |
| 136 | - bias-disable: |
| 137 | Usage: optional |
| 138 | Value type: <none> |
| 139 | Definition: The specified pins should be configued as no pull. |
| 140 | |
| 141 | - bias-pull-down: |
| 142 | Usage: optional |
| 143 | Value type: <none> |
| 144 | Definition: The specified pins should be configued as pull down. |
| 145 | |
| 146 | - bias-pull-up: |
| 147 | Usage: optional |
| 148 | Value type: <none> |
| 149 | Definition: The specified pins should be configued as pull up. |
| 150 | |
| 151 | - output-high: |
| 152 | Usage: optional |
| 153 | Value type: <none> |
| 154 | Definition: The specified pins are configured in output mode, driven |
| 155 | high. |
| 156 | Not valid for sdc pins. |
| 157 | |
| 158 | - output-low: |
| 159 | Usage: optional |
| 160 | Value type: <none> |
| 161 | Definition: The specified pins are configured in output mode, driven |
| 162 | low. |
| 163 | Not valid for sdc pins. |
| 164 | |
| 165 | - drive-strength: |
| 166 | Usage: optional |
| 167 | Value type: <u32> |
| 168 | Definition: Selects the drive strength for the specified pins, in mA. |
| 169 | Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 |
| 170 | |
| 171 | Example: |
| 172 | |
| 173 | tlmm: pinctrl@1000000 { |
| 174 | compatible = "qcom,msm8953-pinctrl"; |
| 175 | reg = <0x1000000 0x300000>; |
| 176 | interrupts = <0 208 0>; |
| 177 | gpio-controller; |
| 178 | #gpio-cells = <2>; |
| 179 | interrupt-controller; |
| 180 | #interrupt-cells = <2>; |
| 181 | |
| 182 | pmx-uartconsole { |
| 183 | uart_console_active: uart_console_active { |
| 184 | mux { |
| 185 | pins = "gpio4", "gpio5"; |
| 186 | function = "blsp_uart2"; |
| 187 | }; |
| 188 | |
| 189 | config { |
| 190 | pins = "gpio4", "gpio5"; |
| 191 | drive-strength = <2>; |
| 192 | bias-disable; |
| 193 | }; |
| 194 | }; |
| 195 | |
| 196 | uart_console_sleep: uart_console_sleep { |
| 197 | mux { |
| 198 | pins = "gpio4", "gpio5"; |
| 199 | function = "blsp_uart2"; |
| 200 | }; |
| 201 | |
| 202 | config { |
| 203 | pins = "gpio4", "gpio5"; |
| 204 | drive-strength = <2>; |
| 205 | bias-pull-down; |
| 206 | }; |
| 207 | }; |
| 208 | |
| 209 | }; |
| 210 | }; |