Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 2515e8bbc5dca415c5a810b8d5c6aa6acec1903c / . / arch / arm / boot / dts / wm8650.dtsi
blob: dd8464eeb40d69bddd1924bd445b9d11d0600d37 [file] [log] [blame]
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]1/*
2 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8650";
13
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "simple-bus";
18 ranges;
19 interrupt-parent = <&intc0>;
20
21 intc0: interrupt-controller@d8140000 {
22 compatible = "via,vt8500-intc";
23 interrupt-controller;
24 reg = <0xd8140000 0x10000>;
25 #interrupt-cells = <1>;
26 };
27
28 /* Secondary IC cascaded to intc0 */
29 intc1: interrupt-controller@d8150000 {
30 compatible = "via,vt8500-intc";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0xD8150000 0x10000>;
34 interrupts = <56 57 58 59 60 61 62 63>;
35 };
36
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]37 pinctrl: pinctrl@d8110000 {
38 compatible = "wm,wm8650-pinctrl";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]39 reg = <0xd8110000 0x10000>;
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]40 interrupt-controller;
41 #interrupt-cells = <2>;
42 gpio-controller;
43 #gpio-cells = <2>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]44 };
45
46 pmc@d8130000 {
47 compatible = "via,vt8500-pmc";
48 reg = <0xd8130000 0x1000>;
49
50 clocks {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ref25: ref25M {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <25000000>;
58 };
59
60 ref24: ref24M {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 };
65
66 plla: plla {
67 #clock-cells = <0>;
68 compatible = "wm,wm8650-pll-clock";
69 clocks = <&ref25>;
70 reg = <0x200>;
71 };
72
73 pllb: pllb {
74 #clock-cells = <0>;
75 compatible = "wm,wm8650-pll-clock";
76 clocks = <&ref25>;
77 reg = <0x204>;
78 };
79
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]80 clkuart0: uart0 {
81 #clock-cells = <0>;
82 compatible = "via,vt8500-device-clock";
83 clocks = <&ref24>;
84 enable-reg = <0x250>;
85 enable-bit = <1>;
86 };
87
88 clkuart1: uart1 {
89 #clock-cells = <0>;
90 compatible = "via,vt8500-device-clock";
91 clocks = <&ref24>;
92 enable-reg = <0x250>;
93 enable-bit = <2>;
94 };
95
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]96 arm: arm {
97 #clock-cells = <0>;
98 compatible = "via,vt8500-device-clock";
99 clocks = <&plla>;
100 divisor-reg = <0x300>;
101 };
102
103 sdhc: sdhc {
104 #clock-cells = <0>;
105 compatible = "via,vt8500-device-clock";
106 clocks = <&pllb>;
107 divisor-reg = <0x328>;
108 divisor-mask = <0x3f>;
109 enable-reg = <0x254>;
110 enable-bit = <18>;
111 };
112 };
113 };
114
115 timer@d8130100 {
116 compatible = "via,vt8500-timer";
117 reg = <0xd8130100 0x28>;
118 interrupts = <36>;
119 };
120
121 ehci@d8007900 {
122 compatible = "via,vt8500-ehci";
123 reg = <0xd8007900 0x200>;
124 interrupts = <43>;
125 };
126
127 uhci@d8007b00 {
128 compatible = "platform-uhci";
129 reg = <0xd8007b00 0x200>;
130 interrupts = <43>;
131 };
132
Tony Prisk7ab0a482013-04-03 07:20:38 +1300[diff] [blame]133 fb: fb@d8050800 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]134 compatible = "wm,wm8505-fb";
135 reg = <0xd8050800 0x200>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]136 };
137
138 ge_rops@d8050400 {
139 compatible = "wm,prizm-ge-rops";
140 reg = <0xd8050400 0x100>;
141 };
142
143 uart@d8200000 {
144 compatible = "via,vt8500-uart";
145 reg = <0xd8200000 0x1040>;
146 interrupts = <32>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]147 clocks = <&clkuart0>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]148 };
149
150 uart@d82b0000 {
151 compatible = "via,vt8500-uart";
152 reg = <0xd82b0000 0x1040>;
153 interrupts = <33>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]154 clocks = <&clkuart1>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]155 };
156
157 rtc@d8100000 {
158 compatible = "via,vt8500-rtc";
159 reg = <0xd8100000 0x10000>;
160 interrupts = <48>;
161 };
162 };
163};