blob: 634c3d37f7b5e010fe315e0734c4205ab4abce58 [file] [log] [blame]
Grant Likelyc103de22011-06-04 18:38:28 -06001/*
2 * Moorestown platform Langwell chip GPIO driver
3 *
Alek Du8bf02612009-09-22 16:46:36 -07004 * Copyright (c) 2008 - 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/* Supports:
21 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070022 * Medfield platform Penwell chip.
Alan Cox72b43792010-10-27 15:33:23 -070023 * Whitney point.
Alek Du8bf02612009-09-22 16:46:36 -070024 */
25
26#include <linux/module.h>
27#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070028#include <linux/platform_device.h>
Alek Du8bf02612009-09-22 16:46:36 -070029#include <linux/kernel.h>
30#include <linux/delay.h>
31#include <linux/stddef.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/irq.h>
35#include <linux/io.h>
36#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090037#include <linux/slab.h>
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010038#include <linux/pm_runtime.h>
Mika Westerberg465f2bd2012-05-02 11:15:50 +030039#include <linux/irqdomain.h>
Alek Du8bf02612009-09-22 16:46:36 -070040
Alek Du8081c842010-05-26 14:42:25 -070041/*
42 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
43 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
44 * registers to control them, so we only define the order here instead of a
45 * structure, to get a bit offset for a pin (use GPDR as an example):
46 *
47 * nreg = ngpio / 32;
48 * reg = offset / 32;
49 * bit = offset % 32;
50 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 *
52 * so the bit of reg_addr is to control pin offset's GPDR feature
53*/
54
55enum GPIO_REG {
56 GPLR = 0, /* pin level read-only */
57 GPDR, /* pin direction */
58 GPSR, /* pin set */
59 GPCR, /* pin clear */
60 GRER, /* rising edge detect */
61 GFER, /* falling edge detect */
62 GEDR, /* edge detect result */
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030063 GAFR, /* alt function */
Alek Du8bf02612009-09-22 16:46:36 -070064};
65
66struct lnw_gpio {
67 struct gpio_chip chip;
Alek Du8081c842010-05-26 14:42:25 -070068 void *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070069 spinlock_t lock;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010070 struct pci_dev *pdev;
Mika Westerberg465f2bd2012-05-02 11:15:50 +030071 struct irq_domain *domain;
Alek Du8bf02612009-09-22 16:46:36 -070072};
73
David Cohen46ebfbc2012-12-20 14:45:51 -080074#define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
75
Alek Du8081c842010-05-26 14:42:25 -070076static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
77 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070078{
David Cohen46ebfbc2012-12-20 14:45:51 -080079 struct lnw_gpio *lnw = to_lnw_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -070080 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070081 u8 reg = offset / 32;
Alek Du8081c842010-05-26 14:42:25 -070082 void __iomem *ptr;
Alek Du8bf02612009-09-22 16:46:36 -070083
Alek Du8081c842010-05-26 14:42:25 -070084 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
85 return ptr;
86}
87
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030088static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
89 enum GPIO_REG reg_type)
90{
David Cohen46ebfbc2012-12-20 14:45:51 -080091 struct lnw_gpio *lnw = to_lnw_priv(chip);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030092 unsigned nreg = chip->ngpio / 32;
93 u8 reg = offset / 16;
94 void __iomem *ptr;
95
96 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
97 return ptr;
98}
99
100static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
101{
102 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
103 u32 value = readl(gafr);
104 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
105
106 if (af) {
107 value &= ~(3 << shift);
108 writel(value, gafr);
109 }
110 return 0;
111}
112
Alek Du8081c842010-05-26 14:42:25 -0700113static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
114{
115 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
116
Alek Du8bf02612009-09-22 16:46:36 -0700117 return readl(gplr) & BIT(offset % 32);
118}
119
120static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
121{
Alek Du8bf02612009-09-22 16:46:36 -0700122 void __iomem *gpsr, *gpcr;
123
124 if (value) {
Alek Du8081c842010-05-26 14:42:25 -0700125 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -0700126 writel(BIT(offset % 32), gpsr);
127 } else {
Alek Du8081c842010-05-26 14:42:25 -0700128 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -0700129 writel(BIT(offset % 32), gpcr);
130 }
131}
132
133static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
134{
David Cohen46ebfbc2012-12-20 14:45:51 -0800135 struct lnw_gpio *lnw = to_lnw_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700136 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700137 u32 value;
138 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700139
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100140 if (lnw->pdev)
141 pm_runtime_get(&lnw->pdev->dev);
142
Alek Du8bf02612009-09-22 16:46:36 -0700143 spin_lock_irqsave(&lnw->lock, flags);
144 value = readl(gpdr);
145 value &= ~BIT(offset % 32);
146 writel(value, gpdr);
147 spin_unlock_irqrestore(&lnw->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100148
149 if (lnw->pdev)
150 pm_runtime_put(&lnw->pdev->dev);
151
Alek Du8bf02612009-09-22 16:46:36 -0700152 return 0;
153}
154
155static int lnw_gpio_direction_output(struct gpio_chip *chip,
156 unsigned offset, int value)
157{
David Cohen46ebfbc2012-12-20 14:45:51 -0800158 struct lnw_gpio *lnw = to_lnw_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700159 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700160 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700161
162 lnw_gpio_set(chip, offset, value);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100163
164 if (lnw->pdev)
165 pm_runtime_get(&lnw->pdev->dev);
166
Alek Du8bf02612009-09-22 16:46:36 -0700167 spin_lock_irqsave(&lnw->lock, flags);
168 value = readl(gpdr);
Justin P. Mattock6eab04a2011-04-08 19:49:08 -0700169 value |= BIT(offset % 32);
Alek Du8bf02612009-09-22 16:46:36 -0700170 writel(value, gpdr);
171 spin_unlock_irqrestore(&lnw->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100172
173 if (lnw->pdev)
174 pm_runtime_put(&lnw->pdev->dev);
175
Alek Du8bf02612009-09-22 16:46:36 -0700176 return 0;
177}
178
179static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
180{
David Cohen46ebfbc2012-12-20 14:45:51 -0800181 struct lnw_gpio *lnw = to_lnw_priv(chip);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300182 return irq_create_mapping(lnw->domain, offset);
Alek Du8bf02612009-09-22 16:46:36 -0700183}
184
Lennert Buytenhek5ffd72c2011-01-12 17:00:13 -0800185static int lnw_irq_type(struct irq_data *d, unsigned type)
Alek Du8bf02612009-09-22 16:46:36 -0700186{
Lennert Buytenhek5ffd72c2011-01-12 17:00:13 -0800187 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300188 u32 gpio = irqd_to_hwirq(d);
Alek Du8bf02612009-09-22 16:46:36 -0700189 unsigned long flags;
190 u32 value;
Alek Du8081c842010-05-26 14:42:25 -0700191 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
192 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700193
Roel Kluin4efec622009-12-15 16:46:18 -0800194 if (gpio >= lnw->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700195 return -EINVAL;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100196
197 if (lnw->pdev)
198 pm_runtime_get(&lnw->pdev->dev);
199
Alek Du8bf02612009-09-22 16:46:36 -0700200 spin_lock_irqsave(&lnw->lock, flags);
201 if (type & IRQ_TYPE_EDGE_RISING)
202 value = readl(grer) | BIT(gpio % 32);
203 else
204 value = readl(grer) & (~BIT(gpio % 32));
205 writel(value, grer);
206
207 if (type & IRQ_TYPE_EDGE_FALLING)
208 value = readl(gfer) | BIT(gpio % 32);
209 else
210 value = readl(gfer) & (~BIT(gpio % 32));
211 writel(value, gfer);
212 spin_unlock_irqrestore(&lnw->lock, flags);
213
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100214 if (lnw->pdev)
215 pm_runtime_put(&lnw->pdev->dev);
216
Alek Du8bf02612009-09-22 16:46:36 -0700217 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700218}
Alek Du8bf02612009-09-22 16:46:36 -0700219
Lennert Buytenhek5ffd72c2011-01-12 17:00:13 -0800220static void lnw_irq_unmask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700221{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700222}
Alek Du8bf02612009-09-22 16:46:36 -0700223
Lennert Buytenhek5ffd72c2011-01-12 17:00:13 -0800224static void lnw_irq_mask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700225{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700226}
Alek Du8bf02612009-09-22 16:46:36 -0700227
228static struct irq_chip lnw_irqchip = {
229 .name = "LNW-GPIO",
Lennert Buytenhek5ffd72c2011-01-12 17:00:13 -0800230 .irq_mask = lnw_irq_mask,
231 .irq_unmask = lnw_irq_unmask,
232 .irq_set_type = lnw_irq_type,
Alek Du8bf02612009-09-22 16:46:36 -0700233};
234
Alek Du8081c842010-05-26 14:42:25 -0700235static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
236 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
237 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
238 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
David Cohen936cb1b2012-12-18 17:52:12 -0800239 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
240 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
Alek Du8bf02612009-09-22 16:46:36 -0700241 { 0, }
242};
243MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
244
245static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
246{
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000247 struct irq_data *data = irq_desc_get_irq_data(desc);
248 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
249 struct irq_chip *chip = irq_data_get_irq_chip(data);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000250 u32 base, gpio, mask;
Thomas Gleixner732063b2011-03-17 19:32:55 +0000251 unsigned long pending;
Alek Du8bf02612009-09-22 16:46:36 -0700252 void __iomem *gedr;
Alek Du8bf02612009-09-22 16:46:36 -0700253
254 /* check GPIO controller to check which pin triggered the interrupt */
Alek Du8081c842010-05-26 14:42:25 -0700255 for (base = 0; base < lnw->chip.ngpio; base += 32) {
256 gedr = gpio_reg(&lnw->chip, base, GEDR);
Mika Westerbergc8f925b2012-05-10 13:01:22 +0300257 while ((pending = readl(gedr))) {
Mathias Nyman2345b202011-07-08 10:02:18 +0100258 gpio = __ffs(pending);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000259 mask = BIT(gpio);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000260 /* Clear before handling so we can't lose an edge */
261 writel(mask, gedr);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300262 generic_handle_irq(irq_find_mapping(lnw->domain,
263 base + gpio));
Thomas Gleixner732063b2011-03-17 19:32:55 +0000264 }
Alek Du8bf02612009-09-22 16:46:36 -0700265 }
Feng Tang0766d202011-01-25 15:07:15 -0800266
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000267 chip->irq_eoi(data);
Alek Du8bf02612009-09-22 16:46:36 -0700268}
269
Mika Westerbergf5f93112012-04-05 12:15:17 +0300270static void lnw_irq_init_hw(struct lnw_gpio *lnw)
271{
272 void __iomem *reg;
273 unsigned base;
274
275 for (base = 0; base < lnw->chip.ngpio; base += 32) {
276 /* Clear the rising-edge detect register */
277 reg = gpio_reg(&lnw->chip, base, GRER);
278 writel(0, reg);
279 /* Clear the falling-edge detect register */
280 reg = gpio_reg(&lnw->chip, base, GFER);
281 writel(0, reg);
282 /* Clear the edge detect status register */
283 reg = gpio_reg(&lnw->chip, base, GEDR);
284 writel(~0, reg);
285 }
286}
287
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300288static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
289 irq_hw_number_t hw)
290{
291 struct lnw_gpio *lnw = d->host_data;
292
293 irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
294 "demux");
295 irq_set_chip_data(virq, lnw);
296 irq_set_irq_type(virq, IRQ_TYPE_NONE);
297
298 return 0;
299}
300
301static const struct irq_domain_ops lnw_gpio_irq_ops = {
302 .map = lnw_gpio_irq_map,
303 .xlate = irq_domain_xlate_twocell,
304};
305
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100306static int lnw_gpio_runtime_idle(struct device *dev)
307{
308 int err = pm_schedule_suspend(dev, 500);
309
310 if (!err)
311 return 0;
312
313 return -EBUSY;
314}
315
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100316static const struct dev_pm_ops lnw_gpio_pm_ops = {
David Cohen46ebfbc2012-12-20 14:45:51 -0800317 SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100318};
319
Bill Pemberton38363092012-11-19 13:22:34 -0500320static int lnw_gpio_probe(struct pci_dev *pdev,
Alek Du8bf02612009-09-22 16:46:36 -0700321 const struct pci_device_id *id)
322{
323 void *base;
Alek Du8bf02612009-09-22 16:46:36 -0700324 resource_size_t start, len;
325 struct lnw_gpio *lnw;
Alek Du8bf02612009-09-22 16:46:36 -0700326 u32 gpio_base;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200327 int retval;
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300328 int ngpio = id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700329
330 retval = pci_enable_device(pdev);
331 if (retval)
Mika Westerberg8302c742012-04-05 12:15:15 +0300332 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700333
334 retval = pci_request_regions(pdev, "langwell_gpio");
335 if (retval) {
336 dev_err(&pdev->dev, "error requesting resources\n");
David Cohen46ebfbc2012-12-20 14:45:51 -0800337 goto err_pci_req_region;
Alek Du8bf02612009-09-22 16:46:36 -0700338 }
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300339 /* get the gpio_base from bar1 */
Alek Du8bf02612009-09-22 16:46:36 -0700340 start = pci_resource_start(pdev, 1);
341 len = pci_resource_len(pdev, 1);
342 base = ioremap_nocache(start, len);
343 if (!base) {
344 dev_err(&pdev->dev, "error mapping bar1\n");
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200345 retval = -EFAULT;
David Cohen46ebfbc2012-12-20 14:45:51 -0800346 goto err_ioremap;
Alek Du8bf02612009-09-22 16:46:36 -0700347 }
Alek Du8bf02612009-09-22 16:46:36 -0700348 gpio_base = *((u32 *)base + 1);
349 /* release the IO mapping, since we already get the info from bar1 */
350 iounmap(base);
351 /* get the register base from bar0 */
352 start = pci_resource_start(pdev, 0);
353 len = pci_resource_len(pdev, 0);
Mika Westerberg8302c742012-04-05 12:15:15 +0300354 base = devm_ioremap_nocache(&pdev->dev, start, len);
Alek Du8bf02612009-09-22 16:46:36 -0700355 if (!base) {
356 dev_err(&pdev->dev, "error mapping bar0\n");
357 retval = -EFAULT;
David Cohen46ebfbc2012-12-20 14:45:51 -0800358 goto err_ioremap;
Alek Du8bf02612009-09-22 16:46:36 -0700359 }
360
David Cohen46ebfbc2012-12-20 14:45:51 -0800361 lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
Alek Du8bf02612009-09-22 16:46:36 -0700362 if (!lnw) {
363 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
364 retval = -ENOMEM;
David Cohen46ebfbc2012-12-20 14:45:51 -0800365 goto err_ioremap;
Alek Du8bf02612009-09-22 16:46:36 -0700366 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300367
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300368 lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
369 &lnw_gpio_irq_ops, lnw);
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200370 if (!lnw->domain) {
371 retval = -ENOMEM;
David Cohen46ebfbc2012-12-20 14:45:51 -0800372 goto err_ioremap;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200373 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300374
Alek Du8bf02612009-09-22 16:46:36 -0700375 lnw->reg_base = base;
Alek Du8bf02612009-09-22 16:46:36 -0700376 lnw->chip.label = dev_name(&pdev->dev);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300377 lnw->chip.request = lnw_gpio_request;
Alek Du8bf02612009-09-22 16:46:36 -0700378 lnw->chip.direction_input = lnw_gpio_direction_input;
379 lnw->chip.direction_output = lnw_gpio_direction_output;
380 lnw->chip.get = lnw_gpio_get;
381 lnw->chip.set = lnw_gpio_set;
382 lnw->chip.to_irq = lnw_gpio_to_irq;
383 lnw->chip.base = gpio_base;
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300384 lnw->chip.ngpio = ngpio;
Alek Du8bf02612009-09-22 16:46:36 -0700385 lnw->chip.can_sleep = 0;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100386 lnw->pdev = pdev;
Alek Du8bf02612009-09-22 16:46:36 -0700387 pci_set_drvdata(pdev, lnw);
388 retval = gpiochip_add(&lnw->chip);
389 if (retval) {
390 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
David Cohen46ebfbc2012-12-20 14:45:51 -0800391 goto err_ioremap;
Alek Du8bf02612009-09-22 16:46:36 -0700392 }
Mika Westerbergf5f93112012-04-05 12:15:17 +0300393
394 lnw_irq_init_hw(lnw);
395
Thomas Gleixner674db902011-03-17 19:32:52 +0000396 irq_set_handler_data(pdev->irq, lnw);
397 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
Alek Du8bf02612009-09-22 16:46:36 -0700398
399 spin_lock_init(&lnw->lock);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100400
401 pm_runtime_put_noidle(&pdev->dev);
402 pm_runtime_allow(&pdev->dev);
403
Mika Westerberg8302c742012-04-05 12:15:15 +0300404 return 0;
405
David Cohen46ebfbc2012-12-20 14:45:51 -0800406err_ioremap:
Alek Du8bf02612009-09-22 16:46:36 -0700407 pci_release_regions(pdev);
David Cohen46ebfbc2012-12-20 14:45:51 -0800408err_pci_req_region:
Alek Du8bf02612009-09-22 16:46:36 -0700409 pci_disable_device(pdev);
Alek Du8bf02612009-09-22 16:46:36 -0700410 return retval;
411}
412
413static struct pci_driver lnw_gpio_driver = {
414 .name = "langwell_gpio",
415 .id_table = lnw_gpio_ids,
416 .probe = lnw_gpio_probe,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100417 .driver = {
418 .pm = &lnw_gpio_pm_ops,
419 },
Alek Du8bf02612009-09-22 16:46:36 -0700420};
421
Alan Cox72b43792010-10-27 15:33:23 -0700422
Bill Pemberton38363092012-11-19 13:22:34 -0500423static int wp_gpio_probe(struct platform_device *pdev)
Alan Cox72b43792010-10-27 15:33:23 -0700424{
425 struct lnw_gpio *lnw;
426 struct gpio_chip *gc;
427 struct resource *rc;
428 int retval = 0;
429
430 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
431 if (!rc)
432 return -EINVAL;
433
434 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
435 if (!lnw) {
436 dev_err(&pdev->dev,
437 "can't allocate whitneypoint_gpio chip data\n");
438 return -ENOMEM;
439 }
440 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
441 if (lnw->reg_base == NULL) {
442 retval = -EINVAL;
443 goto err_kmalloc;
444 }
445 spin_lock_init(&lnw->lock);
446 gc = &lnw->chip;
447 gc->label = dev_name(&pdev->dev);
448 gc->owner = THIS_MODULE;
449 gc->direction_input = lnw_gpio_direction_input;
450 gc->direction_output = lnw_gpio_direction_output;
451 gc->get = lnw_gpio_get;
452 gc->set = lnw_gpio_set;
453 gc->to_irq = NULL;
454 gc->base = 0;
455 gc->ngpio = 64;
456 gc->can_sleep = 0;
457 retval = gpiochip_add(gc);
458 if (retval) {
459 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
460 retval);
461 goto err_ioremap;
462 }
463 platform_set_drvdata(pdev, lnw);
464 return 0;
465err_ioremap:
466 iounmap(lnw->reg_base);
467err_kmalloc:
468 kfree(lnw);
469 return retval;
470}
471
Bill Pemberton206210c2012-11-19 13:25:50 -0500472static int wp_gpio_remove(struct platform_device *pdev)
Alan Cox72b43792010-10-27 15:33:23 -0700473{
474 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
475 int err;
476 err = gpiochip_remove(&lnw->chip);
477 if (err)
478 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
479 iounmap(lnw->reg_base);
480 kfree(lnw);
481 platform_set_drvdata(pdev, NULL);
482 return 0;
483}
484
485static struct platform_driver wp_gpio_driver = {
486 .probe = wp_gpio_probe,
Bill Pemberton8283c4f2012-11-19 13:20:08 -0500487 .remove = wp_gpio_remove,
Alan Cox72b43792010-10-27 15:33:23 -0700488 .driver = {
489 .name = "wp_gpio",
490 .owner = THIS_MODULE,
491 },
492};
493
Alek Du8bf02612009-09-22 16:46:36 -0700494static int __init lnw_gpio_init(void)
495{
Alan Cox72b43792010-10-27 15:33:23 -0700496 int ret;
497 ret = pci_register_driver(&lnw_gpio_driver);
498 if (ret < 0)
499 return ret;
500 ret = platform_driver_register(&wp_gpio_driver);
501 if (ret < 0)
502 pci_unregister_driver(&lnw_gpio_driver);
503 return ret;
Alek Du8bf02612009-09-22 16:46:36 -0700504}
505
506device_initcall(lnw_gpio_init);