blob: 9d16ef8453c556f7ad69a21f65d9526a90325115 [file] [log] [blame]
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080010#include "at91sam9g45.dtsi"
Alexandre Belloni66844c72014-03-19 00:15:41 +010011#include <dt-bindings/pwm/pwm.h>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020012
13/ {
14 model = "Atmel AT91SAM9M10G45-EK";
15 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
16
17 chosen {
Alexandre Belloniaa070462015-06-03 14:24:10 +020018 bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
19 stdout-path = "serial0:115200n8";
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020020 };
21
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020022 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020023 reg = <0x70000000 0x4000000>;
24 };
25
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080026 clocks {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 main_clock: clock@0 {
32 compatible = "atmel,osc", "fixed-clock";
33 clock-frequency = <12000000>;
34 };
Alexandre Belloni4c67a132014-06-13 20:01:51 +020035
36 slow_xtal {
37 clock-frequency = <32768>;
38 };
39
40 main_xtal {
41 clock-frequency = <12000000>;
42 };
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080043 };
44
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020045 ahb {
46 apb {
47 dbgu: serial@ffffee00 {
48 status = "okay";
49 };
50
51 usart1: serial@fff90000 {
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +080052 pinctrl-0 =
53 <&pinctrl_usart1
54 &pinctrl_usart1_rts
55 &pinctrl_usart1_cts>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020056 status = "okay";
57 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +010058
59 macb0: ethernet@fffbc000 {
60 phy-mode = "rmii";
61 status = "okay";
62 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020063
64 i2c0: i2c@fff84000 {
65 status = "okay";
Josh Wu917cdc52015-06-16 18:08:34 +080066 ov2640: camera@30 {
67 compatible = "ovti,ov2640";
68 reg = <0x30>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
71 resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
72 pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
73 clocks = <&pck1>;
74 clock-names = "xvclk";
75 assigned-clocks = <&pck1>;
76 assigned-clock-rates = <25000000>;
77
78 port {
79 ov2640_0: endpoint {
80 remote-endpoint = <&isi_0>;
81 bus-width = <8>;
82 };
83 };
84 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020085 };
86
87 i2c1: i2c@fff88000 {
88 status = "okay";
89 };
Ludovic Desroches4134a452012-11-19 12:24:02 +010090
Wenyou Yangc77bcef2013-05-31 11:11:33 +080091 watchdog@fffffd40 {
92 status = "okay";
93 };
94
Ludovic Desroches4134a452012-11-19 12:24:02 +010095 mmc0: mmc@fff80000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +080096 pinctrl-0 = <
97 &pinctrl_board_mmc0
98 &pinctrl_mmc0_slot0_clk_cmd_dat0
99 &pinctrl_mmc0_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100100 status = "okay";
101 slot@0 {
102 reg = <0>;
103 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800104 cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100105 };
106 };
107
108 mmc1: mmc@fffd0000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800109 pinctrl-0 = <
110 &pinctrl_board_mmc1
111 &pinctrl_mmc1_slot0_clk_cmd_dat0
112 &pinctrl_mmc1_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100113 status = "okay";
114 slot@0 {
115 reg = <0>;
116 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800117 cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
118 wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100119 };
120 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800121
122 pinctrl@fffff200 {
Josh Wu917cdc52015-06-16 18:08:34 +0800123 camera_sensor {
124 pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
125 atmel,pins =
126 <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
127 };
128
129 pinctrl_sensor_reset: sensor_reset-0 {
130 atmel,pins =
131 <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
132 };
133
134 pinctrl_sensor_power: sensor_power-0 {
135 atmel,pins =
136 <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
137 };
138 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800139 mmc0 {
140 pinctrl_board_mmc0: mmc0-board {
141 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800142 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800143 };
144 };
145
146 mmc1 {
147 pinctrl_board_mmc1: mmc1-board {
148 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800149 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */
150 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800151 };
152 };
Bo Sheneed97292013-12-19 11:59:18 +0800153
154 pwm0 {
155 pinctrl_pwm_leds: pwm-led {
156 atmel,pins =
157 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
158 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
159 };
160 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800161 };
Richard Genoudb6811e92013-04-03 14:03:05 +0800162
163 spi0: spi@fffa4000{
164 status = "okay";
165 cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
166 mtd_dataflash@0 {
167 compatible = "atmel,at45", "atmel,dataflash";
168 spi-max-frequency = <13000000>;
169 reg = <0>;
170 };
171 };
Jean-Christophe PLAGNIOL-VILLARD24ce10e2013-05-03 20:56:01 +0800172
173 usb2: gadget@fff78000 {
174 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
175 status = "okay";
176 };
Bo Sheneed97292013-12-19 11:59:18 +0800177
Alexandre Bellonie10a57e2014-03-19 00:15:40 +0100178 adc0: adc@fffb0000 {
179 pinctrl-names = "default";
180 pinctrl-0 = <
181 &pinctrl_adc0_ad0
182 &pinctrl_adc0_ad1
183 &pinctrl_adc0_ad2
184 &pinctrl_adc0_ad3
185 &pinctrl_adc0_ad4
186 &pinctrl_adc0_ad5
187 &pinctrl_adc0_ad6
188 &pinctrl_adc0_ad7>;
189 atmel,adc-ts-wires = <4>;
190 status = "okay";
191 };
192
Josh Wu917cdc52015-06-16 18:08:34 +0800193 isi@fffb4000 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_isi_data_0_7>;
196 status = "okay";
197 port {
198 isi_0: endpoint {
199 remote-endpoint = <&ov2640_0>;
200 bus-width = <8>;
Josh Wubc81beb2015-09-18 19:28:22 +0800201 vsync-active = <1>;
202 hsync-active = <1>;
Josh Wu917cdc52015-06-16 18:08:34 +0800203 };
204 };
205 };
206
Bo Sheneed97292013-12-19 11:59:18 +0800207 pwm0: pwm@fffb8000 {
208 status = "okay";
209
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_pwm_leds>;
212 };
Erik van Luijk4dd79332014-09-02 12:52:12 +0200213
Boris Brezillon199ec7a2014-11-14 11:08:52 +0100214 rtc@fffffd20 {
215 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
216 status = "okay";
217 };
218
219 gpbr: syscon@fffffd60 {
220 status = "okay";
221 };
222
Erik van Luijk4dd79332014-09-02 12:52:12 +0200223 rtc@fffffdb0 {
224 status = "okay";
225 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200226 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800227
Jean-Christophe PLAGNIOL-VILLARDf4390a72013-03-29 02:11:22 +0800228 fb0: fb@0x00500000 {
229 display = <&display0>;
230 status = "okay";
231
232 display0: display {
233 bits-per-pixel = <32>;
234 atmel,lcdcon-backlight;
235 atmel,dmacon = <0x1>;
236 atmel,lcdcon2 = <0x80008002>;
237 atmel,guard-time = <9>;
238 atmel,lcd-wiring-mode = "RGB";
239
240 display-timings {
241 native-mode = <&timing0>;
242 timing0: timing0 {
243 clock-frequency = <9000000>;
244 hactive = <480>;
245 vactive = <272>;
246 hback-porch = <1>;
247 hfront-porch = <1>;
248 vback-porch = <40>;
249 vfront-porch = <1>;
250 hsync-len = <45>;
251 vsync-len = <1>;
252 };
253 };
254 };
255 };
256
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800257 nand0: nand@40000000 {
258 nand-bus-width = <8>;
259 nand-ecc-mode = "soft";
260 nand-on-flash-bbt;
261 status = "okay";
262
263 boot@0 {
264 label = "bootstrap/uboot/kernel";
265 reg = <0x0 0x400000>;
266 };
267
268 rootfs@400000 {
269 label = "rootfs";
270 reg = <0x400000 0x3C00000>;
271 };
272
273 data@4000000 {
274 label = "data";
275 reg = <0x4000000 0xC000000>;
276 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800277 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800278
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800279 usb0: ohci@00700000 {
280 status = "okay";
281 num-ports = <2>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800282 atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
283 &pioD 3 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800284 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800285
286 usb1: ehci@00800000 {
287 status = "okay";
288 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200289 };
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800290
291 leds {
292 compatible = "gpio-leds";
293
294 d8 {
295 label = "d8";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800296 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800297 linux,default-trigger = "heartbeat";
298 };
Bo Sheneed97292013-12-19 11:59:18 +0800299 };
300
301 pwmleds {
302 compatible = "pwm-leds";
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800303
304 d6 {
305 label = "d6";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100306 pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800307 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800308 linux,default-trigger = "nand-disk";
309 };
310
311 d7 {
312 label = "d7";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100313 pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800314 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800315 linux,default-trigger = "mmc0";
316 };
317 };
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800318
319 gpio_keys {
320 compatible = "gpio-keys";
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800321
322 left_click {
323 label = "left_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800324 gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800325 linux,code = <272>;
326 gpio-key,wakeup;
327 };
328
329 right_click {
330 label = "right_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800331 gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800332 linux,code = <273>;
333 gpio-key,wakeup;
334 };
335
336 left {
337 label = "Joystick Left";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800338 gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800339 linux,code = <105>;
340 };
341
342 right {
343 label = "Joystick Right";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800344 gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800345 linux,code = <106>;
346 };
347
348 up {
349 label = "Joystick Up";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800350 gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800351 linux,code = <103>;
352 };
353
354 down {
355 label = "Joystick Down";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800356 gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800357 linux,code = <108>;
358 };
359
360 enter {
361 label = "Joystick Press";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800362 gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800363 linux,code = <28>;
364 };
365 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200366};