blob: 3ca49e348c9d3ede2dde1134ce2edec4bc924d68 [file] [log] [blame]
Francois Romieu1202d6f2007-09-17 17:13:55 -07001/*
2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3 *
4 * Copyright (C) 2003, 2007 IC Plus Corp
5 *
6 * Original Author:
7 *
8 * Craig Rich
9 * Sundance Technology, Inc.
10 * www.sundanceti.com
11 * craig_rich@sundanceti.com
12 *
13 * Current Maintainer:
14 *
15 * Sorbica Shieh.
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
18 *
19 * Jesse Huang
20 * http://www.icplus.com.tw
21 * jesse@icplus.com.tw
22 */
23#include <linux/crc32.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/mutex.h>
27
trem1dad9392007-10-02 14:04:38 -070028#include <asm/div64.h>
29
Francois Romieu1202d6f2007-09-17 17:13:55 -070030#define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31#define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32#define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35 IPG_AC_AUTO_INIT)
36
Pekka Enberg8da5bb72007-11-30 09:55:43 +020037#define ipg_w32(val32, reg) iowrite32((val32), ioaddr + (reg))
38#define ipg_w16(val16, reg) iowrite16((val16), ioaddr + (reg))
39#define ipg_w8(val8, reg) iowrite8((val8), ioaddr + (reg))
Francois Romieu1202d6f2007-09-17 17:13:55 -070040
41#define ipg_r32(reg) ioread32(ioaddr + (reg))
42#define ipg_r16(reg) ioread16(ioaddr + (reg))
43#define ipg_r8(reg) ioread8(ioaddr + (reg))
44
Francois Romieu1202d6f2007-09-17 17:13:55 -070045enum {
46 netdev_io_size = 128
47};
48
49#include "ipg.h"
50#define DRV_NAME "ipg"
51
52MODULE_AUTHOR("IC Plus Corp. 2003");
Pekka Enberg1662e4b2007-11-30 09:54:06 +020053MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
Francois Romieu1202d6f2007-09-17 17:13:55 -070054MODULE_LICENSE("GPL");
55
Pekka Enberg8da5bb72007-11-30 09:55:43 +020056/*
Pekka Enberg532f4ae2008-06-23 14:36:56 +030057 * Defaults
58 */
59#define IPG_MAX_RXFRAME_SIZE 0x0600
60#define IPG_RXFRAG_SIZE 0x0600
61#define IPG_RXSUPPORT_SIZE 0x0600
62#define IPG_IS_JUMBO false
63
64/*
Pekka Enberg8da5bb72007-11-30 09:55:43 +020065 * Variable record -- index by leading revision/length
66 * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
67 */
Adrian Bunk96fd74b2007-10-24 18:23:19 +020068static unsigned short DefaultPhyParam[] = {
Pekka Enberg8da5bb72007-11-30 09:55:43 +020069 /* 11/12/03 IP1000A v1-3 rev=0x40 */
Adrian Bunk96fd74b2007-10-24 18:23:19 +020070 /*--------------------------------------------------------------------------
71 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
72 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
73 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
74 --------------------------------------------------------------------------*/
Pekka Enberg8da5bb72007-11-30 09:55:43 +020075 /* 12/17/03 IP1000A v1-4 rev=0x40 */
Adrian Bunk96fd74b2007-10-24 18:23:19 +020076 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
77 0x0000,
78 30, 0x005e, 9, 0x0700,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020079 /* 01/09/04 IP1000A v1-5 rev=0x41 */
Adrian Bunk96fd74b2007-10-24 18:23:19 +020080 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
81 0x0000,
82 30, 0x005e, 9, 0x0700,
83 0x0000
84};
85
Francois Romieu1202d6f2007-09-17 17:13:55 -070086static const char *ipg_brand_name[] = {
87 "IC PLUS IP1000 1000/100/10 based NIC",
88 "Sundance Technology ST2021 based NIC",
89 "Tamarack Microelectronics TC9020/9021 based NIC",
90 "Tamarack Microelectronics TC9020/9021 based NIC",
Francois Romieu1202d6f2007-09-17 17:13:55 -070091 "D-Link NIC IP1000A"
92};
93
Alexey Dobriyana3aa1882010-01-07 11:58:11 +000094static DEFINE_PCI_DEVICE_TABLE(ipg_pci_tbl) = {
Francois Romieu1202d6f2007-09-17 17:13:55 -070095 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
96 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
97 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
98 { PCI_VDEVICE(DLINK, 0x9021), 3 },
Jeff Mahoney25cca532010-02-11 10:26:38 +000099 { PCI_VDEVICE(DLINK, 0x4020), 4 },
Francois Romieu1202d6f2007-09-17 17:13:55 -0700100 { 0, }
101};
102
103MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
104
105static inline void __iomem *ipg_ioaddr(struct net_device *dev)
106{
107 struct ipg_nic_private *sp = netdev_priv(dev);
108 return sp->ioaddr;
109}
110
111#ifdef IPG_DEBUG
112static void ipg_dump_rfdlist(struct net_device *dev)
113{
114 struct ipg_nic_private *sp = netdev_priv(dev);
115 void __iomem *ioaddr = sp->ioaddr;
116 unsigned int i;
117 u32 offset;
118
119 IPG_DEBUG_MSG("_dump_rfdlist\n");
120
121 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
122 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
123 printk(KERN_INFO "RFDList start address = %16.16lx\n",
124 (unsigned long) sp->rxd_map);
125 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
126 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
127
128 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
129 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
130 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
131 offset, (unsigned long) sp->rxd[i].next_desc);
132 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
133 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
134 offset, (unsigned long) sp->rxd[i].rfs);
135 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
136 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
137 offset, (unsigned long) sp->rxd[i].frag_info);
138 }
139}
140
141static void ipg_dump_tfdlist(struct net_device *dev)
142{
143 struct ipg_nic_private *sp = netdev_priv(dev);
144 void __iomem *ioaddr = sp->ioaddr;
145 unsigned int i;
146 u32 offset;
147
148 IPG_DEBUG_MSG("_dump_tfdlist\n");
149
150 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
151 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
152 printk(KERN_INFO "TFDList start address = %16.16lx\n",
153 (unsigned long) sp->txd_map);
154 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
155 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
156
157 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
158 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
159 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
160 offset, (unsigned long) sp->txd[i].next_desc);
161
162 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
163 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
164 offset, (unsigned long) sp->txd[i].tfc);
165 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
166 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
167 offset, (unsigned long) sp->txd[i].frag_info);
168 }
169}
170#endif
171
172static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
173{
174 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
175 ndelay(IPG_PC_PHYCTRLWAIT_NS);
176}
177
178static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
179{
180 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
181 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
182}
183
184static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
185{
186 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
187
188 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
189}
190
191static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
192{
193 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
194 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
195}
196
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200197static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700198{
199 u16 bit_data;
200
201 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
202
203 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
204
205 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
206
207 return bit_data;
208}
209
210/*
211 * Read a register from the Physical Layer device located
212 * on the IPG NIC, using the IPG PHYCTRL register.
213 */
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200214static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700215{
216 void __iomem *ioaddr = ipg_ioaddr(dev);
217 /*
218 * The GMII mangement frame structure for a read is as follows:
219 *
220 * |Preamble|st|op|phyad|regad|ta| data |idle|
221 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
222 *
223 * <32 1s> = 32 consecutive logic 1 values
224 * A = bit of Physical Layer device address (MSB first)
225 * R = bit of register address (MSB first)
226 * z = High impedance state
227 * D = bit of read data (MSB first)
228 *
229 * Transmission order is 'Preamble' field first, bits transmitted
230 * left to right (first to last).
231 */
232 struct {
233 u32 field;
234 unsigned int len;
235 } p[] = {
236 { GMII_PREAMBLE, 32 }, /* Preamble */
237 { GMII_ST, 2 }, /* ST */
238 { GMII_READ, 2 }, /* OP */
239 { phy_id, 5 }, /* PHYAD */
240 { phy_reg, 5 }, /* REGAD */
241 { 0x0000, 2 }, /* TA */
242 { 0x0000, 16 }, /* DATA */
243 { 0x0000, 1 } /* IDLE */
244 };
245 unsigned int i, j;
246 u8 polarity, data;
247
248 polarity = ipg_r8(PHY_CTRL);
249 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
250
251 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
252 for (j = 0; j < 5; j++) {
253 for (i = 0; i < p[j].len; i++) {
254 /* For each variable length field, the MSB must be
255 * transmitted first. Rotate through the field bits,
256 * starting with the MSB, and move each bit into the
257 * the 1st (2^1) bit position (this is the bit position
258 * corresponding to the MgmtData bit of the PhyCtrl
259 * register for the IPG).
260 *
261 * Example: ST = 01;
262 *
263 * First write a '0' to bit 1 of the PhyCtrl
264 * register, then write a '1' to bit 1 of the
265 * PhyCtrl register.
266 *
267 * To do this, right shift the MSB of ST by the value:
268 * [field length - 1 - #ST bits already written]
269 * then left shift this result by 1.
270 */
271 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
272 data &= IPG_PC_MGMTDATA;
273 data |= polarity | IPG_PC_MGMTDIR;
274
275 ipg_drive_phy_ctl_low_high(ioaddr, data);
276 }
277 }
278
279 send_three_state(ioaddr, polarity);
280
281 read_phy_bit(ioaddr, polarity);
282
283 /*
284 * For a read cycle, the bits for the next two fields (TA and
285 * DATA) are driven by the PHY (the IPG reads these bits).
286 */
287 for (i = 0; i < p[6].len; i++) {
288 p[6].field |=
289 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
290 }
291
292 send_three_state(ioaddr, polarity);
293 send_three_state(ioaddr, polarity);
294 send_three_state(ioaddr, polarity);
295 send_end(ioaddr, polarity);
296
297 /* Return the value of the DATA field. */
298 return p[6].field;
299}
300
301/*
302 * Write to a register from the Physical Layer device located
303 * on the IPG NIC, using the IPG PHYCTRL register.
304 */
305static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
306{
307 void __iomem *ioaddr = ipg_ioaddr(dev);
308 /*
309 * The GMII mangement frame structure for a read is as follows:
310 *
311 * |Preamble|st|op|phyad|regad|ta| data |idle|
312 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
313 *
314 * <32 1s> = 32 consecutive logic 1 values
315 * A = bit of Physical Layer device address (MSB first)
316 * R = bit of register address (MSB first)
317 * z = High impedance state
318 * D = bit of write data (MSB first)
319 *
320 * Transmission order is 'Preamble' field first, bits transmitted
321 * left to right (first to last).
322 */
323 struct {
324 u32 field;
325 unsigned int len;
326 } p[] = {
327 { GMII_PREAMBLE, 32 }, /* Preamble */
328 { GMII_ST, 2 }, /* ST */
329 { GMII_WRITE, 2 }, /* OP */
330 { phy_id, 5 }, /* PHYAD */
331 { phy_reg, 5 }, /* REGAD */
332 { 0x0002, 2 }, /* TA */
333 { val & 0xffff, 16 }, /* DATA */
334 { 0x0000, 1 } /* IDLE */
335 };
336 unsigned int i, j;
337 u8 polarity, data;
338
339 polarity = ipg_r8(PHY_CTRL);
340 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
341
342 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
343 for (j = 0; j < 7; j++) {
344 for (i = 0; i < p[j].len; i++) {
345 /* For each variable length field, the MSB must be
346 * transmitted first. Rotate through the field bits,
347 * starting with the MSB, and move each bit into the
348 * the 1st (2^1) bit position (this is the bit position
349 * corresponding to the MgmtData bit of the PhyCtrl
350 * register for the IPG).
351 *
352 * Example: ST = 01;
353 *
354 * First write a '0' to bit 1 of the PhyCtrl
355 * register, then write a '1' to bit 1 of the
356 * PhyCtrl register.
357 *
358 * To do this, right shift the MSB of ST by the value:
359 * [field length - 1 - #ST bits already written]
360 * then left shift this result by 1.
361 */
362 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
363 data &= IPG_PC_MGMTDATA;
364 data |= polarity | IPG_PC_MGMTDIR;
365
366 ipg_drive_phy_ctl_low_high(ioaddr, data);
367 }
368 }
369
370 /* The last cycle is a tri-state, so read from the PHY. */
371 for (j = 7; j < 8; j++) {
372 for (i = 0; i < p[j].len; i++) {
373 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
374
375 p[j].field |= ((ipg_r8(PHY_CTRL) &
376 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
377
378 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
379 }
380 }
381}
382
Francois Romieu1202d6f2007-09-17 17:13:55 -0700383static void ipg_set_led_mode(struct net_device *dev)
384{
385 struct ipg_nic_private *sp = netdev_priv(dev);
386 void __iomem *ioaddr = sp->ioaddr;
387 u32 mode;
388
389 mode = ipg_r32(ASIC_CTRL);
390 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
391
Pekka Enberg9893ba12008-01-24 02:01:17 -0800392 if ((sp->led_mode & 0x03) > 1)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700393 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
394
Pekka Enberg9893ba12008-01-24 02:01:17 -0800395 if ((sp->led_mode & 0x01) == 1)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700396 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
397
Pekka Enberg9893ba12008-01-24 02:01:17 -0800398 if ((sp->led_mode & 0x08) == 8)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700399 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
400
401 ipg_w32(mode, ASIC_CTRL);
402}
403
Francois Romieu1202d6f2007-09-17 17:13:55 -0700404static void ipg_set_phy_set(struct net_device *dev)
405{
406 struct ipg_nic_private *sp = netdev_priv(dev);
407 void __iomem *ioaddr = sp->ioaddr;
408 int physet;
409
410 physet = ipg_r8(PHY_SET);
411 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
Pekka Enberg9893ba12008-01-24 02:01:17 -0800412 physet |= ((sp->led_mode & 0x70) >> 4);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700413 ipg_w8(physet, PHY_SET);
414}
415
416static int ipg_reset(struct net_device *dev, u32 resetflags)
417{
418 /* Assert functional resets via the IPG AsicCtrl
419 * register as specified by the 'resetflags' input
420 * parameter.
421 */
Pekka Enbergdea4a872007-11-30 09:54:51 +0200422 void __iomem *ioaddr = ipg_ioaddr(dev);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700423 unsigned int timeout_count = 0;
424
425 IPG_DEBUG_MSG("_reset\n");
426
427 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
428
429 /* Delay added to account for problem with 10Mbps reset. */
430 mdelay(IPG_AC_RESETWAIT);
431
432 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
433 mdelay(IPG_AC_RESETWAIT);
434 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
435 return -ETIME;
436 }
Pekka Enbergdea4a872007-11-30 09:54:51 +0200437 /* Set LED Mode in Asic Control */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700438 ipg_set_led_mode(dev);
439
Pekka Enbergdea4a872007-11-30 09:54:51 +0200440 /* Set PHYSet Register Value */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700441 ipg_set_phy_set(dev);
442 return 0;
443}
444
445/* Find the GMII PHY address. */
446static int ipg_find_phyaddr(struct net_device *dev)
447{
448 unsigned int phyaddr, i;
449
450 for (i = 0; i < 32; i++) {
451 u32 status;
452
453 /* Search for the correct PHY address among 32 possible. */
454 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
455
456 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
457 GMII_PHY_ID1
458 */
459
460 status = mdio_read(dev, phyaddr, MII_BMSR);
461
462 if ((status != 0xFFFF) && (status != 0))
463 return phyaddr;
464 }
465
466 return 0x1f;
467}
468
469/*
470 * Configure IPG based on result of IEEE 802.3 PHY
471 * auto-negotiation.
472 */
473static int ipg_config_autoneg(struct net_device *dev)
474{
475 struct ipg_nic_private *sp = netdev_priv(dev);
476 void __iomem *ioaddr = sp->ioaddr;
477 unsigned int txflowcontrol;
478 unsigned int rxflowcontrol;
479 unsigned int fullduplex;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700480 u32 mac_ctrl_val;
481 u32 asicctrl;
482 u8 phyctrl;
483
484 IPG_DEBUG_MSG("_config_autoneg\n");
485
486 asicctrl = ipg_r32(ASIC_CTRL);
487 phyctrl = ipg_r8(PHY_CTRL);
488 mac_ctrl_val = ipg_r32(MAC_CTRL);
489
490 /* Set flags for use in resolving auto-negotation, assuming
491 * non-1000Mbps, half duplex, no flow control.
492 */
493 fullduplex = 0;
494 txflowcontrol = 0;
495 rxflowcontrol = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700496
497 /* To accomodate a problem in 10Mbps operation,
498 * set a global flag if PHY running in 10Mbps mode.
499 */
500 sp->tenmbpsmode = 0;
501
502 printk(KERN_INFO "%s: Link speed = ", dev->name);
503
504 /* Determine actual speed of operation. */
505 switch (phyctrl & IPG_PC_LINK_SPEED) {
506 case IPG_PC_LINK_SPEED_10MBPS:
507 printk("10Mbps.\n");
508 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
509 dev->name);
510 sp->tenmbpsmode = 1;
511 break;
512 case IPG_PC_LINK_SPEED_100MBPS:
513 printk("100Mbps.\n");
514 break;
515 case IPG_PC_LINK_SPEED_1000MBPS:
516 printk("1000Mbps.\n");
Francois Romieu1202d6f2007-09-17 17:13:55 -0700517 break;
518 default:
519 printk("undefined!\n");
520 return 0;
521 }
522
523 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
524 fullduplex = 1;
525 txflowcontrol = 1;
526 rxflowcontrol = 1;
527 }
528
529 /* Configure full duplex, and flow control. */
530 if (fullduplex == 1) {
531 /* Configure IPG for full duplex operation. */
532 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
533
534 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
535
536 if (txflowcontrol == 1) {
537 printk("TX flow control");
538 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
539 } else {
540 printk("no TX flow control");
541 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
542 }
543
544 if (rxflowcontrol == 1) {
545 printk(", RX flow control.");
546 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
547 } else {
548 printk(", no RX flow control.");
549 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
550 }
551
552 printk("\n");
553 } else {
554 /* Configure IPG for half duplex operation. */
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200555 printk(KERN_INFO "%s: setting half duplex, "
Francois Romieu1202d6f2007-09-17 17:13:55 -0700556 "no TX flow control, no RX flow control.\n", dev->name);
557
558 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
559 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
560 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
561 }
562 ipg_w32(mac_ctrl_val, MAC_CTRL);
563 return 0;
564}
565
566/* Determine and configure multicast operation and set
567 * receive mode for IPG.
568 */
569static void ipg_nic_set_multicast_list(struct net_device *dev)
570{
571 void __iomem *ioaddr = ipg_ioaddr(dev);
572 struct dev_mc_list *mc_list_ptr;
573 unsigned int hashindex;
574 u32 hashtable[2];
575 u8 receivemode;
576
577 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
578
579 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
580
581 if (dev->flags & IFF_PROMISC) {
582 /* NIC to be configured in promiscuous mode. */
583 receivemode = IPG_RM_RECEIVEALLFRAMES;
584 } else if ((dev->flags & IFF_ALLMULTI) ||
Roel Kluin07612482008-06-09 16:33:50 -0700585 ((dev->flags & IFF_MULTICAST) &&
Jiri Pirko4cd24ea2010-02-08 04:30:35 +0000586 (netdev_mc_count(dev) > IPG_MULTICAST_HASHTABLE_SIZE))) {
Francois Romieu1202d6f2007-09-17 17:13:55 -0700587 /* NIC to be configured to receive all multicast
588 * frames. */
589 receivemode |= IPG_RM_RECEIVEMULTICAST;
Jiri Pirko4cd24ea2010-02-08 04:30:35 +0000590 } else if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
Francois Romieu1202d6f2007-09-17 17:13:55 -0700591 /* NIC to be configured to receive selected
592 * multicast addresses. */
593 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
594 }
595
596 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
597 * The IPG applies a cyclic-redundancy-check (the same CRC
598 * used to calculate the frame data FCS) to the destination
599 * address all incoming multicast frames whose destination
600 * address has the multicast bit set. The least significant
601 * 6 bits of the CRC result are used as an addressing index
602 * into the hash table. If the value of the bit addressed by
603 * this index is a 1, the frame is passed to the host system.
604 */
605
606 /* Clear hashtable. */
607 hashtable[0] = 0x00000000;
608 hashtable[1] = 0x00000000;
609
610 /* Cycle through all multicast addresses to filter. */
611 for (mc_list_ptr = dev->mc_list;
612 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
613 /* Calculate CRC result for each multicast address. */
614 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
615 ETH_ALEN);
616
617 /* Use only the least significant 6 bits. */
618 hashindex = hashindex & 0x3F;
619
620 /* Within "hashtable", set bit number "hashindex"
621 * to a logic 1.
622 */
623 set_bit(hashindex, (void *)hashtable);
624 }
625
626 /* Write the value of the hashtable, to the 4, 16 bit
627 * HASHTABLE IPG registers.
628 */
629 ipg_w32(hashtable[0], HASHTABLE_0);
630 ipg_w32(hashtable[1], HASHTABLE_1);
631
632 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
633
634 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
635}
636
637static int ipg_io_config(struct net_device *dev)
638{
Pekka Enbergda02b232008-06-23 14:36:35 +0300639 struct ipg_nic_private *sp = netdev_priv(dev);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700640 void __iomem *ioaddr = ipg_ioaddr(dev);
641 u32 origmacctrl;
642 u32 restoremacctrl;
643
644 IPG_DEBUG_MSG("_io_config\n");
645
646 origmacctrl = ipg_r32(MAC_CTRL);
647
648 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
649
650 /* Based on compilation option, determine if FCS is to be
651 * stripped on receive frames by IPG.
652 */
653 if (!IPG_STRIP_FCS_ON_RX)
654 restoremacctrl |= IPG_MC_RCV_FCS;
655
656 /* Determine if transmitter and/or receiver are
657 * enabled so we may restore MACCTRL correctly.
658 */
659 if (origmacctrl & IPG_MC_TX_ENABLED)
660 restoremacctrl |= IPG_MC_TX_ENABLE;
661
662 if (origmacctrl & IPG_MC_RX_ENABLED)
663 restoremacctrl |= IPG_MC_RX_ENABLE;
664
665 /* Transmitter and receiver must be disabled before setting
666 * IFSSelect.
667 */
668 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
669 IPG_MC_RSVD_MASK, MAC_CTRL);
670
671 /* Now that transmitter and receiver are disabled, write
672 * to IFSSelect.
673 */
674 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
675
676 /* Set RECEIVEMODE register. */
677 ipg_nic_set_multicast_list(dev);
678
Pekka Enbergda02b232008-06-23 14:36:35 +0300679 ipg_w16(sp->max_rxframe_size, MAX_FRAME_SIZE);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700680
681 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
682 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
683 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
684 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
685 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
686 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
687 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
688 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
689 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
690 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
691 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
692 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
693
694 /* IPG multi-frag frame bug workaround.
695 * Per silicon revision B3 eratta.
696 */
697 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
698
699 /* IPG TX poll now bug workaround.
700 * Per silicon revision B3 eratta.
701 */
702 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
703
704 /* IPG RX poll now bug workaround.
705 * Per silicon revision B3 eratta.
706 */
707 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
708
709 /* Now restore MACCTRL to original setting. */
710 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
711
712 /* Disable unused RMON statistics. */
713 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
714
715 /* Disable unused MIB statistics. */
716 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
717 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
718 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
719 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
720 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
721 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
722
723 return 0;
724}
725
726/*
727 * Create a receive buffer within system memory and update
728 * NIC private structure appropriately.
729 */
730static int ipg_get_rxbuff(struct net_device *dev, int entry)
731{
732 struct ipg_nic_private *sp = netdev_priv(dev);
733 struct ipg_rx *rxfd = sp->rxd + entry;
734 struct sk_buff *skb;
735 u64 rxfragsize;
736
737 IPG_DEBUG_MSG("_get_rxbuff\n");
738
Eric Dumazet89d71a62009-10-13 05:34:20 +0000739 skb = netdev_alloc_skb_ip_align(dev, sp->rxsupport_size);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700740 if (!skb) {
Pekka Enberg9893ba12008-01-24 02:01:17 -0800741 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700742 return -ENOMEM;
743 }
744
Francois Romieu1202d6f2007-09-17 17:13:55 -0700745 /* Associate the receive buffer with the IPG NIC. */
746 skb->dev = dev;
747
748 /* Save the address of the sk_buff structure. */
Pekka Enberg9893ba12008-01-24 02:01:17 -0800749 sp->rx_buff[entry] = skb;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700750
751 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
752 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
753
754 /* Set the RFD fragment length. */
Pekka Enberg18a9cdb2008-06-23 14:36:00 +0300755 rxfragsize = sp->rxfrag_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700756 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
757
758 return 0;
759}
760
761static int init_rfdlist(struct net_device *dev)
762{
763 struct ipg_nic_private *sp = netdev_priv(dev);
764 void __iomem *ioaddr = sp->ioaddr;
765 unsigned int i;
766
767 IPG_DEBUG_MSG("_init_rfdlist\n");
768
769 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
770 struct ipg_rx *rxfd = sp->rxd + i;
771
Pekka Enberg9893ba12008-01-24 02:01:17 -0800772 if (sp->rx_buff[i]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -0700773 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +0100774 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -0700775 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
Pekka Enberg9893ba12008-01-24 02:01:17 -0800776 dev_kfree_skb_irq(sp->rx_buff[i]);
777 sp->rx_buff[i] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700778 }
779
780 /* Clear out the RFS field. */
781 rxfd->rfs = 0x0000000000000000;
782
783 if (ipg_get_rxbuff(dev, i) < 0) {
784 /*
785 * A receive buffer was not ready, break the
786 * RFD list here.
787 */
788 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
789
790 /* Just in case we cannot allocate a single RFD.
791 * Should not occur.
792 */
793 if (i == 0) {
794 printk(KERN_ERR "%s: No memory available"
795 " for RFD list.\n", dev->name);
796 return -ENOMEM;
797 }
798 }
799
800 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
801 sizeof(struct ipg_rx)*(i + 1));
802 }
803 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
804
805 sp->rx_current = 0;
806 sp->rx_dirty = 0;
807
808 /* Write the location of the RFDList to the IPG. */
809 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
810 ipg_w32(0x00000000, RFD_LIST_PTR_1);
811
812 return 0;
813}
814
815static void init_tfdlist(struct net_device *dev)
816{
817 struct ipg_nic_private *sp = netdev_priv(dev);
818 void __iomem *ioaddr = sp->ioaddr;
819 unsigned int i;
820
821 IPG_DEBUG_MSG("_init_tfdlist\n");
822
823 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
824 struct ipg_tx *txfd = sp->txd + i;
825
826 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
827
Pekka Enberg9893ba12008-01-24 02:01:17 -0800828 if (sp->tx_buff[i]) {
829 dev_kfree_skb_irq(sp->tx_buff[i]);
830 sp->tx_buff[i] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700831 }
832
833 txfd->next_desc = cpu_to_le64(sp->txd_map +
834 sizeof(struct ipg_tx)*(i + 1));
835 }
836 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
837
838 sp->tx_current = 0;
839 sp->tx_dirty = 0;
840
841 /* Write the location of the TFDList to the IPG. */
842 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
843 (u32) sp->txd_map);
844 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
845 ipg_w32(0x00000000, TFD_LIST_PTR_1);
846
Pekka Enberg9893ba12008-01-24 02:01:17 -0800847 sp->reset_current_tfd = 1;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700848}
849
850/*
851 * Free all transmit buffers which have already been transfered
852 * via DMA to the IPG.
853 */
854static void ipg_nic_txfree(struct net_device *dev)
855{
856 struct ipg_nic_private *sp = netdev_priv(dev);
Francois Romieu0da1b992008-01-10 23:40:59 +0100857 unsigned int released, pending, dirty;
trem1dad9392007-10-02 14:04:38 -0700858
Francois Romieu1202d6f2007-09-17 17:13:55 -0700859 IPG_DEBUG_MSG("_nic_txfree\n");
860
861 pending = sp->tx_current - sp->tx_dirty;
Francois Romieu0da1b992008-01-10 23:40:59 +0100862 dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700863
864 for (released = 0; released < pending; released++) {
Pekka Enberg9893ba12008-01-24 02:01:17 -0800865 struct sk_buff *skb = sp->tx_buff[dirty];
Francois Romieu1202d6f2007-09-17 17:13:55 -0700866 struct ipg_tx *txfd = sp->txd + dirty;
867
868 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
869
870 /* Look at each TFD's TFC field beginning
871 * at the last freed TFD up to the current TFD.
872 * If the TFDDone bit is set, free the associated
873 * buffer.
874 */
Francois Romieu0da1b992008-01-10 23:40:59 +0100875 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
876 break;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700877
878 /* Free the transmit buffer. */
879 if (skb) {
880 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +0100881 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -0700882 skb->len, PCI_DMA_TODEVICE);
883
Pekka Enberg85d68a52007-11-30 09:53:51 +0200884 dev_kfree_skb_irq(skb);
Francois Romieu1202d6f2007-09-17 17:13:55 -0700885
Pekka Enberg9893ba12008-01-24 02:01:17 -0800886 sp->tx_buff[dirty] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700887 }
Francois Romieu0da1b992008-01-10 23:40:59 +0100888 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700889 }
890
891 sp->tx_dirty += released;
892
893 if (netif_queue_stopped(dev) &&
894 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
895 netif_wake_queue(dev);
896 }
897}
898
899static void ipg_tx_timeout(struct net_device *dev)
900{
901 struct ipg_nic_private *sp = netdev_priv(dev);
902 void __iomem *ioaddr = sp->ioaddr;
903
904 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
905 IPG_AC_FIFO);
906
907 spin_lock_irq(&sp->lock);
908
909 /* Re-configure after DMA reset. */
910 if (ipg_io_config(dev) < 0) {
911 printk(KERN_INFO "%s: Error during re-configuration.\n",
912 dev->name);
913 }
914
915 init_tfdlist(dev);
916
917 spin_unlock_irq(&sp->lock);
918
919 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
920 MAC_CTRL);
921}
922
923/*
924 * For TxComplete interrupts, free all transmit
925 * buffers which have already been transfered via DMA
926 * to the IPG.
927 */
928static void ipg_nic_txcleanup(struct net_device *dev)
929{
930 struct ipg_nic_private *sp = netdev_priv(dev);
931 void __iomem *ioaddr = sp->ioaddr;
932 unsigned int i;
933
934 IPG_DEBUG_MSG("_nic_txcleanup\n");
935
936 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
937 /* Reading the TXSTATUS register clears the
938 * TX_COMPLETE interrupt.
939 */
940 u32 txstatusdword = ipg_r32(TX_STATUS);
941
942 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
943
944 /* Check for Transmit errors. Error bits only valid if
945 * TX_COMPLETE bit in the TXSTATUS register is a 1.
946 */
947 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
948 break;
949
950 /* If in 10Mbps mode, indicate transmit is ready. */
951 if (sp->tenmbpsmode) {
952 netif_wake_queue(dev);
953 }
954
955 /* Transmit error, increment stat counters. */
956 if (txstatusdword & IPG_TS_TX_ERROR) {
957 IPG_DEBUG_MSG("Transmit error.\n");
958 sp->stats.tx_errors++;
959 }
960
961 /* Late collision, re-enable transmitter. */
962 if (txstatusdword & IPG_TS_LATE_COLLISION) {
963 IPG_DEBUG_MSG("Late collision on transmit.\n");
964 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
965 IPG_MC_RSVD_MASK, MAC_CTRL);
966 }
967
968 /* Maximum collisions, re-enable transmitter. */
969 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
970 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
971 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
972 IPG_MC_RSVD_MASK, MAC_CTRL);
973 }
974
975 /* Transmit underrun, reset and re-enable
976 * transmitter.
977 */
978 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
979 IPG_DEBUG_MSG("Transmitter underrun.\n");
980 sp->stats.tx_fifo_errors++;
981 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
982 IPG_AC_NETWORK | IPG_AC_FIFO);
983
984 /* Re-configure after DMA reset. */
985 if (ipg_io_config(dev) < 0) {
986 printk(KERN_INFO
987 "%s: Error during re-configuration.\n",
988 dev->name);
989 }
990 init_tfdlist(dev);
991
992 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
993 IPG_MC_RSVD_MASK, MAC_CTRL);
994 }
995 }
996
997 ipg_nic_txfree(dev);
998}
999
1000/* Provides statistical information about the IPG NIC. */
Adrian Bunk96fd74b2007-10-24 18:23:19 +02001001static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001002{
1003 struct ipg_nic_private *sp = netdev_priv(dev);
1004 void __iomem *ioaddr = sp->ioaddr;
1005 u16 temp1;
1006 u16 temp2;
1007
1008 IPG_DEBUG_MSG("_nic_get_stats\n");
1009
1010 /* Check to see if the NIC has been initialized via nic_open,
1011 * before trying to read statistic registers.
1012 */
1013 if (!test_bit(__LINK_STATE_START, &dev->state))
1014 return &sp->stats;
1015
1016 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1017 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1018 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1019 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1020 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1021 sp->stats.rx_errors += temp1;
1022 sp->stats.rx_missed_errors += temp1;
1023 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1024 ipg_r32(IPG_LATECOLLISIONS);
1025 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1026 sp->stats.collisions += temp1;
1027 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1028 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1029 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1030 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1031
1032 /* detailed tx_errors */
1033 sp->stats.tx_carrier_errors += temp2;
1034
1035 /* detailed rx_errors */
1036 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1037 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1038 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1039
1040 /* Unutilized IPG statistic registers. */
1041 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1042
1043 return &sp->stats;
1044}
1045
1046/* Restore used receive buffers. */
1047static int ipg_nic_rxrestore(struct net_device *dev)
1048{
1049 struct ipg_nic_private *sp = netdev_priv(dev);
1050 const unsigned int curr = sp->rx_current;
1051 unsigned int dirty = sp->rx_dirty;
1052
1053 IPG_DEBUG_MSG("_nic_rxrestore\n");
1054
1055 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1056 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1057
1058 /* rx_copybreak may poke hole here and there. */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001059 if (sp->rx_buff[entry])
Francois Romieu1202d6f2007-09-17 17:13:55 -07001060 continue;
1061
1062 /* Generate a new receive buffer to replace the
1063 * current buffer (which will be released by the
1064 * Linux system).
1065 */
1066 if (ipg_get_rxbuff(dev, entry) < 0) {
1067 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1068
1069 break;
1070 }
1071
1072 /* Reset the RFS field. */
1073 sp->rxd[entry].rfs = 0x0000000000000000;
1074 }
1075 sp->rx_dirty = dirty;
1076
1077 return 0;
1078}
1079
Francois Romieu1202d6f2007-09-17 17:13:55 -07001080/* use jumboindex and jumbosize to control jumbo frame status
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001081 * initial status is jumboindex=-1 and jumbosize=0
1082 * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1083 * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1084 * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1085 * previous receiving and need to continue dumping the current one
1086 */
Francois Romieu1202d6f2007-09-17 17:13:55 -07001087enum {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001088 NORMAL_PACKET,
1089 ERROR_PACKET
Francois Romieu1202d6f2007-09-17 17:13:55 -07001090};
1091
1092enum {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001093 FRAME_NO_START_NO_END = 0,
1094 FRAME_WITH_START = 1,
1095 FRAME_WITH_END = 10,
1096 FRAME_WITH_START_WITH_END = 11
Francois Romieu1202d6f2007-09-17 17:13:55 -07001097};
1098
Pekka Enberg024f4d882008-06-23 14:35:16 +03001099static void ipg_nic_rx_free_skb(struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001100{
1101 struct ipg_nic_private *sp = netdev_priv(dev);
1102 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1103
Pekka Enberg9893ba12008-01-24 02:01:17 -08001104 if (sp->rx_buff[entry]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001105 struct ipg_rx *rxfd = sp->rxd + entry;
1106
1107 pci_unmap_single(sp->pdev,
Harvey Harrisonb88ed5c2008-11-19 15:54:38 -08001108 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001109 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001110 dev_kfree_skb_irq(sp->rx_buff[entry]);
1111 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001112 }
1113}
1114
Pekka Enberg024f4d882008-06-23 14:35:16 +03001115static int ipg_nic_rx_check_frame_type(struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001116{
1117 struct ipg_nic_private *sp = netdev_priv(dev);
1118 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001119 int type = FRAME_NO_START_NO_END;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001120
1121 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
Pekka Enberg9893ba12008-01-24 02:01:17 -08001122 type += FRAME_WITH_START;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001123 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
Pekka Enberg9893ba12008-01-24 02:01:17 -08001124 type += FRAME_WITH_END;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001125 return type;
1126}
1127
Pekka Enberg024f4d882008-06-23 14:35:16 +03001128static int ipg_nic_rx_check_error(struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001129{
1130 struct ipg_nic_private *sp = netdev_priv(dev);
1131 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1132 struct ipg_rx *rxfd = sp->rxd + entry;
1133
1134 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1135 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1136 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1137 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1138 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1139 (unsigned long) rxfd->rfs);
1140
1141 /* Increment general receive error statistic. */
1142 sp->stats.rx_errors++;
1143
1144 /* Increment detailed receive error statistics. */
1145 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1146 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1147
1148 sp->stats.rx_fifo_errors++;
1149 }
1150
1151 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1152 IPG_DEBUG_MSG("RX runt occured.\n");
1153 sp->stats.rx_length_errors++;
1154 }
1155
1156 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1157 * error count handled by a IPG statistic register.
1158 */
1159
1160 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1161 IPG_DEBUG_MSG("RX alignment error occured.\n");
1162 sp->stats.rx_frame_errors++;
1163 }
1164
1165 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1166 * handled by a IPG statistic register.
1167 */
1168
1169 /* Free the memory associated with the RX
1170 * buffer since it is erroneous and we will
1171 * not pass it to higher layer processes.
1172 */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001173 if (sp->rx_buff[entry]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001174 pci_unmap_single(sp->pdev,
Harvey Harrisonb88ed5c2008-11-19 15:54:38 -08001175 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001176 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1177
Pekka Enberg9893ba12008-01-24 02:01:17 -08001178 dev_kfree_skb_irq(sp->rx_buff[entry]);
1179 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001180 }
Pekka Enberg9893ba12008-01-24 02:01:17 -08001181 return ERROR_PACKET;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001182 }
Pekka Enberg9893ba12008-01-24 02:01:17 -08001183 return NORMAL_PACKET;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001184}
1185
1186static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1187 struct ipg_nic_private *sp,
1188 struct ipg_rx *rxfd, unsigned entry)
1189{
Pekka Enberg9893ba12008-01-24 02:01:17 -08001190 struct ipg_jumbo *jumbo = &sp->jumbo;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001191 struct sk_buff *skb;
1192 int framelen;
1193
Pekka Enberg9893ba12008-01-24 02:01:17 -08001194 if (jumbo->found_start) {
Pekka Enberg85d68a52007-11-30 09:53:51 +02001195 dev_kfree_skb_irq(jumbo->skb);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001196 jumbo->found_start = 0;
1197 jumbo->current_size = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001198 jumbo->skb = NULL;
1199 }
1200
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001201 /* 1: found error, 0 no error */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001202 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001203 return;
1204
Pekka Enberg9893ba12008-01-24 02:01:17 -08001205 skb = sp->rx_buff[entry];
Francois Romieu1202d6f2007-09-17 17:13:55 -07001206 if (!skb)
1207 return;
1208
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001209 /* accept this frame and send to upper layer */
Francois Romieu1202d6f2007-09-17 17:13:55 -07001210 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001211 if (framelen > sp->rxfrag_size)
1212 framelen = sp->rxfrag_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001213
1214 skb_put(skb, framelen);
1215 skb->protocol = eth_type_trans(skb, dev);
1216 skb->ip_summed = CHECKSUM_NONE;
1217 netif_rx(skb);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001218 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001219}
1220
1221static void ipg_nic_rx_with_start(struct net_device *dev,
1222 struct ipg_nic_private *sp,
1223 struct ipg_rx *rxfd, unsigned entry)
1224{
Pekka Enberg9893ba12008-01-24 02:01:17 -08001225 struct ipg_jumbo *jumbo = &sp->jumbo;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001226 struct pci_dev *pdev = sp->pdev;
1227 struct sk_buff *skb;
1228
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001229 /* 1: found error, 0 no error */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001230 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001231 return;
1232
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001233 /* accept this frame and send to upper layer */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001234 skb = sp->rx_buff[entry];
Francois Romieu1202d6f2007-09-17 17:13:55 -07001235 if (!skb)
1236 return;
1237
Pekka Enberg9893ba12008-01-24 02:01:17 -08001238 if (jumbo->found_start)
Pekka Enberg85d68a52007-11-30 09:53:51 +02001239 dev_kfree_skb_irq(jumbo->skb);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001240
Harvey Harrisonb88ed5c2008-11-19 15:54:38 -08001241 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001242 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1243
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001244 skb_put(skb, sp->rxfrag_size);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001245
Pekka Enberg9893ba12008-01-24 02:01:17 -08001246 jumbo->found_start = 1;
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001247 jumbo->current_size = sp->rxfrag_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001248 jumbo->skb = skb;
1249
Pekka Enberg9893ba12008-01-24 02:01:17 -08001250 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001251}
1252
1253static void ipg_nic_rx_with_end(struct net_device *dev,
1254 struct ipg_nic_private *sp,
1255 struct ipg_rx *rxfd, unsigned entry)
1256{
Pekka Enberg9893ba12008-01-24 02:01:17 -08001257 struct ipg_jumbo *jumbo = &sp->jumbo;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001258
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001259 /* 1: found error, 0 no error */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001260 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1261 struct sk_buff *skb = sp->rx_buff[entry];
Francois Romieu1202d6f2007-09-17 17:13:55 -07001262
1263 if (!skb)
1264 return;
1265
Pekka Enberg9893ba12008-01-24 02:01:17 -08001266 if (jumbo->found_start) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001267 int framelen, endframelen;
1268
1269 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1270
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001271 endframelen = framelen - jumbo->current_size;
Pekka Enberg39f20582008-06-23 14:36:18 +03001272 if (framelen > sp->rxsupport_size)
Pekka Enberg85d68a52007-11-30 09:53:51 +02001273 dev_kfree_skb_irq(jumbo->skb);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001274 else {
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001275 memcpy(skb_put(jumbo->skb, endframelen),
1276 skb->data, endframelen);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001277
1278 jumbo->skb->protocol =
1279 eth_type_trans(jumbo->skb, dev);
1280
1281 jumbo->skb->ip_summed = CHECKSUM_NONE;
1282 netif_rx(jumbo->skb);
1283 }
1284 }
1285
Pekka Enberg9893ba12008-01-24 02:01:17 -08001286 jumbo->found_start = 0;
1287 jumbo->current_size = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001288 jumbo->skb = NULL;
1289
1290 ipg_nic_rx_free_skb(dev);
1291 } else {
Pekka Enberg85d68a52007-11-30 09:53:51 +02001292 dev_kfree_skb_irq(jumbo->skb);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001293 jumbo->found_start = 0;
1294 jumbo->current_size = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001295 jumbo->skb = NULL;
1296 }
1297}
1298
1299static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1300 struct ipg_nic_private *sp,
1301 struct ipg_rx *rxfd, unsigned entry)
1302{
Pekka Enberg9893ba12008-01-24 02:01:17 -08001303 struct ipg_jumbo *jumbo = &sp->jumbo;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001304
Pekka Enberg8da5bb72007-11-30 09:55:43 +02001305 /* 1: found error, 0 no error */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001306 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1307 struct sk_buff *skb = sp->rx_buff[entry];
Francois Romieu1202d6f2007-09-17 17:13:55 -07001308
1309 if (skb) {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001310 if (jumbo->found_start) {
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001311 jumbo->current_size += sp->rxfrag_size;
Pekka Enberg39f20582008-06-23 14:36:18 +03001312 if (jumbo->current_size <= sp->rxsupport_size) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001313 memcpy(skb_put(jumbo->skb,
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001314 sp->rxfrag_size),
1315 skb->data, sp->rxfrag_size);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001316 }
1317 }
Francois Romieu1202d6f2007-09-17 17:13:55 -07001318 ipg_nic_rx_free_skb(dev);
1319 }
1320 } else {
Pekka Enberg85d68a52007-11-30 09:53:51 +02001321 dev_kfree_skb_irq(jumbo->skb);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001322 jumbo->found_start = 0;
1323 jumbo->current_size = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001324 jumbo->skb = NULL;
1325 }
1326}
1327
Pekka Enberg024f4d882008-06-23 14:35:16 +03001328static int ipg_nic_rx_jumbo(struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001329{
1330 struct ipg_nic_private *sp = netdev_priv(dev);
1331 unsigned int curr = sp->rx_current;
1332 void __iomem *ioaddr = sp->ioaddr;
1333 unsigned int i;
1334
1335 IPG_DEBUG_MSG("_nic_rx\n");
1336
1337 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1338 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1339 struct ipg_rx *rxfd = sp->rxd + entry;
1340
Harvey Harrisonb88ed5c2008-11-19 15:54:38 -08001341 if (!(rxfd->rfs & cpu_to_le64(IPG_RFS_RFDDONE)))
Francois Romieu1202d6f2007-09-17 17:13:55 -07001342 break;
1343
1344 switch (ipg_nic_rx_check_frame_type(dev)) {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001345 case FRAME_WITH_START_WITH_END:
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001346 ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001347 break;
Pekka Enberg9893ba12008-01-24 02:01:17 -08001348 case FRAME_WITH_START:
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001349 ipg_nic_rx_with_start(dev, sp, rxfd, entry);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001350 break;
Pekka Enberg9893ba12008-01-24 02:01:17 -08001351 case FRAME_WITH_END:
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001352 ipg_nic_rx_with_end(dev, sp, rxfd, entry);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001353 break;
Pekka Enberg9893ba12008-01-24 02:01:17 -08001354 case FRAME_NO_START_NO_END:
Pekka Enbergecfecfb2008-06-23 14:34:29 +03001355 ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001356 break;
1357 }
1358 }
1359
1360 sp->rx_current = curr;
1361
1362 if (i == IPG_MAXRFDPROCESS_COUNT) {
1363 /* There are more RFDs to process, however the
1364 * allocated amount of RFD processing time has
1365 * expired. Assert Interrupt Requested to make
1366 * sure we come back to process the remaining RFDs.
1367 */
1368 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1369 }
1370
1371 ipg_nic_rxrestore(dev);
1372
1373 return 0;
1374}
1375
Francois Romieu1202d6f2007-09-17 17:13:55 -07001376static int ipg_nic_rx(struct net_device *dev)
1377{
1378 /* Transfer received Ethernet frames to higher network layers. */
1379 struct ipg_nic_private *sp = netdev_priv(dev);
1380 unsigned int curr = sp->rx_current;
1381 void __iomem *ioaddr = sp->ioaddr;
1382 struct ipg_rx *rxfd;
1383 unsigned int i;
1384
1385 IPG_DEBUG_MSG("_nic_rx\n");
1386
1387#define __RFS_MASK \
1388 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1389
1390 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1391 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
Pekka Enberg9893ba12008-01-24 02:01:17 -08001392 struct sk_buff *skb = sp->rx_buff[entry];
Francois Romieu1202d6f2007-09-17 17:13:55 -07001393 unsigned int framelen;
1394
1395 rxfd = sp->rxd + entry;
1396
1397 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1398 break;
1399
1400 /* Get received frame length. */
1401 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1402
1403 /* Check for jumbo frame arrival with too small
1404 * RXFRAG_SIZE.
1405 */
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001406 if (framelen > sp->rxfrag_size) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001407 IPG_DEBUG_MSG
1408 ("RFS FrameLen > allocated fragment size.\n");
1409
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03001410 framelen = sp->rxfrag_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001411 }
1412
Al Viro325a8072007-10-14 19:41:29 +01001413 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
Francois Romieu1202d6f2007-09-17 17:13:55 -07001414 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1415 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
Al Viro325a8072007-10-14 19:41:29 +01001416 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001417
1418 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1419 (unsigned long int) rxfd->rfs);
1420
1421 /* Increment general receive error statistic. */
1422 sp->stats.rx_errors++;
1423
1424 /* Increment detailed receive error statistics. */
Al Viro325a8072007-10-14 19:41:29 +01001425 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001426 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1427 sp->stats.rx_fifo_errors++;
1428 }
1429
Al Viro325a8072007-10-14 19:41:29 +01001430 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001431 IPG_DEBUG_MSG("RX runt occured.\n");
1432 sp->stats.rx_length_errors++;
1433 }
1434
Al Viro325a8072007-10-14 19:41:29 +01001435 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001436 /* Do nothing, error count handled by a IPG
1437 * statistic register.
1438 */
1439
Al Viro325a8072007-10-14 19:41:29 +01001440 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001441 IPG_DEBUG_MSG("RX alignment error occured.\n");
1442 sp->stats.rx_frame_errors++;
1443 }
1444
Al Viro325a8072007-10-14 19:41:29 +01001445 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001446 /* Do nothing, error count handled by a IPG
1447 * statistic register.
1448 */
1449
1450 /* Free the memory associated with the RX
1451 * buffer since it is erroneous and we will
1452 * not pass it to higher layer processes.
1453 */
1454 if (skb) {
Al Viro325a8072007-10-14 19:41:29 +01001455 __le64 info = rxfd->frag_info;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001456
1457 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +01001458 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001459 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1460
Pekka Enberg85d68a52007-11-30 09:53:51 +02001461 dev_kfree_skb_irq(skb);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001462 }
1463 } else {
1464
1465 /* Adjust the new buffer length to accomodate the size
1466 * of the received frame.
1467 */
1468 skb_put(skb, framelen);
1469
1470 /* Set the buffer's protocol field to Ethernet. */
1471 skb->protocol = eth_type_trans(skb, dev);
1472
Pekka Enberg6d3b2cb2007-11-30 09:54:33 +02001473 /* The IPG encountered an error with (or
1474 * there were no) IP/TCP/UDP checksums.
1475 * This may or may not indicate an invalid
1476 * IP/TCP/UDP frame was received. Let the
1477 * upper layer decide.
Francois Romieu1202d6f2007-09-17 17:13:55 -07001478 */
Pekka Enberg6d3b2cb2007-11-30 09:54:33 +02001479 skb->ip_summed = CHECKSUM_NONE;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001480
1481 /* Hand off frame for higher layer processing.
1482 * The function netif_rx() releases the sk_buff
1483 * when processing completes.
1484 */
1485 netif_rx(skb);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001486 }
1487
1488 /* Assure RX buffer is not reused by IPG. */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001489 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001490 }
1491
1492 /*
1493 * If there are more RFDs to proces and the allocated amount of RFD
1494 * processing time has expired, assert Interrupt Requested to make
1495 * sure we come back to process the remaining RFDs.
1496 */
1497 if (i == IPG_MAXRFDPROCESS_COUNT)
1498 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1499
1500#ifdef IPG_DEBUG
1501 /* Check if the RFD list contained no receive frame data. */
1502 if (!i)
1503 sp->EmptyRFDListCount++;
1504#endif
Al Viro325a8072007-10-14 19:41:29 +01001505 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1506 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1507 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001508 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1509
1510 rxfd = sp->rxd + entry;
1511
1512 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1513
1514 /* An unexpected event, additional code needed to handle
1515 * properly. So for the time being, just disregard the
1516 * frame.
1517 */
1518
1519 /* Free the memory associated with the RX
1520 * buffer since it is erroneous and we will
1521 * not pass it to higher layer processes.
1522 */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001523 if (sp->rx_buff[entry]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001524 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +01001525 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001526 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
Pekka Enberg9893ba12008-01-24 02:01:17 -08001527 dev_kfree_skb_irq(sp->rx_buff[entry]);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001528 }
1529
1530 /* Assure RX buffer is not reused by IPG. */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001531 sp->rx_buff[entry] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001532 }
1533
1534 sp->rx_current = curr;
1535
1536 /* Check to see if there are a minimum number of used
1537 * RFDs before restoring any (should improve performance.)
1538 */
1539 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1540 ipg_nic_rxrestore(dev);
1541
1542 return 0;
1543}
Francois Romieu1202d6f2007-09-17 17:13:55 -07001544
1545static void ipg_reset_after_host_error(struct work_struct *work)
1546{
1547 struct ipg_nic_private *sp =
1548 container_of(work, struct ipg_nic_private, task.work);
1549 struct net_device *dev = sp->dev;
1550
1551 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1552
1553 /*
1554 * Acknowledge HostError interrupt by resetting
1555 * IPG DMA and HOST.
1556 */
1557 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1558
1559 init_rfdlist(dev);
1560 init_tfdlist(dev);
1561
1562 if (ipg_io_config(dev) < 0) {
1563 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1564 dev->name);
1565 schedule_delayed_work(&sp->task, HZ);
1566 }
1567}
1568
1569static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1570{
1571 struct net_device *dev = dev_inst;
1572 struct ipg_nic_private *sp = netdev_priv(dev);
1573 void __iomem *ioaddr = sp->ioaddr;
1574 unsigned int handled = 0;
1575 u16 status;
1576
1577 IPG_DEBUG_MSG("_interrupt_handler\n");
1578
Pekka Enberg024f4d882008-06-23 14:35:16 +03001579 if (sp->is_jumbo)
1580 ipg_nic_rxrestore(dev);
1581
Francois Romieu227bc242008-01-10 23:25:30 +01001582 spin_lock(&sp->lock);
1583
Francois Romieu1202d6f2007-09-17 17:13:55 -07001584 /* Get interrupt source information, and acknowledge
1585 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1586 * IntRequested, MacControlFrame, LinkEvent) interrupts
1587 * if issued. Also, all IPG interrupts are disabled by
1588 * reading IntStatusAck.
1589 */
1590 status = ipg_r16(INT_STATUS_ACK);
1591
1592 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1593
1594 /* Shared IRQ of remove event. */
1595 if (!(status & IPG_IS_RSVD_MASK))
1596 goto out_enable;
1597
1598 handled = 1;
1599
1600 if (unlikely(!netif_running(dev)))
Francois Romieu227bc242008-01-10 23:25:30 +01001601 goto out_unlock;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001602
1603 /* If RFDListEnd interrupt, restore all used RFDs. */
1604 if (status & IPG_IS_RFD_LIST_END) {
1605 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1606
1607 /* The RFD list end indicates an RFD was encountered
1608 * with a 0 NextPtr, or with an RFDDone bit set to 1
1609 * (indicating the RFD is not read for use by the
1610 * IPG.) Try to restore all RFDs.
1611 */
1612 ipg_nic_rxrestore(dev);
1613
1614#ifdef IPG_DEBUG
1615 /* Increment the RFDlistendCount counter. */
1616 sp->RFDlistendCount++;
1617#endif
1618 }
1619
1620 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1621 * IntRequested interrupt, process received frames. */
1622 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1623 (status & IPG_IS_RFD_LIST_END) ||
1624 (status & IPG_IS_RX_DMA_COMPLETE) ||
1625 (status & IPG_IS_INT_REQUESTED)) {
1626#ifdef IPG_DEBUG
1627 /* Increment the RFD list checked counter if interrupted
1628 * only to check the RFD list. */
1629 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1630 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1631 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1632 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1633 IPG_IS_UPDATE_STATS)))
1634 sp->RFDListCheckedCount++;
1635#endif
1636
Pekka Enberg024f4d882008-06-23 14:35:16 +03001637 if (sp->is_jumbo)
1638 ipg_nic_rx_jumbo(dev);
1639 else
1640 ipg_nic_rx(dev);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001641 }
1642
1643 /* If TxDMAComplete interrupt, free used TFDs. */
1644 if (status & IPG_IS_TX_DMA_COMPLETE)
1645 ipg_nic_txfree(dev);
1646
1647 /* TxComplete interrupts indicate one of numerous actions.
1648 * Determine what action to take based on TXSTATUS register.
1649 */
1650 if (status & IPG_IS_TX_COMPLETE)
1651 ipg_nic_txcleanup(dev);
1652
1653 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1654 if (status & IPG_IS_UPDATE_STATS)
1655 ipg_nic_get_stats(dev);
1656
1657 /* If HostError interrupt, reset IPG. */
1658 if (status & IPG_IS_HOST_ERROR) {
1659 IPG_DDEBUG_MSG("HostError Interrupt\n");
1660
1661 schedule_delayed_work(&sp->task, 0);
1662 }
1663
1664 /* If LinkEvent interrupt, resolve autonegotiation. */
1665 if (status & IPG_IS_LINK_EVENT) {
1666 if (ipg_config_autoneg(dev) < 0)
1667 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1668 dev->name);
1669 }
1670
1671 /* If MACCtrlFrame interrupt, do nothing. */
1672 if (status & IPG_IS_MAC_CTRL_FRAME)
1673 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1674
1675 /* If RxComplete interrupt, do nothing. */
1676 if (status & IPG_IS_RX_COMPLETE)
1677 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1678
1679 /* If RxEarly interrupt, do nothing. */
1680 if (status & IPG_IS_RX_EARLY)
1681 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1682
1683out_enable:
1684 /* Re-enable IPG interrupts. */
1685 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1686 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1687 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
Francois Romieu227bc242008-01-10 23:25:30 +01001688out_unlock:
Francois Romieu1202d6f2007-09-17 17:13:55 -07001689 spin_unlock(&sp->lock);
Francois Romieu227bc242008-01-10 23:25:30 +01001690
Francois Romieu1202d6f2007-09-17 17:13:55 -07001691 return IRQ_RETVAL(handled);
1692}
1693
1694static void ipg_rx_clear(struct ipg_nic_private *sp)
1695{
1696 unsigned int i;
1697
1698 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001699 if (sp->rx_buff[i]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001700 struct ipg_rx *rxfd = sp->rxd + i;
1701
Pekka Enberg9893ba12008-01-24 02:01:17 -08001702 dev_kfree_skb_irq(sp->rx_buff[i]);
1703 sp->rx_buff[i] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001704 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +01001705 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001706 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1707 }
1708 }
1709}
1710
1711static void ipg_tx_clear(struct ipg_nic_private *sp)
1712{
1713 unsigned int i;
1714
1715 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
Pekka Enberg9893ba12008-01-24 02:01:17 -08001716 if (sp->tx_buff[i]) {
Francois Romieu1202d6f2007-09-17 17:13:55 -07001717 struct ipg_tx *txfd = sp->txd + i;
1718
1719 pci_unmap_single(sp->pdev,
Al Viro325a8072007-10-14 19:41:29 +01001720 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
Pekka Enberg9893ba12008-01-24 02:01:17 -08001721 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001722
Pekka Enberg9893ba12008-01-24 02:01:17 -08001723 dev_kfree_skb_irq(sp->tx_buff[i]);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001724
Pekka Enberg9893ba12008-01-24 02:01:17 -08001725 sp->tx_buff[i] = NULL;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001726 }
1727 }
1728}
1729
1730static int ipg_nic_open(struct net_device *dev)
1731{
1732 struct ipg_nic_private *sp = netdev_priv(dev);
1733 void __iomem *ioaddr = sp->ioaddr;
1734 struct pci_dev *pdev = sp->pdev;
1735 int rc;
1736
1737 IPG_DEBUG_MSG("_nic_open\n");
1738
Pekka Enberg39f20582008-06-23 14:36:18 +03001739 sp->rx_buf_sz = sp->rxsupport_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001740
1741 /* Check for interrupt line conflicts, and request interrupt
1742 * line for IPG.
1743 *
1744 * IMPORTANT: Disable IPG interrupts prior to registering
1745 * IRQ.
1746 */
1747 ipg_w16(0x0000, INT_ENABLE);
1748
1749 /* Register the interrupt line to be used by the IPG within
1750 * the Linux system.
1751 */
Julia Lawall90145c92009-11-18 08:21:45 +00001752 rc = request_irq(pdev->irq, ipg_interrupt_handler, IRQF_SHARED,
Francois Romieu1202d6f2007-09-17 17:13:55 -07001753 dev->name, dev);
1754 if (rc < 0) {
1755 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1756 dev->name);
1757 goto out;
1758 }
1759
1760 dev->irq = pdev->irq;
1761
1762 rc = -ENOMEM;
1763
1764 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1765 &sp->rxd_map, GFP_KERNEL);
1766 if (!sp->rxd)
1767 goto err_free_irq_0;
1768
1769 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1770 &sp->txd_map, GFP_KERNEL);
1771 if (!sp->txd)
1772 goto err_free_rx_1;
1773
1774 rc = init_rfdlist(dev);
1775 if (rc < 0) {
1776 printk(KERN_INFO "%s: Error during configuration.\n",
1777 dev->name);
1778 goto err_free_tx_2;
1779 }
1780
1781 init_tfdlist(dev);
1782
1783 rc = ipg_io_config(dev);
1784 if (rc < 0) {
1785 printk(KERN_INFO "%s: Error during configuration.\n",
1786 dev->name);
1787 goto err_release_tfdlist_3;
1788 }
1789
1790 /* Resolve autonegotiation. */
1791 if (ipg_config_autoneg(dev) < 0)
1792 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1793
Francois Romieu1202d6f2007-09-17 17:13:55 -07001794 /* initialize JUMBO Frame control variable */
Pekka Enberg9893ba12008-01-24 02:01:17 -08001795 sp->jumbo.found_start = 0;
1796 sp->jumbo.current_size = 0;
Pekka Enberge8399fe2008-06-23 14:34:50 +03001797 sp->jumbo.skb = NULL;
Pekka Enberg83042952008-06-23 14:35:37 +03001798
Francois Romieu1202d6f2007-09-17 17:13:55 -07001799 /* Enable transmit and receive operation of the IPG. */
1800 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1801 IPG_MC_RSVD_MASK, MAC_CTRL);
1802
1803 netif_start_queue(dev);
1804out:
1805 return rc;
1806
1807err_release_tfdlist_3:
1808 ipg_tx_clear(sp);
1809 ipg_rx_clear(sp);
1810err_free_tx_2:
1811 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1812err_free_rx_1:
1813 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1814err_free_irq_0:
1815 free_irq(pdev->irq, dev);
1816 goto out;
1817}
1818
1819static int ipg_nic_stop(struct net_device *dev)
1820{
1821 struct ipg_nic_private *sp = netdev_priv(dev);
1822 void __iomem *ioaddr = sp->ioaddr;
1823 struct pci_dev *pdev = sp->pdev;
1824
1825 IPG_DEBUG_MSG("_nic_stop\n");
1826
1827 netif_stop_queue(dev);
1828
1829 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1830 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1831 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1832 IPG_DUMPTFDLIST(dev);
1833
1834 do {
1835 (void) ipg_r16(INT_STATUS_ACK);
1836
1837 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1838
1839 synchronize_irq(pdev->irq);
1840 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1841
1842 ipg_rx_clear(sp);
1843
1844 ipg_tx_clear(sp);
1845
1846 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1847 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1848
1849 free_irq(pdev->irq, dev);
1850
1851 return 0;
1852}
1853
Stephen Hemminger613573252009-08-31 19:50:58 +00001854static netdev_tx_t ipg_nic_hard_start_xmit(struct sk_buff *skb,
1855 struct net_device *dev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07001856{
1857 struct ipg_nic_private *sp = netdev_priv(dev);
1858 void __iomem *ioaddr = sp->ioaddr;
1859 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1860 unsigned long flags;
1861 struct ipg_tx *txfd;
1862
1863 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1864
1865 /* If in 10Mbps mode, stop the transmit queue so
1866 * no more transmit frames are accepted.
1867 */
1868 if (sp->tenmbpsmode)
1869 netif_stop_queue(dev);
1870
Pekka Enberg9893ba12008-01-24 02:01:17 -08001871 if (sp->reset_current_tfd) {
1872 sp->reset_current_tfd = 0;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001873 entry = 0;
1874 }
1875
1876 txfd = sp->txd + entry;
1877
Pekka Enberg9893ba12008-01-24 02:01:17 -08001878 sp->tx_buff[entry] = skb;
Francois Romieu1202d6f2007-09-17 17:13:55 -07001879
1880 /* Clear all TFC fields, except TFDDONE. */
1881 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1882
1883 /* Specify the TFC field within the TFD. */
1884 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
Al Viro48f5fec2008-03-16 22:22:14 +00001885 (IPG_TFC_FRAMEID & sp->tx_current) |
Francois Romieu1202d6f2007-09-17 17:13:55 -07001886 (IPG_TFC_FRAGCOUNT & (1 << 24)));
Al Viro48f5fec2008-03-16 22:22:14 +00001887 /*
1888 * 16--17 (WordAlign) <- 3 (disable),
1889 * 0--15 (FrameId) <- sp->tx_current,
1890 * 24--27 (FragCount) <- 1
1891 */
Francois Romieu1202d6f2007-09-17 17:13:55 -07001892
1893 /* Request TxComplete interrupts at an interval defined
1894 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1895 * Request TxComplete interrupt for every frame
1896 * if in 10Mbps mode to accomodate problem with 10Mbps
1897 * processing.
1898 */
1899 if (sp->tenmbpsmode)
1900 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
Francois Romieu47cccd72008-01-10 23:53:15 +01001901 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001902 /* Based on compilation option, determine if FCS is to be
1903 * appended to transmit frame by IPG.
1904 */
1905 if (!(IPG_APPEND_FCS_ON_TX))
1906 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1907
1908 /* Based on compilation option, determine if IP, TCP and/or
1909 * UDP checksums are to be added to transmit frame by IPG.
1910 */
1911 if (IPG_ADD_IPCHECKSUM_ON_TX)
1912 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1913
1914 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1915 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1916
1917 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1918 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1919
1920 /* Based on compilation option, determine if VLAN tag info is to be
1921 * inserted into transmit frame by IPG.
1922 */
1923 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1924 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1925 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1926 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1927 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1928 }
1929
1930 /* The fragment start location within system memory is defined
1931 * by the sk_buff structure's data field. The physical address
1932 * of this location within the system's virtual memory space
1933 * is determined using the IPG_HOST2BUS_MAP function.
1934 */
1935 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1936 skb->len, PCI_DMA_TODEVICE));
1937
1938 /* The length of the fragment within system memory is defined by
1939 * the sk_buff structure's len field.
1940 */
1941 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1942 ((u64) (skb->len & 0xffff) << 48));
1943
1944 /* Clear the TFDDone bit last to indicate the TFD is ready
1945 * for transfer to the IPG.
1946 */
1947 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1948
1949 spin_lock_irqsave(&sp->lock, flags);
1950
1951 sp->tx_current++;
1952
1953 mmiowb();
1954
1955 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1956
1957 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
Francois Romieudafdec72008-01-10 23:45:05 +01001958 netif_stop_queue(dev);
Francois Romieu1202d6f2007-09-17 17:13:55 -07001959
1960 spin_unlock_irqrestore(&sp->lock, flags);
1961
1962 return NETDEV_TX_OK;
1963}
1964
1965static void ipg_set_phy_default_param(unsigned char rev,
1966 struct net_device *dev, int phy_address)
1967{
1968 unsigned short length;
1969 unsigned char revision;
1970 unsigned short *phy_param;
1971 unsigned short address, value;
1972
1973 phy_param = &DefaultPhyParam[0];
1974 length = *phy_param & 0x00FF;
1975 revision = (unsigned char)((*phy_param) >> 8);
1976 phy_param++;
1977 while (length != 0) {
1978 if (rev == revision) {
1979 while (length > 1) {
1980 address = *phy_param;
1981 value = *(phy_param + 1);
1982 phy_param += 2;
1983 mdio_write(dev, phy_address, address, value);
1984 length -= 4;
1985 }
1986 break;
1987 } else {
1988 phy_param += length / 2;
1989 length = *phy_param & 0x00FF;
1990 revision = (unsigned char)((*phy_param) >> 8);
1991 phy_param++;
1992 }
1993 }
1994}
1995
Francois Romieu1202d6f2007-09-17 17:13:55 -07001996static int read_eeprom(struct net_device *dev, int eep_addr)
1997{
1998 void __iomem *ioaddr = ipg_ioaddr(dev);
1999 unsigned int i;
2000 int ret = 0;
2001 u16 value;
2002
2003 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2004 ipg_w16(value, EEPROM_CTRL);
2005
2006 for (i = 0; i < 1000; i++) {
2007 u16 data;
2008
2009 mdelay(10);
2010 data = ipg_r16(EEPROM_CTRL);
2011 if (!(data & IPG_EC_EEPROM_BUSY)) {
2012 ret = ipg_r16(EEPROM_DATA);
2013 break;
2014 }
2015 }
2016 return ret;
2017}
2018
2019static void ipg_init_mii(struct net_device *dev)
2020{
2021 struct ipg_nic_private *sp = netdev_priv(dev);
2022 struct mii_if_info *mii_if = &sp->mii_if;
2023 int phyaddr;
2024
2025 mii_if->dev = dev;
2026 mii_if->mdio_read = mdio_read;
2027 mii_if->mdio_write = mdio_write;
2028 mii_if->phy_id_mask = 0x1f;
2029 mii_if->reg_num_mask = 0x1f;
2030
2031 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2032
2033 if (phyaddr != 0x1f) {
2034 u16 mii_phyctrl, mii_1000cr;
2035 u8 revisionid = 0;
2036
2037 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2038 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2039 GMII_PHY_1000BASETCONTROL_PreferMaster;
2040 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2041
2042 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2043
2044 /* Set default phyparam */
2045 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2046 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2047
2048 /* Reset PHY */
2049 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2050 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2051
2052 }
2053}
2054
2055static int ipg_hw_init(struct net_device *dev)
2056{
2057 struct ipg_nic_private *sp = netdev_priv(dev);
2058 void __iomem *ioaddr = sp->ioaddr;
2059 unsigned int i;
2060 int rc;
2061
Pekka Enbergdea4a872007-11-30 09:54:51 +02002062 /* Read/Write and Reset EEPROM Value */
Francois Romieu1202d6f2007-09-17 17:13:55 -07002063 /* Read LED Mode Configuration from EEPROM */
Pekka Enberg9893ba12008-01-24 02:01:17 -08002064 sp->led_mode = read_eeprom(dev, 6);
Francois Romieu1202d6f2007-09-17 17:13:55 -07002065
2066 /* Reset all functions within the IPG. Do not assert
2067 * RST_OUT as not compatible with some PHYs.
2068 */
2069 rc = ipg_reset(dev, IPG_RESET_MASK);
2070 if (rc < 0)
2071 goto out;
2072
2073 ipg_init_mii(dev);
2074
2075 /* Read MAC Address from EEPROM */
2076 for (i = 0; i < 3; i++)
2077 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2078
2079 for (i = 0; i < 3; i++)
2080 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2081
2082 /* Set station address in ethernet_device structure. */
2083 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2084 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2085 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2086 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2087 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2088 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2089out:
2090 return rc;
2091}
2092
2093static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2094{
2095 struct ipg_nic_private *sp = netdev_priv(dev);
2096 int rc;
2097
2098 mutex_lock(&sp->mii_mutex);
2099 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2100 mutex_unlock(&sp->mii_mutex);
2101
2102 return rc;
2103}
2104
2105static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2106{
Pekka Enbergda02b232008-06-23 14:36:35 +03002107 struct ipg_nic_private *sp = netdev_priv(dev);
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002108 int err;
Pekka Enbergda02b232008-06-23 14:36:35 +03002109
Francois Romieu1202d6f2007-09-17 17:13:55 -07002110 /* Function to accomodate changes to Maximum Transfer Unit
2111 * (or MTU) of IPG NIC. Cannot use default function since
2112 * the default will not allow for MTU > 1500 bytes.
2113 */
2114
2115 IPG_DEBUG_MSG("_nic_change_mtu\n");
2116
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002117 /*
2118 * Check that the new MTU value is between 68 (14 byte header, 46 byte
2119 * payload, 4 byte FCS) and 10 KB, which is the largest supported MTU.
Francois Romieu1202d6f2007-09-17 17:13:55 -07002120 */
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002121 if (new_mtu < 68 || new_mtu > 10240)
Francois Romieu1202d6f2007-09-17 17:13:55 -07002122 return -EINVAL;
2123
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002124 err = ipg_nic_stop(dev);
2125 if (err)
2126 return err;
2127
Francois Romieu1202d6f2007-09-17 17:13:55 -07002128 dev->mtu = new_mtu;
2129
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002130 sp->max_rxframe_size = new_mtu;
2131
2132 sp->rxfrag_size = new_mtu;
2133 if (sp->rxfrag_size > 4088)
2134 sp->rxfrag_size = 4088;
2135
2136 sp->rxsupport_size = sp->max_rxframe_size;
2137
2138 if (new_mtu > 0x0600)
2139 sp->is_jumbo = true;
2140 else
2141 sp->is_jumbo = false;
2142
2143 return ipg_nic_open(dev);
Francois Romieu1202d6f2007-09-17 17:13:55 -07002144}
2145
2146static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2147{
2148 struct ipg_nic_private *sp = netdev_priv(dev);
2149 int rc;
2150
2151 mutex_lock(&sp->mii_mutex);
2152 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2153 mutex_unlock(&sp->mii_mutex);
2154
2155 return rc;
2156}
2157
2158static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2159{
2160 struct ipg_nic_private *sp = netdev_priv(dev);
2161 int rc;
2162
2163 mutex_lock(&sp->mii_mutex);
2164 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2165 mutex_unlock(&sp->mii_mutex);
2166
2167 return rc;
2168}
2169
2170static int ipg_nway_reset(struct net_device *dev)
2171{
2172 struct ipg_nic_private *sp = netdev_priv(dev);
2173 int rc;
2174
2175 mutex_lock(&sp->mii_mutex);
2176 rc = mii_nway_restart(&sp->mii_if);
2177 mutex_unlock(&sp->mii_mutex);
2178
2179 return rc;
2180}
2181
Stephen Hemminger0fc0b732009-09-02 01:03:33 -07002182static const struct ethtool_ops ipg_ethtool_ops = {
Francois Romieu1202d6f2007-09-17 17:13:55 -07002183 .get_settings = ipg_get_settings,
2184 .set_settings = ipg_set_settings,
2185 .nway_reset = ipg_nway_reset,
2186};
2187
Adrian Bunkef312242007-12-11 23:20:30 +01002188static void __devexit ipg_remove(struct pci_dev *pdev)
Francois Romieu1202d6f2007-09-17 17:13:55 -07002189{
2190 struct net_device *dev = pci_get_drvdata(pdev);
2191 struct ipg_nic_private *sp = netdev_priv(dev);
2192
2193 IPG_DEBUG_MSG("_remove\n");
2194
2195 /* Un-register Ethernet device. */
2196 unregister_netdev(dev);
2197
2198 pci_iounmap(pdev, sp->ioaddr);
2199
2200 pci_release_regions(pdev);
2201
2202 free_netdev(dev);
2203 pci_disable_device(pdev);
2204 pci_set_drvdata(pdev, NULL);
2205}
2206
Stephen Hemminger04fb5f72009-01-07 17:26:14 -08002207static const struct net_device_ops ipg_netdev_ops = {
2208 .ndo_open = ipg_nic_open,
2209 .ndo_stop = ipg_nic_stop,
2210 .ndo_start_xmit = ipg_nic_hard_start_xmit,
2211 .ndo_get_stats = ipg_nic_get_stats,
2212 .ndo_set_multicast_list = ipg_nic_set_multicast_list,
2213 .ndo_do_ioctl = ipg_ioctl,
2214 .ndo_tx_timeout = ipg_tx_timeout,
2215 .ndo_change_mtu = ipg_nic_change_mtu,
2216 .ndo_set_mac_address = eth_mac_addr,
2217 .ndo_validate_addr = eth_validate_addr,
2218};
2219
Francois Romieu1202d6f2007-09-17 17:13:55 -07002220static int __devinit ipg_probe(struct pci_dev *pdev,
2221 const struct pci_device_id *id)
2222{
2223 unsigned int i = id->driver_data;
2224 struct ipg_nic_private *sp;
2225 struct net_device *dev;
2226 void __iomem *ioaddr;
2227 int rc;
2228
2229 rc = pci_enable_device(pdev);
2230 if (rc < 0)
2231 goto out;
2232
2233 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2234
2235 pci_set_master(pdev);
2236
Yang Hongyang50cf1562009-04-06 19:01:14 -07002237 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
Francois Romieu1202d6f2007-09-17 17:13:55 -07002238 if (rc < 0) {
Yang Hongyang284901a2009-04-06 19:01:15 -07002239 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Francois Romieu1202d6f2007-09-17 17:13:55 -07002240 if (rc < 0) {
2241 printk(KERN_ERR "%s: DMA config failed.\n",
2242 pci_name(pdev));
2243 goto err_disable_0;
2244 }
2245 }
2246
2247 /*
2248 * Initialize net device.
2249 */
2250 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2251 if (!dev) {
2252 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2253 rc = -ENOMEM;
2254 goto err_disable_0;
2255 }
2256
2257 sp = netdev_priv(dev);
2258 spin_lock_init(&sp->lock);
2259 mutex_init(&sp->mii_mutex);
2260
Pekka Enberg532f4ae2008-06-23 14:36:56 +03002261 sp->is_jumbo = IPG_IS_JUMBO;
Pekka Enberg18a9cdb2008-06-23 14:36:00 +03002262 sp->rxfrag_size = IPG_RXFRAG_SIZE;
Pekka Enberg39f20582008-06-23 14:36:18 +03002263 sp->rxsupport_size = IPG_RXSUPPORT_SIZE;
Pekka Enbergda02b232008-06-23 14:36:35 +03002264 sp->max_rxframe_size = IPG_MAX_RXFRAME_SIZE;
Pekka Enberg024f4d882008-06-23 14:35:16 +03002265
Francois Romieu1202d6f2007-09-17 17:13:55 -07002266 /* Declare IPG NIC functions for Ethernet device methods.
2267 */
Stephen Hemminger04fb5f72009-01-07 17:26:14 -08002268 dev->netdev_ops = &ipg_netdev_ops;
Francois Romieu1202d6f2007-09-17 17:13:55 -07002269 SET_NETDEV_DEV(dev, &pdev->dev);
2270 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2271
2272 rc = pci_request_regions(pdev, DRV_NAME);
2273 if (rc)
2274 goto err_free_dev_1;
2275
2276 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2277 if (!ioaddr) {
2278 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2279 rc = -EIO;
2280 goto err_release_regions_2;
2281 }
2282
2283 /* Save the pointer to the PCI device information. */
2284 sp->ioaddr = ioaddr;
2285 sp->pdev = pdev;
2286 sp->dev = dev;
2287
2288 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2289
2290 pci_set_drvdata(pdev, dev);
2291
2292 rc = ipg_hw_init(dev);
2293 if (rc < 0)
2294 goto err_unmap_3;
2295
2296 rc = register_netdev(dev);
2297 if (rc < 0)
2298 goto err_unmap_3;
2299
2300 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2301out:
2302 return rc;
2303
2304err_unmap_3:
2305 pci_iounmap(pdev, ioaddr);
2306err_release_regions_2:
2307 pci_release_regions(pdev);
2308err_free_dev_1:
2309 free_netdev(dev);
2310err_disable_0:
2311 pci_disable_device(pdev);
2312 goto out;
2313}
2314
2315static struct pci_driver ipg_pci_driver = {
2316 .name = IPG_DRIVER_NAME,
2317 .id_table = ipg_pci_tbl,
2318 .probe = ipg_probe,
2319 .remove = __devexit_p(ipg_remove),
2320};
2321
2322static int __init ipg_init_module(void)
2323{
2324 return pci_register_driver(&ipg_pci_driver);
2325}
2326
2327static void __exit ipg_exit_module(void)
2328{
2329 pci_unregister_driver(&ipg_pci_driver);
2330}
2331
2332module_init(ipg_init_module);
2333module_exit(ipg_exit_module);