Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * PCI Express PCI Hot Plug Driver |
| 3 | * |
| 4 | * Copyright (C) 1995,2001 Compaq Computer Corporation |
| 5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) |
| 6 | * Copyright (C) 2001 IBM Corp. |
| 7 | * Copyright (C) 2003-2004 Intel Corporation |
| 8 | * |
| 9 | * All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or (at |
| 14 | * your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 19 | * NON INFRINGEMENT. See the GNU General Public License for more |
| 20 | * details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
Kristen Accardi | 8cf4c19 | 2005-08-16 15:16:10 -0700 | [diff] [blame] | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | * |
| 28 | */ |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/types.h> |
Tim Schmielau | de25968 | 2006-01-08 01:02:05 -0800 | [diff] [blame] | 33 | #include <linux/signal.h> |
| 34 | #include <linux/jiffies.h> |
| 35 | #include <linux/timer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <linux/pci.h> |
Andrew Morton | 5d1b8c9 | 2005-11-13 16:06:39 -0800 | [diff] [blame] | 37 | #include <linux/interrupt.h> |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #include "../pci.h" |
| 40 | #include "pciehp.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #ifdef DEBUG |
| 42 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ |
| 43 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ |
| 44 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ |
| 45 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ |
| 46 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) |
| 47 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) |
| 48 | /* Redefine this flagword to set debug level */ |
| 49 | #define DEBUG_LEVEL DBG_K_STANDARD |
| 50 | |
| 51 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; |
| 52 | |
| 53 | #define DBG_PRINT( dbg_flags, args... ) \ |
| 54 | do { \ |
| 55 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ |
| 56 | { \ |
| 57 | int len; \ |
| 58 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ |
| 59 | __FILE__, __LINE__, __FUNCTION__ ); \ |
| 60 | sprintf( __dbg_str_buf + len, args ); \ |
| 61 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ |
| 62 | } \ |
| 63 | } while (0) |
| 64 | |
| 65 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); |
| 66 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); |
| 67 | #else |
| 68 | #define DEFINE_DBG_BUFFER |
| 69 | #define DBG_ENTER_ROUTINE |
| 70 | #define DBG_LEAVE_ROUTINE |
| 71 | #endif /* DEBUG */ |
| 72 | |
| 73 | struct ctrl_reg { |
| 74 | u8 cap_id; |
| 75 | u8 nxt_ptr; |
| 76 | u16 cap_reg; |
| 77 | u32 dev_cap; |
| 78 | u16 dev_ctrl; |
| 79 | u16 dev_status; |
| 80 | u32 lnk_cap; |
| 81 | u16 lnk_ctrl; |
| 82 | u16 lnk_status; |
| 83 | u32 slot_cap; |
| 84 | u16 slot_ctrl; |
| 85 | u16 slot_status; |
| 86 | u16 root_ctrl; |
| 87 | u16 rsvp; |
| 88 | u32 root_status; |
| 89 | } __attribute__ ((packed)); |
| 90 | |
| 91 | /* offsets to the controller registers based on the above structure layout */ |
| 92 | enum ctrl_offsets { |
| 93 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), |
| 94 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), |
| 95 | CAPREG = offsetof(struct ctrl_reg, cap_reg), |
| 96 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), |
| 97 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), |
| 98 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), |
| 99 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), |
| 100 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), |
| 101 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), |
| 102 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), |
| 103 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), |
| 104 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), |
| 105 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), |
| 106 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), |
| 107 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 109 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
| 110 | { |
| 111 | struct pci_dev *dev = ctrl->pci_dev; |
| 112 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); |
| 113 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 115 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) |
| 116 | { |
| 117 | struct pci_dev *dev = ctrl->pci_dev; |
| 118 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); |
| 119 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 121 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) |
| 122 | { |
| 123 | struct pci_dev *dev = ctrl->pci_dev; |
| 124 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); |
| 125 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 127 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) |
| 128 | { |
| 129 | struct pci_dev *dev = ctrl->pci_dev; |
| 130 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); |
| 131 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | /* Field definitions in PCI Express Capabilities Register */ |
| 134 | #define CAP_VER 0x000F |
| 135 | #define DEV_PORT_TYPE 0x00F0 |
| 136 | #define SLOT_IMPL 0x0100 |
| 137 | #define MSG_NUM 0x3E00 |
| 138 | |
| 139 | /* Device or Port Type */ |
| 140 | #define NAT_ENDPT 0x00 |
| 141 | #define LEG_ENDPT 0x01 |
| 142 | #define ROOT_PORT 0x04 |
| 143 | #define UP_STREAM 0x05 |
| 144 | #define DN_STREAM 0x06 |
| 145 | #define PCIE_PCI_BRDG 0x07 |
| 146 | #define PCI_PCIE_BRDG 0x10 |
| 147 | |
| 148 | /* Field definitions in Device Capabilities Register */ |
| 149 | #define DATTN_BUTTN_PRSN 0x1000 |
| 150 | #define DATTN_LED_PRSN 0x2000 |
| 151 | #define DPWR_LED_PRSN 0x4000 |
| 152 | |
| 153 | /* Field definitions in Link Capabilities Register */ |
| 154 | #define MAX_LNK_SPEED 0x000F |
| 155 | #define MAX_LNK_WIDTH 0x03F0 |
| 156 | |
| 157 | /* Link Width Encoding */ |
| 158 | #define LNK_X1 0x01 |
| 159 | #define LNK_X2 0x02 |
| 160 | #define LNK_X4 0x04 |
| 161 | #define LNK_X8 0x08 |
| 162 | #define LNK_X12 0x0C |
| 163 | #define LNK_X16 0x10 |
| 164 | #define LNK_X32 0x20 |
| 165 | |
| 166 | /*Field definitions of Link Status Register */ |
| 167 | #define LNK_SPEED 0x000F |
| 168 | #define NEG_LINK_WD 0x03F0 |
| 169 | #define LNK_TRN_ERR 0x0400 |
| 170 | #define LNK_TRN 0x0800 |
| 171 | #define SLOT_CLK_CONF 0x1000 |
| 172 | |
| 173 | /* Field definitions in Slot Capabilities Register */ |
| 174 | #define ATTN_BUTTN_PRSN 0x00000001 |
| 175 | #define PWR_CTRL_PRSN 0x00000002 |
| 176 | #define MRL_SENS_PRSN 0x00000004 |
| 177 | #define ATTN_LED_PRSN 0x00000008 |
| 178 | #define PWR_LED_PRSN 0x00000010 |
| 179 | #define HP_SUPR_RM_SUP 0x00000020 |
| 180 | #define HP_CAP 0x00000040 |
| 181 | #define SLOT_PWR_VALUE 0x000003F8 |
| 182 | #define SLOT_PWR_LIMIT 0x00000C00 |
| 183 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ |
| 184 | |
| 185 | /* Field definitions in Slot Control Register */ |
| 186 | #define ATTN_BUTTN_ENABLE 0x0001 |
| 187 | #define PWR_FAULT_DETECT_ENABLE 0x0002 |
| 188 | #define MRL_DETECT_ENABLE 0x0004 |
| 189 | #define PRSN_DETECT_ENABLE 0x0008 |
| 190 | #define CMD_CMPL_INTR_ENABLE 0x0010 |
| 191 | #define HP_INTR_ENABLE 0x0020 |
| 192 | #define ATTN_LED_CTRL 0x00C0 |
| 193 | #define PWR_LED_CTRL 0x0300 |
| 194 | #define PWR_CTRL 0x0400 |
| 195 | |
| 196 | /* Attention indicator and Power indicator states */ |
| 197 | #define LED_ON 0x01 |
| 198 | #define LED_BLINK 0x10 |
| 199 | #define LED_OFF 0x11 |
| 200 | |
| 201 | /* Power Control Command */ |
| 202 | #define POWER_ON 0 |
| 203 | #define POWER_OFF 0x0400 |
| 204 | |
| 205 | /* Field definitions in Slot Status Register */ |
| 206 | #define ATTN_BUTTN_PRESSED 0x0001 |
| 207 | #define PWR_FAULT_DETECTED 0x0002 |
| 208 | #define MRL_SENS_CHANGED 0x0004 |
| 209 | #define PRSN_DETECT_CHANGED 0x0008 |
| 210 | #define CMD_COMPLETED 0x0010 |
| 211 | #define MRL_STATE 0x0020 |
| 212 | #define PRSN_STATE 0x0040 |
| 213 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | static spinlock_t hpc_event_lock; |
| 215 | |
| 216 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | static int ctlr_seq_num = 0; /* Controller sequence # */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 219 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
| 220 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | |
| 222 | /* This is the interrupt polling timeout function. */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 223 | static void int_poll_timeout(unsigned long data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 225 | struct controller *ctrl = (struct controller *)data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | |
| 227 | DBG_ENTER_ROUTINE |
| 228 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | /* Poll for interrupt events. regs == NULL => polling */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 230 | pcie_isr(0, ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 232 | init_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | if (!pciehp_poll_time) |
| 234 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ |
| 235 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 236 | start_int_poll_timer(ctrl, pciehp_poll_time); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | /* This function starts the interrupt polling timer. */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 240 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 242 | /* Clamp to sane value */ |
| 243 | if ((sec <= 0) || (sec > 60)) |
| 244 | sec = 2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 246 | ctrl->poll_timer.function = &int_poll_timeout; |
| 247 | ctrl->poll_timer.data = (unsigned long)ctrl; |
| 248 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
| 249 | add_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | } |
| 251 | |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 252 | static inline int pcie_wait_cmd(struct controller *ctrl) |
| 253 | { |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame^] | 254 | int retval = 0; |
| 255 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
| 256 | unsigned long timeout = msecs_to_jiffies(msecs); |
| 257 | int rc; |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 258 | |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame^] | 259 | rc = wait_event_interruptible_timeout(ctrl->queue, |
| 260 | !ctrl->cmd_busy, timeout); |
| 261 | if (!rc) |
| 262 | dbg("Command not completed in 1000 msec\n"); |
| 263 | else if (rc < 0) { |
| 264 | retval = -EINTR; |
| 265 | info("Command was interrupted by a signal\n"); |
| 266 | } |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 267 | |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame^] | 268 | return retval; |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 269 | } |
| 270 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | static int pcie_write_cmd(struct slot *slot, u16 cmd) |
| 272 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 273 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | int retval = 0; |
| 275 | u16 slot_status; |
| 276 | |
| 277 | DBG_ENTER_ROUTINE |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 278 | |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 279 | mutex_lock(&ctrl->ctrl_lock); |
| 280 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 281 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 283 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 284 | goto out; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 285 | } |
| 286 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 288 | /* After 1 sec and CMD_COMPLETED still not set, just |
| 289 | proceed forward to issue the next command according |
| 290 | to spec. Just print out the error message */ |
| 291 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", |
| 292 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame^] | 295 | ctrl->cmd_busy = 1; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 296 | retval = pciehp_writew(ctrl, SLOTCTRL, (cmd | CMD_CMPL_INTR_ENABLE)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 298 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 299 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 302 | /* |
| 303 | * Wait for command completion. |
| 304 | */ |
| 305 | retval = pcie_wait_cmd(ctrl); |
| 306 | out: |
| 307 | mutex_unlock(&ctrl->ctrl_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | DBG_LEAVE_ROUTINE |
| 309 | return retval; |
| 310 | } |
| 311 | |
| 312 | static int hpc_check_lnk_status(struct controller *ctrl) |
| 313 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | u16 lnk_status; |
| 315 | int retval = 0; |
| 316 | |
| 317 | DBG_ENTER_ROUTINE |
| 318 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 319 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 321 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | return retval; |
| 323 | } |
| 324 | |
| 325 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); |
| 326 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
| 327 | !(lnk_status & NEG_LINK_WD)) { |
| 328 | err("%s : Link Training Error occurs \n", __FUNCTION__); |
| 329 | retval = -1; |
| 330 | return retval; |
| 331 | } |
| 332 | |
| 333 | DBG_LEAVE_ROUTINE |
| 334 | return retval; |
| 335 | } |
| 336 | |
| 337 | |
| 338 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
| 339 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 340 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | u16 slot_ctrl; |
| 342 | u8 atten_led_state; |
| 343 | int retval = 0; |
| 344 | |
| 345 | DBG_ENTER_ROUTINE |
| 346 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 347 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 349 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | return retval; |
| 351 | } |
| 352 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 353 | dbg("%s: SLOTCTRL %x, value read %x\n", |
| 354 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | |
| 356 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; |
| 357 | |
| 358 | switch (atten_led_state) { |
| 359 | case 0: |
| 360 | *status = 0xFF; /* Reserved */ |
| 361 | break; |
| 362 | case 1: |
| 363 | *status = 1; /* On */ |
| 364 | break; |
| 365 | case 2: |
| 366 | *status = 2; /* Blink */ |
| 367 | break; |
| 368 | case 3: |
| 369 | *status = 0; /* Off */ |
| 370 | break; |
| 371 | default: |
| 372 | *status = 0xFF; |
| 373 | break; |
| 374 | } |
| 375 | |
| 376 | DBG_LEAVE_ROUTINE |
| 377 | return 0; |
| 378 | } |
| 379 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 380 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 382 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | u16 slot_ctrl; |
| 384 | u8 pwr_state; |
| 385 | int retval = 0; |
| 386 | |
| 387 | DBG_ENTER_ROUTINE |
| 388 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 389 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 391 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | return retval; |
| 393 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 394 | dbg("%s: SLOTCTRL %x value read %x\n", |
| 395 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | |
| 397 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; |
| 398 | |
| 399 | switch (pwr_state) { |
| 400 | case 0: |
| 401 | *status = 1; |
| 402 | break; |
| 403 | case 1: |
| 404 | *status = 0; |
| 405 | break; |
| 406 | default: |
| 407 | *status = 0xFF; |
| 408 | break; |
| 409 | } |
| 410 | |
| 411 | DBG_LEAVE_ROUTINE |
| 412 | return retval; |
| 413 | } |
| 414 | |
| 415 | |
| 416 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
| 417 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 418 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | u16 slot_status; |
| 420 | int retval = 0; |
| 421 | |
| 422 | DBG_ENTER_ROUTINE |
| 423 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 424 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 426 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | return retval; |
| 428 | } |
| 429 | |
| 430 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
| 431 | |
| 432 | DBG_LEAVE_ROUTINE |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) |
| 437 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 438 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | u16 slot_status; |
| 440 | u8 card_state; |
| 441 | int retval = 0; |
| 442 | |
| 443 | DBG_ENTER_ROUTINE |
| 444 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 445 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 447 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | return retval; |
| 449 | } |
| 450 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); |
| 451 | *status = (card_state == 1) ? 1 : 0; |
| 452 | |
| 453 | DBG_LEAVE_ROUTINE |
| 454 | return 0; |
| 455 | } |
| 456 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 457 | static int hpc_query_power_fault(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 459 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | u16 slot_status; |
| 461 | u8 pwr_fault; |
| 462 | int retval = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | |
| 464 | DBG_ENTER_ROUTINE |
| 465 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 466 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 468 | err("%s: Cannot check for power fault\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | return retval; |
| 470 | } |
| 471 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 472 | |
| 473 | DBG_LEAVE_ROUTINE |
rajesh.shah@intel.com | 8239def | 2005-10-31 16:20:13 -0800 | [diff] [blame] | 474 | return pwr_fault; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
| 478 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 479 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | u16 slot_cmd = 0; |
| 481 | u16 slot_ctrl; |
| 482 | int rc = 0; |
| 483 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 484 | DBG_ENTER_ROUTINE |
| 485 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 486 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 488 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | return rc; |
| 490 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
| 492 | switch (value) { |
| 493 | case 0 : /* turn off */ |
| 494 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; |
| 495 | break; |
| 496 | case 1: /* turn on */ |
| 497 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; |
| 498 | break; |
| 499 | case 2: /* turn blink */ |
| 500 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; |
| 501 | break; |
| 502 | default: |
| 503 | return -1; |
| 504 | } |
| 505 | if (!pciehp_poll_mode) |
| 506 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
| 507 | |
| 508 | pcie_write_cmd(slot, slot_cmd); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 509 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 510 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 512 | DBG_LEAVE_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | return rc; |
| 514 | } |
| 515 | |
| 516 | |
| 517 | static void hpc_set_green_led_on(struct slot *slot) |
| 518 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 519 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | u16 slot_cmd; |
| 521 | u16 slot_ctrl; |
| 522 | int rc = 0; |
| 523 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 524 | DBG_ENTER_ROUTINE |
| 525 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 526 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 528 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | return; |
| 530 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; |
| 532 | if (!pciehp_poll_mode) |
| 533 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
| 534 | |
| 535 | pcie_write_cmd(slot, slot_cmd); |
| 536 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 537 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 538 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 539 | DBG_LEAVE_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | return; |
| 541 | } |
| 542 | |
| 543 | static void hpc_set_green_led_off(struct slot *slot) |
| 544 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 545 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | u16 slot_cmd; |
| 547 | u16 slot_ctrl; |
| 548 | int rc = 0; |
| 549 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 550 | DBG_ENTER_ROUTINE |
| 551 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 552 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 554 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | return; |
| 556 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | |
| 558 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; |
| 559 | |
| 560 | if (!pciehp_poll_mode) |
| 561 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
| 562 | pcie_write_cmd(slot, slot_cmd); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 563 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 564 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 566 | DBG_LEAVE_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | return; |
| 568 | } |
| 569 | |
| 570 | static void hpc_set_green_led_blink(struct slot *slot) |
| 571 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 572 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | u16 slot_cmd; |
| 574 | u16 slot_ctrl; |
| 575 | int rc = 0; |
| 576 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 577 | DBG_ENTER_ROUTINE |
| 578 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 579 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 581 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | return; |
| 583 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | |
| 585 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; |
| 586 | |
| 587 | if (!pciehp_poll_mode) |
| 588 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
| 589 | pcie_write_cmd(slot, slot_cmd); |
| 590 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 591 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 592 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 593 | DBG_LEAVE_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | return; |
| 595 | } |
| 596 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | static void hpc_release_ctlr(struct controller *ctrl) |
| 598 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | DBG_ENTER_ROUTINE |
| 600 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 601 | if (pciehp_poll_mode) |
| 602 | del_timer(&ctrl->poll_timer); |
| 603 | else |
| 604 | free_irq(ctrl->pci_dev->irq, ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 605 | |
| 606 | DBG_LEAVE_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | } |
| 608 | |
| 609 | static int hpc_power_on_slot(struct slot * slot) |
| 610 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 611 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | u16 slot_cmd; |
Rajesh Shah | 5a49f20 | 2005-11-23 15:44:54 -0800 | [diff] [blame] | 613 | u16 slot_ctrl, slot_status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | int retval = 0; |
| 615 | |
| 616 | DBG_ENTER_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | |
Rajesh Shah | 5a49f20 | 2005-11-23 15:44:54 -0800 | [diff] [blame] | 620 | /* Clear sticky power-fault bit from previous power failures */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 621 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 623 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
| 624 | return retval; |
| 625 | } |
| 626 | slot_status &= PWR_FAULT_DETECTED; |
| 627 | if (slot_status) { |
| 628 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); |
| 629 | if (retval) { |
| 630 | err("%s: Cannot write to SLOTSTATUS register\n", |
| 631 | __FUNCTION__); |
| 632 | return retval; |
| 633 | } |
| 634 | } |
| 635 | |
| 636 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
| 637 | if (retval) { |
| 638 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | return retval; |
| 640 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | |
| 642 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; |
| 643 | |
Thomas Schaefer | c7ab337 | 2005-12-08 11:55:57 -0800 | [diff] [blame] | 644 | /* Enable detection that we turned off at slot power-off time */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | if (!pciehp_poll_mode) |
Thomas Schaefer | c7ab337 | 2005-12-08 11:55:57 -0800 | [diff] [blame] | 646 | slot_cmd = slot_cmd | |
| 647 | PWR_FAULT_DETECT_ENABLE | |
| 648 | MRL_DETECT_ENABLE | |
| 649 | PRSN_DETECT_ENABLE | |
| 650 | HP_INTR_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | |
| 652 | retval = pcie_write_cmd(slot, slot_cmd); |
| 653 | |
| 654 | if (retval) { |
| 655 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); |
| 656 | return -1; |
| 657 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 658 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 659 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | |
| 661 | DBG_LEAVE_ROUTINE |
| 662 | |
| 663 | return retval; |
| 664 | } |
| 665 | |
| 666 | static int hpc_power_off_slot(struct slot * slot) |
| 667 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 668 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | u16 slot_cmd; |
| 670 | u16 slot_ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 671 | int retval = 0; |
| 672 | |
| 673 | DBG_ENTER_ROUTINE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 677 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 678 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 679 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | return retval; |
| 681 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | |
| 683 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; |
| 684 | |
Thomas Schaefer | c7ab337 | 2005-12-08 11:55:57 -0800 | [diff] [blame] | 685 | /* |
| 686 | * If we get MRL or presence detect interrupts now, the isr |
| 687 | * will notice the sticky power-fault bit too and issue power |
| 688 | * indicator change commands. This will lead to an endless loop |
| 689 | * of command completions, since the power-fault bit remains on |
| 690 | * till the slot is powered on again. |
| 691 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 692 | if (!pciehp_poll_mode) |
Thomas Schaefer | c7ab337 | 2005-12-08 11:55:57 -0800 | [diff] [blame] | 693 | slot_cmd = (slot_cmd & |
| 694 | ~PWR_FAULT_DETECT_ENABLE & |
| 695 | ~MRL_DETECT_ENABLE & |
| 696 | ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | |
| 698 | retval = pcie_write_cmd(slot, slot_cmd); |
| 699 | |
| 700 | if (retval) { |
| 701 | err("%s: Write command failed!\n", __FUNCTION__); |
| 702 | return -1; |
| 703 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 704 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
| 705 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | |
| 707 | DBG_LEAVE_ROUTINE |
| 708 | |
| 709 | return retval; |
| 710 | } |
| 711 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 712 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 714 | struct controller *ctrl = (struct controller *)dev_id; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | u16 slot_status, intr_detect, intr_loc; |
| 716 | u16 temp_word; |
| 717 | int hp_slot = 0; /* only 1 slot per PCI Express port */ |
| 718 | int rc = 0; |
| 719 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 720 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 722 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | return IRQ_NONE; |
| 724 | } |
| 725 | |
| 726 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | |
| 727 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); |
| 728 | |
| 729 | intr_loc = slot_status & intr_detect; |
| 730 | |
| 731 | /* Check to see if it was our interrupt */ |
| 732 | if ( !intr_loc ) |
| 733 | return IRQ_NONE; |
| 734 | |
| 735 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); |
| 736 | /* Mask Hot-plug Interrupt Enable */ |
| 737 | if (!pciehp_poll_mode) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 738 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 740 | err("%s: Cannot read SLOT_CTRL register\n", |
| 741 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | return IRQ_NONE; |
| 743 | } |
| 744 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 745 | dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", |
| 746 | __FUNCTION__, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 748 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
| 749 | if (rc) { |
| 750 | err("%s: Cannot write to SLOTCTRL register\n", |
| 751 | __FUNCTION__); |
| 752 | return IRQ_NONE; |
| 753 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 755 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 757 | err("%s: Cannot read SLOT_STATUS register\n", |
| 758 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | return IRQ_NONE; |
| 760 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 761 | dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n", |
| 762 | __FUNCTION__, slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | |
| 764 | /* Clear command complete interrupt caused by this write */ |
| 765 | temp_word = 0x1f; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 766 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 768 | err("%s: Cannot write to SLOTSTATUS register\n", |
| 769 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | return IRQ_NONE; |
| 771 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | if (intr_loc & CMD_COMPLETED) { |
| 775 | /* |
| 776 | * Command Complete Interrupt Pending |
| 777 | */ |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame^] | 778 | ctrl->cmd_busy = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | wake_up_interruptible(&ctrl->queue); |
| 780 | } |
| 781 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 782 | if (intr_loc & MRL_SENS_CHANGED) |
| 783 | pciehp_handle_switch_change(hp_slot, ctrl); |
| 784 | |
| 785 | if (intr_loc & ATTN_BUTTN_PRESSED) |
| 786 | pciehp_handle_attention_button(hp_slot, ctrl); |
| 787 | |
| 788 | if (intr_loc & PRSN_DETECT_CHANGED) |
| 789 | pciehp_handle_presence_change(hp_slot, ctrl); |
| 790 | |
| 791 | if (intr_loc & PWR_FAULT_DETECTED) |
| 792 | pciehp_handle_power_fault(hp_slot, ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | |
| 794 | /* Clear all events after serving them */ |
| 795 | temp_word = 0x1F; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 796 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 798 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | return IRQ_NONE; |
| 800 | } |
| 801 | /* Unmask Hot-plug Interrupt Enable */ |
| 802 | if (!pciehp_poll_mode) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 803 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 805 | err("%s: Cannot read SLOTCTRL register\n", |
| 806 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | return IRQ_NONE; |
| 808 | } |
| 809 | |
| 810 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
| 812 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 813 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 815 | err("%s: Cannot write to SLOTCTRL register\n", |
| 816 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | return IRQ_NONE; |
| 818 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 819 | |
| 820 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 821 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 822 | err("%s: Cannot read SLOT_STATUS register\n", |
| 823 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 824 | return IRQ_NONE; |
| 825 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | |
| 827 | /* Clear command complete interrupt caused by this write */ |
| 828 | temp_word = 0x1F; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 829 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 831 | err("%s: Cannot write to SLOTSTATUS failed\n", |
| 832 | __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | return IRQ_NONE; |
| 834 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 835 | dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n", |
| 836 | __FUNCTION__, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | return IRQ_HANDLED; |
| 840 | } |
| 841 | |
| 842 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) |
| 843 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 844 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | enum pcie_link_speed lnk_speed; |
| 846 | u32 lnk_cap; |
| 847 | int retval = 0; |
| 848 | |
| 849 | DBG_ENTER_ROUTINE |
| 850 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 851 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 853 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | return retval; |
| 855 | } |
| 856 | |
| 857 | switch (lnk_cap & 0x000F) { |
| 858 | case 1: |
| 859 | lnk_speed = PCIE_2PT5GB; |
| 860 | break; |
| 861 | default: |
| 862 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; |
| 863 | break; |
| 864 | } |
| 865 | |
| 866 | *value = lnk_speed; |
| 867 | dbg("Max link speed = %d\n", lnk_speed); |
| 868 | DBG_LEAVE_ROUTINE |
| 869 | return retval; |
| 870 | } |
| 871 | |
| 872 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) |
| 873 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 874 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | enum pcie_link_width lnk_wdth; |
| 876 | u32 lnk_cap; |
| 877 | int retval = 0; |
| 878 | |
| 879 | DBG_ENTER_ROUTINE |
| 880 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 881 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 882 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 883 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | return retval; |
| 885 | } |
| 886 | |
| 887 | switch ((lnk_cap & 0x03F0) >> 4){ |
| 888 | case 0: |
| 889 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; |
| 890 | break; |
| 891 | case 1: |
| 892 | lnk_wdth = PCIE_LNK_X1; |
| 893 | break; |
| 894 | case 2: |
| 895 | lnk_wdth = PCIE_LNK_X2; |
| 896 | break; |
| 897 | case 4: |
| 898 | lnk_wdth = PCIE_LNK_X4; |
| 899 | break; |
| 900 | case 8: |
| 901 | lnk_wdth = PCIE_LNK_X8; |
| 902 | break; |
| 903 | case 12: |
| 904 | lnk_wdth = PCIE_LNK_X12; |
| 905 | break; |
| 906 | case 16: |
| 907 | lnk_wdth = PCIE_LNK_X16; |
| 908 | break; |
| 909 | case 32: |
| 910 | lnk_wdth = PCIE_LNK_X32; |
| 911 | break; |
| 912 | default: |
| 913 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
| 914 | break; |
| 915 | } |
| 916 | |
| 917 | *value = lnk_wdth; |
| 918 | dbg("Max link width = %d\n", lnk_wdth); |
| 919 | DBG_LEAVE_ROUTINE |
| 920 | return retval; |
| 921 | } |
| 922 | |
| 923 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) |
| 924 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 925 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
| 927 | int retval = 0; |
| 928 | u16 lnk_status; |
| 929 | |
| 930 | DBG_ENTER_ROUTINE |
| 931 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 932 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 933 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 934 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 935 | return retval; |
| 936 | } |
| 937 | |
| 938 | switch (lnk_status & 0x0F) { |
| 939 | case 1: |
| 940 | lnk_speed = PCIE_2PT5GB; |
| 941 | break; |
| 942 | default: |
| 943 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; |
| 944 | break; |
| 945 | } |
| 946 | |
| 947 | *value = lnk_speed; |
| 948 | dbg("Current link speed = %d\n", lnk_speed); |
| 949 | DBG_LEAVE_ROUTINE |
| 950 | return retval; |
| 951 | } |
| 952 | |
| 953 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) |
| 954 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 955 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
| 957 | int retval = 0; |
| 958 | u16 lnk_status; |
| 959 | |
| 960 | DBG_ENTER_ROUTINE |
| 961 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 962 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 963 | if (retval) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 964 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | return retval; |
| 966 | } |
| 967 | |
| 968 | switch ((lnk_status & 0x03F0) >> 4){ |
| 969 | case 0: |
| 970 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; |
| 971 | break; |
| 972 | case 1: |
| 973 | lnk_wdth = PCIE_LNK_X1; |
| 974 | break; |
| 975 | case 2: |
| 976 | lnk_wdth = PCIE_LNK_X2; |
| 977 | break; |
| 978 | case 4: |
| 979 | lnk_wdth = PCIE_LNK_X4; |
| 980 | break; |
| 981 | case 8: |
| 982 | lnk_wdth = PCIE_LNK_X8; |
| 983 | break; |
| 984 | case 12: |
| 985 | lnk_wdth = PCIE_LNK_X12; |
| 986 | break; |
| 987 | case 16: |
| 988 | lnk_wdth = PCIE_LNK_X16; |
| 989 | break; |
| 990 | case 32: |
| 991 | lnk_wdth = PCIE_LNK_X32; |
| 992 | break; |
| 993 | default: |
| 994 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
| 995 | break; |
| 996 | } |
| 997 | |
| 998 | *value = lnk_wdth; |
| 999 | dbg("Current link width = %d\n", lnk_wdth); |
| 1000 | DBG_LEAVE_ROUTINE |
| 1001 | return retval; |
| 1002 | } |
| 1003 | |
| 1004 | static struct hpc_ops pciehp_hpc_ops = { |
| 1005 | .power_on_slot = hpc_power_on_slot, |
| 1006 | .power_off_slot = hpc_power_off_slot, |
| 1007 | .set_attention_status = hpc_set_attention_status, |
| 1008 | .get_power_status = hpc_get_power_status, |
| 1009 | .get_attention_status = hpc_get_attention_status, |
| 1010 | .get_latch_status = hpc_get_latch_status, |
| 1011 | .get_adapter_status = hpc_get_adapter_status, |
| 1012 | |
| 1013 | .get_max_bus_speed = hpc_get_max_lnk_speed, |
| 1014 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, |
| 1015 | .get_max_lnk_width = hpc_get_max_lnk_width, |
| 1016 | .get_cur_lnk_width = hpc_get_cur_lnk_width, |
| 1017 | |
| 1018 | .query_power_fault = hpc_query_power_fault, |
| 1019 | .green_led_on = hpc_set_green_led_on, |
| 1020 | .green_led_off = hpc_set_green_led_off, |
| 1021 | .green_led_blink = hpc_set_green_led_blink, |
| 1022 | |
| 1023 | .release_ctlr = hpc_release_ctlr, |
| 1024 | .check_lnk_status = hpc_check_lnk_status, |
| 1025 | }; |
| 1026 | |
Kristen Accardi | 783c49f | 2006-03-03 10:16:05 -0800 | [diff] [blame] | 1027 | #ifdef CONFIG_ACPI |
| 1028 | int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) |
| 1029 | { |
| 1030 | acpi_status status; |
| 1031 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); |
| 1032 | struct pci_dev *pdev = dev; |
| 1033 | struct pci_bus *parent; |
MUNEDA Takahiro | b2e6e3b | 2006-03-17 09:18:39 +0900 | [diff] [blame] | 1034 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
Kristen Accardi | 783c49f | 2006-03-03 10:16:05 -0800 | [diff] [blame] | 1035 | |
| 1036 | /* |
| 1037 | * Per PCI firmware specification, we should run the ACPI _OSC |
| 1038 | * method to get control of hotplug hardware before using it. |
| 1039 | * If an _OSC is missing, we look for an OSHP to do the same thing. |
| 1040 | * To handle different BIOS behavior, we look for _OSC and OSHP |
| 1041 | * within the scope of the hotplug controller and its parents, upto |
| 1042 | * the host bridge under which this controller exists. |
| 1043 | */ |
| 1044 | while (!handle) { |
| 1045 | /* |
| 1046 | * This hotplug controller was not listed in the ACPI name |
| 1047 | * space at all. Try to get acpi handle of parent pci bus. |
| 1048 | */ |
| 1049 | if (!pdev || !pdev->bus->parent) |
| 1050 | break; |
| 1051 | parent = pdev->bus->parent; |
| 1052 | dbg("Could not find %s in acpi namespace, trying parent\n", |
| 1053 | pci_name(pdev)); |
| 1054 | if (!parent->self) |
| 1055 | /* Parent must be a host bridge */ |
| 1056 | handle = acpi_get_pci_rootbridge_handle( |
| 1057 | pci_domain_nr(parent), |
| 1058 | parent->number); |
| 1059 | else |
| 1060 | handle = DEVICE_ACPI_HANDLE( |
| 1061 | &(parent->self->dev)); |
| 1062 | pdev = parent->self; |
| 1063 | } |
| 1064 | |
| 1065 | while (handle) { |
MUNEDA Takahiro | b2e6e3b | 2006-03-17 09:18:39 +0900 | [diff] [blame] | 1066 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
| 1067 | dbg("Trying to get hotplug control for %s \n", |
| 1068 | (char *)string.pointer); |
Kristen Accardi | 783c49f | 2006-03-03 10:16:05 -0800 | [diff] [blame] | 1069 | status = pci_osc_control_set(handle, |
| 1070 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); |
| 1071 | if (status == AE_NOT_FOUND) |
| 1072 | status = acpi_run_oshp(handle); |
| 1073 | if (ACPI_SUCCESS(status)) { |
| 1074 | dbg("Gained control for hotplug HW for pci %s (%s)\n", |
MUNEDA Takahiro | b2e6e3b | 2006-03-17 09:18:39 +0900 | [diff] [blame] | 1075 | pci_name(dev), (char *)string.pointer); |
Kristen Accardi | 81b26bc | 2006-04-18 14:36:43 -0700 | [diff] [blame] | 1076 | kfree(string.pointer); |
Kristen Accardi | 783c49f | 2006-03-03 10:16:05 -0800 | [diff] [blame] | 1077 | return 0; |
| 1078 | } |
| 1079 | if (acpi_root_bridge(handle)) |
| 1080 | break; |
| 1081 | chandle = handle; |
| 1082 | status = acpi_get_parent(chandle, &handle); |
| 1083 | if (ACPI_FAILURE(status)) |
| 1084 | break; |
| 1085 | } |
| 1086 | |
| 1087 | err("Cannot get control of hotplug hardware for pci %s\n", |
| 1088 | pci_name(dev)); |
MUNEDA Takahiro | b2e6e3b | 2006-03-17 09:18:39 +0900 | [diff] [blame] | 1089 | |
Kristen Accardi | 81b26bc | 2006-04-18 14:36:43 -0700 | [diff] [blame] | 1090 | kfree(string.pointer); |
Kristen Accardi | 783c49f | 2006-03-03 10:16:05 -0800 | [diff] [blame] | 1091 | return -1; |
| 1092 | } |
| 1093 | #endif |
| 1094 | |
| 1095 | |
| 1096 | |
rajesh.shah@intel.com | ed6cbcf | 2005-10-31 16:20:09 -0800 | [diff] [blame] | 1097 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1098 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1099 | int rc; |
| 1100 | static int first = 1; |
| 1101 | u16 temp_word; |
| 1102 | u16 cap_reg; |
| 1103 | u16 intr_enable = 0; |
| 1104 | u32 slot_cap; |
Kenji Kaneshige | 75e1317 | 2006-12-21 17:01:08 -0800 | [diff] [blame] | 1105 | int cap_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1106 | u16 slot_status, slot_ctrl; |
| 1107 | struct pci_dev *pdev; |
| 1108 | |
| 1109 | DBG_ENTER_ROUTINE |
| 1110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1111 | pdev = dev->port; |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1112 | ctrl->pci_dev = pdev; /* save pci_dev in context */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 1114 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
| 1115 | __FUNCTION__, pdev->vendor, pdev->device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1116 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { |
| 1118 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); |
| 1119 | goto abort_free_ctlr; |
| 1120 | } |
| 1121 | |
Dely Sy | 8b245e4 | 2005-05-06 17:19:09 -0700 | [diff] [blame] | 1122 | ctrl->cap_base = cap_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1123 | |
Kenji Kaneshige | 75e1317 | 2006-12-21 17:01:08 -0800 | [diff] [blame] | 1124 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1125 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1126 | rc = pciehp_readw(ctrl, CAPREG, &cap_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1128 | err("%s: Cannot read CAPREG register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1129 | goto abort_free_ctlr; |
| 1130 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1131 | dbg("%s: CAPREG offset %x cap_reg %x\n", |
| 1132 | __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1133 | |
Dely Sy | 8b245e4 | 2005-05-06 17:19:09 -0700 | [diff] [blame] | 1134 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) |
| 1135 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1136 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); |
| 1137 | goto abort_free_ctlr; |
| 1138 | } |
| 1139 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1140 | rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1142 | err("%s: Cannot read SLOTCAP register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | goto abort_free_ctlr; |
| 1144 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1145 | dbg("%s: SLOTCAP offset %x slot_cap %x\n", |
| 1146 | __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | |
| 1148 | if (!(slot_cap & HP_CAP)) { |
| 1149 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); |
| 1150 | goto abort_free_ctlr; |
| 1151 | } |
| 1152 | /* For debugging purpose */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1153 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1154 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1155 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | goto abort_free_ctlr; |
| 1157 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1158 | dbg("%s: SLOTSTATUS offset %x slot_status %x\n", |
| 1159 | __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1160 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1161 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1163 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | goto abort_free_ctlr; |
| 1165 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1166 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", |
| 1167 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
| 1169 | if (first) { |
| 1170 | spin_lock_init(&hpc_event_lock); |
| 1171 | first = 0; |
| 1172 | } |
| 1173 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
| 1175 | if (pci_resource_len(pdev, rc) > 0) |
Greg Kroah-Hartman | 1396a8c | 2006-06-12 15:14:29 -0700 | [diff] [blame] | 1176 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, |
| 1177 | (unsigned long long)pci_resource_start(pdev, rc), |
| 1178 | (unsigned long long)pci_resource_len(pdev, rc)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | |
| 1180 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, |
| 1181 | pdev->subsystem_vendor, pdev->subsystem_device); |
| 1182 | |
Ingo Molnar | 6aa4cdd | 2006-01-13 16:02:15 +0100 | [diff] [blame] | 1183 | mutex_init(&ctrl->crit_sect); |
Kenji Kaneshige | dd5619c | 2006-09-22 10:17:29 -0700 | [diff] [blame] | 1184 | mutex_init(&ctrl->ctrl_lock); |
| 1185 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1186 | /* setup wait queue */ |
| 1187 | init_waitqueue_head(&ctrl->queue); |
| 1188 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1189 | /* return PCI Controller Info */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1190 | ctrl->slot_device_offset = 0; |
| 1191 | ctrl->num_slots = 1; |
| 1192 | ctrl->first_slot = slot_cap >> 19; |
| 1193 | ctrl->ctrlcap = slot_cap & 0x0000007f; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | |
| 1195 | /* Mask Hot-plug Interrupt Enable */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1196 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1197 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1198 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1199 | goto abort_free_ctlr; |
| 1200 | } |
| 1201 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1202 | dbg("%s: SLOTCTRL %x value read %x\n", |
| 1203 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1204 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
| 1205 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1206 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1207 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1208 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1209 | goto abort_free_ctlr; |
| 1210 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1212 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1213 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1214 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1215 | goto abort_free_ctlr; |
| 1216 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | |
| 1218 | temp_word = 0x1F; /* Clear all events */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1219 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1220 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1221 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1222 | goto abort_free_ctlr; |
| 1223 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1224 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1225 | if (pciehp_poll_mode) { |
| 1226 | /* Install interrupt polling timer. Start with 10 sec delay */ |
| 1227 | init_timer(&ctrl->poll_timer); |
| 1228 | start_int_poll_timer(ctrl, 10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | } else { |
| 1230 | /* Installs the interrupt handler */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1231 | rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, |
| 1232 | MY_NAME, (void *)ctrl); |
| 1233 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", |
| 1234 | __FUNCTION__, ctrl->pci_dev->irq, ctlr_seq_num, rc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | if (rc) { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1236 | err("Can't get irq %d for the hotplug controller\n", |
| 1237 | ctrl->pci_dev->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1238 | goto abort_free_ctlr; |
| 1239 | } |
| 1240 | } |
rajesh.shah@intel.com | 1a9ed1b | 2005-10-31 16:20:10 -0800 | [diff] [blame] | 1241 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
| 1242 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); |
| 1243 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1244 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1245 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1246 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1247 | goto abort_free_irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1248 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1249 | |
| 1250 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; |
| 1251 | |
| 1252 | if (ATTN_BUTTN(slot_cap)) |
| 1253 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; |
| 1254 | |
| 1255 | if (POWER_CTRL(slot_cap)) |
| 1256 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; |
| 1257 | |
| 1258 | if (MRL_SENS(slot_cap)) |
| 1259 | intr_enable = intr_enable | MRL_DETECT_ENABLE; |
| 1260 | |
| 1261 | temp_word = (temp_word & ~intr_enable) | intr_enable; |
| 1262 | |
| 1263 | if (pciehp_poll_mode) { |
| 1264 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; |
| 1265 | } else { |
| 1266 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
| 1267 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | |
| 1269 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1270 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1272 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1273 | goto abort_free_irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | } |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1275 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1277 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1278 | goto abort_disable_intr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1279 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1280 | |
| 1281 | temp_word = 0x1F; /* Clear all events */ |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1282 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1283 | if (rc) { |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1284 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1285 | goto abort_disable_intr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1286 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | |
rajesh.shah@intel.com | a3a45ec | 2005-10-31 16:20:12 -0800 | [diff] [blame] | 1288 | if (pciehp_force) { |
| 1289 | dbg("Bypassing BIOS check for pciehp use on %s\n", |
| 1290 | pci_name(ctrl->pci_dev)); |
| 1291 | } else { |
Rajesh Shah | 6560aa5 | 2005-11-07 13:37:36 -0800 | [diff] [blame] | 1292 | rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); |
rajesh.shah@intel.com | a3a45ec | 2005-10-31 16:20:12 -0800 | [diff] [blame] | 1293 | if (rc) |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1294 | goto abort_disable_intr; |
rajesh.shah@intel.com | a3a45ec | 2005-10-31 16:20:12 -0800 | [diff] [blame] | 1295 | } |
rajesh.shah@intel.com | a8a2be9 | 2005-10-31 16:20:07 -0800 | [diff] [blame] | 1296 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1297 | ctlr_seq_num++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | ctrl->hpc_ops = &pciehp_hpc_ops; |
| 1299 | |
| 1300 | DBG_LEAVE_ROUTINE |
| 1301 | return 0; |
| 1302 | |
| 1303 | /* We end up here for the many possible ways to fail this API. */ |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1304 | abort_disable_intr: |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1305 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1306 | if (!rc) { |
| 1307 | temp_word &= ~(intr_enable | HP_INTR_ENABLE); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 1308 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1309 | } |
| 1310 | if (rc) |
| 1311 | err("%s : disabling interrupts failed\n", __FUNCTION__); |
| 1312 | |
| 1313 | abort_free_irq: |
| 1314 | if (pciehp_poll_mode) |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1315 | del_timer_sync(&ctrl->poll_timer); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1316 | else |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 1317 | free_irq(ctrl->pci_dev->irq, ctrl); |
Jan Beulich | 9c64f97 | 2006-05-09 00:50:31 -0700 | [diff] [blame] | 1318 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | abort_free_ctlr: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1320 | DBG_LEAVE_ROUTINE |
| 1321 | return -1; |
| 1322 | } |