Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 12 | #include "skeleton.dtsi" |
Markus Pargmann | 61664d0 | 2014-02-08 13:54:43 +0800 | [diff] [blame] | 13 | #include "imx27-pinfunc.h" |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 14 | |
| 15 | #include <dt-bindings/clock/imx27-clock.h> |
| 16 | #include <dt-bindings/gpio/gpio.h> |
Fabio Estevam | f6bd3f3 | 2014-04-17 15:23:31 -0300 | [diff] [blame] | 17 | #include <dt-bindings/input/input.h> |
Alexander Shiyan | 6ece55b | 2013-11-30 10:18:04 +0400 | [diff] [blame] | 18 | #include <dt-bindings/interrupt-controller/irq.h> |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 19 | |
| 20 | / { |
| 21 | aliases { |
Marek Vasut | 2297007 | 2014-02-28 12:58:41 +0100 | [diff] [blame] | 22 | ethernet0 = &fec; |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 23 | gpio0 = &gpio1; |
| 24 | gpio1 = &gpio2; |
| 25 | gpio2 = &gpio3; |
| 26 | gpio3 = &gpio4; |
| 27 | gpio4 = &gpio5; |
| 28 | gpio5 = &gpio6; |
Sascha Hauer | 6a3c0b3 | 2013-06-25 15:51:54 +0200 | [diff] [blame] | 29 | i2c0 = &i2c1; |
| 30 | i2c1 = &i2c2; |
| 31 | serial0 = &uart1; |
| 32 | serial1 = &uart2; |
| 33 | serial2 = &uart3; |
| 34 | serial3 = &uart4; |
| 35 | serial4 = &uart5; |
| 36 | serial5 = &uart6; |
Alexander Shiyan | a5a641a | 2013-05-01 14:46:57 +0400 | [diff] [blame] | 37 | spi0 = &cspi1; |
| 38 | spi1 = &cspi2; |
| 39 | spi2 = &cspi3; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 40 | }; |
| 41 | |
Fabio Estevam | 6189bc3 | 2013-06-28 16:50:33 +0200 | [diff] [blame] | 42 | aitc: aitc-interrupt-controller@e0000000 { |
| 43 | compatible = "fsl,imx27-aitc", "fsl,avic"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 44 | interrupt-controller; |
| 45 | #interrupt-cells = <1>; |
| 46 | reg = <0x10040000 0x1000>; |
| 47 | }; |
| 48 | |
| 49 | clocks { |
| 50 | #address-cells = <1>; |
| 51 | #size-cells = <0>; |
| 52 | |
| 53 | osc26m { |
| 54 | compatible = "fsl,imx-osc26m", "fixed-clock"; |
Shawn Guo | 4b2b404 | 2014-04-11 09:56:46 +0800 | [diff] [blame] | 55 | #clock-cells = <0>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 56 | clock-frequency = <26000000>; |
| 57 | }; |
| 58 | }; |
| 59 | |
Markus Pargmann | dc1d0f9 | 2013-06-28 16:50:36 +0200 | [diff] [blame] | 60 | cpus { |
| 61 | #size-cells = <0>; |
| 62 | #address-cells = <1>; |
| 63 | |
Alexander Shiyan | 48568be | 2013-07-20 11:17:56 +0400 | [diff] [blame] | 64 | cpu: cpu@0 { |
Markus Pargmann | dc1d0f9 | 2013-06-28 16:50:36 +0200 | [diff] [blame] | 65 | device_type = "cpu"; |
| 66 | compatible = "arm,arm926ej-s"; |
| 67 | operating-points = < |
Alexander Shiyan | 98a3e80 | 2013-07-13 08:34:44 +0400 | [diff] [blame] | 68 | /* kHz uV */ |
| 69 | 266000 1300000 |
| 70 | 399000 1450000 |
Markus Pargmann | dc1d0f9 | 2013-06-28 16:50:36 +0200 | [diff] [blame] | 71 | >; |
Alexander Shiyan | 8defcb5 | 2013-07-20 11:17:57 +0400 | [diff] [blame] | 72 | clock-latency = <62500>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 73 | clocks = <&clks IMX27_CLK_CPU_DIV>; |
Alexander Shiyan | 98a3e80 | 2013-07-13 08:34:44 +0400 | [diff] [blame] | 74 | voltage-tolerance = <5>; |
Markus Pargmann | dc1d0f9 | 2013-06-28 16:50:36 +0200 | [diff] [blame] | 75 | }; |
| 76 | }; |
| 77 | |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 78 | soc { |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | compatible = "simple-bus"; |
Fabio Estevam | 6189bc3 | 2013-06-28 16:50:33 +0200 | [diff] [blame] | 82 | interrupt-parent = <&aitc>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 83 | ranges; |
| 84 | |
| 85 | aipi@10000000 { /* AIPI1 */ |
| 86 | compatible = "fsl,aipi-bus", "simple-bus"; |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <1>; |
Fabio Estevam | 3e24b05 | 2012-11-21 17:19:38 -0200 | [diff] [blame] | 89 | reg = <0x10000000 0x20000>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 90 | ranges; |
| 91 | |
Alexander Shiyan | b858c34 | 2013-06-08 18:39:36 +0400 | [diff] [blame] | 92 | dma: dma@10001000 { |
| 93 | compatible = "fsl,imx27-dma"; |
| 94 | reg = <0x10001000 0x1000>; |
| 95 | interrupts = <32>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 96 | clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, |
| 97 | <&clks IMX27_CLK_DMA_AHB_GATE>; |
Alexander Shiyan | b858c34 | 2013-06-08 18:39:36 +0400 | [diff] [blame] | 98 | clock-names = "ipg", "ahb"; |
| 99 | #dma-cells = <1>; |
| 100 | #dma-channels = <16>; |
| 101 | }; |
| 102 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 103 | wdog: wdog@10002000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 104 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 105 | reg = <0x10002000 0x1000>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 106 | interrupts = <27>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 107 | clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 108 | }; |
| 109 | |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 110 | gpt1: timer@10003000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 111 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 112 | reg = <0x10003000 0x1000>; |
| 113 | interrupts = <26>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 114 | clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, |
| 115 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 116 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | gpt2: timer@10004000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 120 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 121 | reg = <0x10004000 0x1000>; |
| 122 | interrupts = <25>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 123 | clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, |
| 124 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 125 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | gpt3: timer@10005000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 129 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 130 | reg = <0x10005000 0x1000>; |
| 131 | interrupts = <24>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 132 | clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, |
| 133 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 134 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 135 | }; |
| 136 | |
Alexander Shiyan | a392d04 | 2013-06-23 10:54:47 +0400 | [diff] [blame] | 137 | pwm: pwm@10006000 { |
Steffen Trumtrar | 443b658 | 2013-10-17 15:03:16 +0200 | [diff] [blame] | 138 | #pwm-cells = <2>; |
Gwenhael Goavec-Merou | 08f4881a | 2013-04-14 09:44:25 +0200 | [diff] [blame] | 139 | compatible = "fsl,imx27-pwm"; |
| 140 | reg = <0x10006000 0x1000>; |
| 141 | interrupts = <23>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 142 | clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, |
| 143 | <&clks IMX27_CLK_PER1_GATE>; |
Gwenhael Goavec-Merou | 08f4881a | 2013-04-14 09:44:25 +0200 | [diff] [blame] | 144 | clock-names = "ipg", "per"; |
| 145 | }; |
| 146 | |
Philippe Reynes | 91eca8d | 2015-07-26 23:37:53 +0200 | [diff] [blame] | 147 | rtc: rtc@10007000 { |
| 148 | compatible = "fsl,imx21-rtc"; |
| 149 | reg = <0x10007000 0x1000>; |
| 150 | interrupts = <22>; |
| 151 | clocks = <&clks IMX27_CLK_CKIL>, |
| 152 | <&clks IMX27_CLK_RTC_IPG_GATE>; |
| 153 | clock-names = "ref", "ipg"; |
| 154 | }; |
| 155 | |
Alexander Shiyan | 6c04ad2 | 2013-06-23 10:54:50 +0400 | [diff] [blame] | 156 | kpp: kpp@10008000 { |
| 157 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; |
| 158 | reg = <0x10008000 0x1000>; |
| 159 | interrupts = <21>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 160 | clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; |
Alexander Shiyan | 6c04ad2 | 2013-06-23 10:54:50 +0400 | [diff] [blame] | 161 | status = "disabled"; |
| 162 | }; |
| 163 | |
Markus Pargmann | 6a486b7 | 2013-07-01 17:21:22 +0800 | [diff] [blame] | 164 | owire: owire@10009000 { |
| 165 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; |
| 166 | reg = <0x10009000 0x1000>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 167 | clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; |
Markus Pargmann | 6a486b7 | 2013-07-01 17:21:22 +0800 | [diff] [blame] | 168 | status = "disabled"; |
| 169 | }; |
| 170 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 171 | uart1: serial@1000a000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 172 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 173 | reg = <0x1000a000 0x1000>; |
| 174 | interrupts = <20>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 175 | clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, |
| 176 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 177 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 178 | status = "disabled"; |
| 179 | }; |
| 180 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 181 | uart2: serial@1000b000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 182 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 183 | reg = <0x1000b000 0x1000>; |
| 184 | interrupts = <19>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 185 | clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, |
| 186 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 187 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 188 | status = "disabled"; |
| 189 | }; |
| 190 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 191 | uart3: serial@1000c000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 192 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 193 | reg = <0x1000c000 0x1000>; |
| 194 | interrupts = <18>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 195 | clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, |
| 196 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 197 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 198 | status = "disabled"; |
| 199 | }; |
| 200 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 201 | uart4: serial@1000d000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 202 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 203 | reg = <0x1000d000 0x1000>; |
| 204 | interrupts = <17>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 205 | clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, |
| 206 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 207 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | cspi1: cspi@1000e000 { |
| 212 | #address-cells = <1>; |
| 213 | #size-cells = <0>; |
| 214 | compatible = "fsl,imx27-cspi"; |
| 215 | reg = <0x1000e000 0x1000>; |
| 216 | interrupts = <16>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 217 | clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, |
| 218 | <&clks IMX27_CLK_PER2_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 219 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 220 | status = "disabled"; |
| 221 | }; |
| 222 | |
| 223 | cspi2: cspi@1000f000 { |
| 224 | #address-cells = <1>; |
| 225 | #size-cells = <0>; |
| 226 | compatible = "fsl,imx27-cspi"; |
| 227 | reg = <0x1000f000 0x1000>; |
| 228 | interrupts = <15>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 229 | clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, |
| 230 | <&clks IMX27_CLK_PER2_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 231 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 232 | status = "disabled"; |
| 233 | }; |
| 234 | |
Alexander Shiyan | ba2d1ea | 2014-01-04 22:28:35 +0400 | [diff] [blame] | 235 | ssi1: ssi@10010000 { |
| 236 | #sound-dai-cells = <0>; |
| 237 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; |
| 238 | reg = <0x10010000 0x1000>; |
| 239 | interrupts = <14>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 240 | clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; |
Alexander Shiyan | ba2d1ea | 2014-01-04 22:28:35 +0400 | [diff] [blame] | 241 | dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; |
| 242 | dma-names = "rx0", "tx0", "rx1", "tx1"; |
| 243 | fsl,fifo-depth = <8>; |
| 244 | status = "disabled"; |
| 245 | }; |
| 246 | |
| 247 | ssi2: ssi@10011000 { |
| 248 | #sound-dai-cells = <0>; |
| 249 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; |
| 250 | reg = <0x10011000 0x1000>; |
| 251 | interrupts = <13>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 252 | clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; |
Alexander Shiyan | ba2d1ea | 2014-01-04 22:28:35 +0400 | [diff] [blame] | 253 | dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; |
| 254 | dma-names = "rx0", "tx0", "rx1", "tx1"; |
| 255 | fsl,fifo-depth = <8>; |
| 256 | status = "disabled"; |
| 257 | }; |
| 258 | |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 259 | i2c1: i2c@10012000 { |
| 260 | #address-cells = <1>; |
| 261 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 262 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 263 | reg = <0x10012000 0x1000>; |
| 264 | interrupts = <12>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 265 | clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 266 | status = "disabled"; |
| 267 | }; |
| 268 | |
Alexander Shiyan | 0e7b01a | 2013-06-08 18:39:37 +0400 | [diff] [blame] | 269 | sdhci1: sdhci@10013000 { |
| 270 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 271 | reg = <0x10013000 0x1000>; |
| 272 | interrupts = <11>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 273 | clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, |
| 274 | <&clks IMX27_CLK_PER2_GATE>; |
Alexander Shiyan | 0e7b01a | 2013-06-08 18:39:37 +0400 | [diff] [blame] | 275 | clock-names = "ipg", "per"; |
| 276 | dmas = <&dma 7>; |
| 277 | dma-names = "rx-tx"; |
| 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | sdhci2: sdhci@10014000 { |
| 282 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 283 | reg = <0x10014000 0x1000>; |
| 284 | interrupts = <10>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 285 | clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, |
| 286 | <&clks IMX27_CLK_PER2_GATE>; |
Alexander Shiyan | 0e7b01a | 2013-06-08 18:39:37 +0400 | [diff] [blame] | 287 | clock-names = "ipg", "per"; |
| 288 | dmas = <&dma 6>; |
| 289 | dma-names = "rx-tx"; |
| 290 | status = "disabled"; |
| 291 | }; |
| 292 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 293 | iomuxc: iomuxc@10015000 { |
| 294 | compatible = "fsl,imx27-iomuxc"; |
| 295 | reg = <0x10015000 0x600>; |
| 296 | #address-cells = <1>; |
| 297 | #size-cells = <1>; |
| 298 | ranges; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 299 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 300 | gpio1: gpio@10015000 { |
| 301 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 302 | reg = <0x10015000 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 303 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 304 | interrupts = <8>; |
| 305 | gpio-controller; |
| 306 | #gpio-cells = <2>; |
| 307 | interrupt-controller; |
| 308 | #interrupt-cells = <2>; |
| 309 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 310 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 311 | gpio2: gpio@10015100 { |
| 312 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 313 | reg = <0x10015100 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 314 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 315 | interrupts = <8>; |
| 316 | gpio-controller; |
| 317 | #gpio-cells = <2>; |
| 318 | interrupt-controller; |
| 319 | #interrupt-cells = <2>; |
| 320 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 321 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 322 | gpio3: gpio@10015200 { |
| 323 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 324 | reg = <0x10015200 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 325 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 326 | interrupts = <8>; |
| 327 | gpio-controller; |
| 328 | #gpio-cells = <2>; |
| 329 | interrupt-controller; |
| 330 | #interrupt-cells = <2>; |
| 331 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 332 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 333 | gpio4: gpio@10015300 { |
| 334 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 335 | reg = <0x10015300 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 336 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 337 | interrupts = <8>; |
| 338 | gpio-controller; |
| 339 | #gpio-cells = <2>; |
| 340 | interrupt-controller; |
| 341 | #interrupt-cells = <2>; |
| 342 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 343 | |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 344 | gpio5: gpio@10015400 { |
| 345 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 346 | reg = <0x10015400 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 347 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 348 | interrupts = <8>; |
| 349 | gpio-controller; |
| 350 | #gpio-cells = <2>; |
| 351 | interrupt-controller; |
| 352 | #interrupt-cells = <2>; |
| 353 | }; |
| 354 | |
| 355 | gpio6: gpio@10015500 { |
| 356 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 357 | reg = <0x10015500 0x100>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 358 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
Markus Pargmann | 733f6ca | 2013-11-20 09:45:48 +0100 | [diff] [blame] | 359 | interrupts = <8>; |
| 360 | gpio-controller; |
| 361 | #gpio-cells = <2>; |
| 362 | interrupt-controller; |
| 363 | #interrupt-cells = <2>; |
| 364 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 365 | }; |
| 366 | |
Alexander Shiyan | 6e228e8 | 2013-06-23 10:54:46 +0400 | [diff] [blame] | 367 | audmux: audmux@10016000 { |
| 368 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; |
| 369 | reg = <0x10016000 0x1000>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 370 | clocks = <&clks IMX27_CLK_DUMMY>; |
Alexander Shiyan | 6e228e8 | 2013-06-23 10:54:46 +0400 | [diff] [blame] | 371 | clock-names = "audmux"; |
Alexander Shiyan | 1c04ab0 | 2013-08-10 12:51:50 +0400 | [diff] [blame] | 372 | status = "disabled"; |
Alexander Shiyan | 6e228e8 | 2013-06-23 10:54:46 +0400 | [diff] [blame] | 373 | }; |
| 374 | |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 375 | cspi3: cspi@10017000 { |
| 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; |
| 378 | compatible = "fsl,imx27-cspi"; |
| 379 | reg = <0x10017000 0x1000>; |
| 380 | interrupts = <6>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 381 | clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, |
| 382 | <&clks IMX27_CLK_PER2_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 383 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 384 | status = "disabled"; |
| 385 | }; |
| 386 | |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 387 | gpt4: timer@10019000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 388 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 389 | reg = <0x10019000 0x1000>; |
| 390 | interrupts = <4>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 391 | clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, |
| 392 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 393 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | gpt5: timer@1001a000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 397 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 398 | reg = <0x1001a000 0x1000>; |
| 399 | interrupts = <3>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 400 | clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, |
| 401 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 402 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 403 | }; |
| 404 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 405 | uart5: serial@1001b000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 406 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 407 | reg = <0x1001b000 0x1000>; |
| 408 | interrupts = <49>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 409 | clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, |
| 410 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 411 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 412 | status = "disabled"; |
| 413 | }; |
| 414 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 415 | uart6: serial@1001c000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 416 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 417 | reg = <0x1001c000 0x1000>; |
| 418 | interrupts = <48>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 419 | clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, |
| 420 | <&clks IMX27_CLK_PER1_GATE>; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 421 | clock-names = "ipg", "per"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 422 | status = "disabled"; |
| 423 | }; |
| 424 | |
| 425 | i2c2: i2c@1001d000 { |
| 426 | #address-cells = <1>; |
| 427 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 428 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 429 | reg = <0x1001d000 0x1000>; |
| 430 | interrupts = <1>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 431 | clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 432 | status = "disabled"; |
| 433 | }; |
| 434 | |
Alexander Shiyan | 0e7b01a | 2013-06-08 18:39:37 +0400 | [diff] [blame] | 435 | sdhci3: sdhci@1001e000 { |
| 436 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; |
| 437 | reg = <0x1001e000 0x1000>; |
| 438 | interrupts = <9>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 439 | clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, |
| 440 | <&clks IMX27_CLK_PER2_GATE>; |
Alexander Shiyan | 0e7b01a | 2013-06-08 18:39:37 +0400 | [diff] [blame] | 441 | clock-names = "ipg", "per"; |
| 442 | dmas = <&dma 36>; |
| 443 | dma-names = "rx-tx"; |
| 444 | status = "disabled"; |
| 445 | }; |
| 446 | |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 447 | gpt6: timer@1001f000 { |
Fabio Estevam | afde131 | 2015-06-27 17:51:13 -0300 | [diff] [blame] | 448 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 449 | reg = <0x1001f000 0x1000>; |
| 450 | interrupts = <2>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 451 | clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, |
| 452 | <&clks IMX27_CLK_PER1_GATE>; |
Sascha Hauer | b700c11 | 2013-03-14 13:09:02 +0100 | [diff] [blame] | 453 | clock-names = "ipg", "per"; |
Sascha Hauer | ca26d04 | 2013-03-14 13:08:57 +0100 | [diff] [blame] | 454 | }; |
Fabio Estevam | 3e24b05 | 2012-11-21 17:19:38 -0200 | [diff] [blame] | 455 | }; |
| 456 | |
| 457 | aipi@10020000 { /* AIPI2 */ |
| 458 | compatible = "fsl,aipi-bus", "simple-bus"; |
| 459 | #address-cells = <1>; |
| 460 | #size-cells = <1>; |
| 461 | reg = <0x10020000 0x20000>; |
| 462 | ranges; |
| 463 | |
Markus Pargmann | 5e57b24 | 2013-06-28 16:50:34 +0200 | [diff] [blame] | 464 | fb: fb@10021000 { |
| 465 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; |
| 466 | interrupts = <61>; |
| 467 | reg = <0x10021000 0x1000>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 468 | clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, |
| 469 | <&clks IMX27_CLK_LCDC_AHB_GATE>, |
| 470 | <&clks IMX27_CLK_PER3_GATE>; |
Markus Pargmann | 5e57b24 | 2013-06-28 16:50:34 +0200 | [diff] [blame] | 471 | clock-names = "ipg", "ahb", "per"; |
| 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
Alexander Shiyan | 93b331c | 2013-06-15 16:22:58 +0400 | [diff] [blame] | 475 | coda: coda@10023000 { |
Fabio Estevam | 7194661 | 2014-11-27 10:18:19 -0200 | [diff] [blame] | 476 | compatible = "fsl,imx27-vpu", "cnm,codadx6"; |
Alexander Shiyan | 93b331c | 2013-06-15 16:22:58 +0400 | [diff] [blame] | 477 | reg = <0x10023000 0x0200>; |
| 478 | interrupts = <53>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 479 | clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, |
| 480 | <&clks IMX27_CLK_VPU_AHB_GATE>; |
Alexander Shiyan | 93b331c | 2013-06-15 16:22:58 +0400 | [diff] [blame] | 481 | clock-names = "per", "ahb"; |
| 482 | iram = <&iram>; |
| 483 | }; |
| 484 | |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 485 | usbotg: usb@10024000 { |
| 486 | compatible = "fsl,imx27-usb"; |
| 487 | reg = <0x10024000 0x200>; |
| 488 | interrupts = <56>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 489 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 490 | fsl,usbmisc = <&usbmisc 0>; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | usbh1: usb@10024200 { |
| 495 | compatible = "fsl,imx27-usb"; |
| 496 | reg = <0x10024200 0x200>; |
| 497 | interrupts = <54>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 498 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 499 | fsl,usbmisc = <&usbmisc 1>; |
Matt Porter | 3ec481e | 2015-02-27 09:06:00 -0500 | [diff] [blame] | 500 | dr_mode = "host"; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 501 | status = "disabled"; |
| 502 | }; |
| 503 | |
| 504 | usbh2: usb@10024400 { |
| 505 | compatible = "fsl,imx27-usb"; |
| 506 | reg = <0x10024400 0x200>; |
| 507 | interrupts = <55>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 508 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 509 | fsl,usbmisc = <&usbmisc 2>; |
Matt Porter | 3ec481e | 2015-02-27 09:06:00 -0500 | [diff] [blame] | 510 | dr_mode = "host"; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 511 | status = "disabled"; |
| 512 | }; |
| 513 | |
| 514 | usbmisc: usbmisc@10024600 { |
| 515 | #index-cells = <1>; |
| 516 | compatible = "fsl,imx27-usbmisc"; |
| 517 | reg = <0x10024600 0x200>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 518 | clocks = <&clks IMX27_CLK_USB_AHB_GATE>; |
Alexander Shiyan | a2e502c | 2014-02-22 13:32:33 +0400 | [diff] [blame] | 519 | }; |
| 520 | |
Alexander Shiyan | e4b6a05 | 2013-06-23 10:54:45 +0400 | [diff] [blame] | 521 | sahara2: sahara@10025000 { |
| 522 | compatible = "fsl,imx27-sahara"; |
| 523 | reg = <0x10025000 0x1000>; |
| 524 | interrupts = <59>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 525 | clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, |
| 526 | <&clks IMX27_CLK_SAHARA_AHB_GATE>; |
Alexander Shiyan | e4b6a05 | 2013-06-23 10:54:45 +0400 | [diff] [blame] | 527 | clock-names = "ipg", "ahb"; |
| 528 | }; |
| 529 | |
Alexander Shiyan | 93b331c | 2013-06-15 16:22:58 +0400 | [diff] [blame] | 530 | clks: ccm@10027000{ |
| 531 | compatible = "fsl,imx27-ccm"; |
| 532 | reg = <0x10027000 0x1000>; |
| 533 | #clock-cells = <1>; |
| 534 | }; |
| 535 | |
Alexander Shiyan | d36afcd | 2013-07-02 20:02:24 +0400 | [diff] [blame] | 536 | iim: iim@10028000 { |
| 537 | compatible = "fsl,imx27-iim"; |
| 538 | reg = <0x10028000 0x1000>; |
| 539 | interrupts = <62>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 540 | clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; |
Alexander Shiyan | d36afcd | 2013-07-02 20:02:24 +0400 | [diff] [blame] | 541 | }; |
| 542 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 543 | fec: ethernet@1002b000 { |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 544 | compatible = "fsl,imx27-fec"; |
Philippe Reynes | a29ef81 | 2015-05-13 00:18:26 +0200 | [diff] [blame] | 545 | reg = <0x1002b000 0x1000>; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 546 | interrupts = <50>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 547 | clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, |
| 548 | <&clks IMX27_CLK_FEC_AHB_GATE>; |
Alexander Shiyan | c0b357c | 2013-07-20 11:17:55 +0400 | [diff] [blame] | 549 | clock-names = "ipg", "ahb"; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 550 | status = "disabled"; |
| 551 | }; |
| 552 | }; |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 553 | |
| 554 | nfc: nand@d8000000 { |
Uwe Kleine-König | 3778736 | 2012-04-23 11:23:42 +0200 | [diff] [blame] | 555 | #address-cells = <1>; |
| 556 | #size-cells = <1>; |
Uwe Kleine-König | 3778736 | 2012-04-23 11:23:42 +0200 | [diff] [blame] | 557 | compatible = "fsl,imx27-nand"; |
| 558 | reg = <0xd8000000 0x1000>; |
| 559 | interrupts = <29>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 560 | clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; |
Uwe Kleine-König | 3778736 | 2012-04-23 11:23:42 +0200 | [diff] [blame] | 561 | status = "disabled"; |
| 562 | }; |
Alexander Shiyan | ff1450f | 2013-06-23 10:54:48 +0400 | [diff] [blame] | 563 | |
Alexander Shiyan | 0912f59 | 2013-07-02 20:02:25 +0400 | [diff] [blame] | 564 | weim: weim@d8002000 { |
| 565 | #address-cells = <2>; |
| 566 | #size-cells = <1>; |
| 567 | compatible = "fsl,imx27-weim"; |
| 568 | reg = <0xd8002000 0x1000>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 569 | clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; |
Alexander Shiyan | 0912f59 | 2013-07-02 20:02:25 +0400 | [diff] [blame] | 570 | ranges = < |
| 571 | 0 0 0xc0000000 0x08000000 |
| 572 | 1 0 0xc8000000 0x08000000 |
| 573 | 2 0 0xd0000000 0x02000000 |
| 574 | 3 0 0xd2000000 0x02000000 |
| 575 | 4 0 0xd4000000 0x02000000 |
| 576 | 5 0 0xd6000000 0x02000000 |
| 577 | >; |
| 578 | status = "disabled"; |
| 579 | }; |
| 580 | |
Alexander Shiyan | ff1450f | 2013-06-23 10:54:48 +0400 | [diff] [blame] | 581 | iram: iram@ffff4c00 { |
| 582 | compatible = "mmio-sram"; |
| 583 | reg = <0xffff4c00 0xb400>; |
| 584 | }; |
Sascha Hauer | 9f0749e | 2012-02-28 21:57:50 +0100 | [diff] [blame] | 585 | }; |
| 586 | }; |