Andy Fleming | 2654d63 | 2006-08-18 18:04:34 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * MPC8555 CDS Device Tree Source |
| 3 | * |
| 4 | * Copyright 2006 Freescale Semiconductor Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
| 12 | |
| 13 | / { |
| 14 | model = "MPC8555CDS"; |
| 15 | compatible = "MPC85xxCDS"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | linux,phandle = <100>; |
| 19 | |
| 20 | cpus { |
| 21 | #cpus = <1>; |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; |
| 24 | linux,phandle = <200>; |
| 25 | |
| 26 | PowerPC,8555@0 { |
| 27 | device_type = "cpu"; |
| 28 | reg = <0>; |
| 29 | d-cache-line-size = <20>; // 32 bytes |
| 30 | i-cache-line-size = <20>; // 32 bytes |
| 31 | d-cache-size = <8000>; // L1, 32K |
| 32 | i-cache-size = <8000>; // L1, 32K |
| 33 | timebase-frequency = <0>; // 33 MHz, from uboot |
| 34 | bus-frequency = <0>; // 166 MHz |
| 35 | clock-frequency = <0>; // 825 MHz, from uboot |
| 36 | 32-bit; |
| 37 | linux,phandle = <201>; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | memory { |
| 42 | device_type = "memory"; |
| 43 | linux,phandle = <300>; |
| 44 | reg = <00000000 08000000>; // 128M at 0x0 |
| 45 | }; |
| 46 | |
| 47 | soc8555@e0000000 { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | #interrupt-cells = <2>; |
| 51 | device_type = "soc"; |
| 52 | ranges = <0 e0000000 00100000>; |
| 53 | reg = <e0000000 00100000>; // CCSRBAR 1M |
| 54 | bus-frequency = <0>; |
| 55 | |
| 56 | i2c@3000 { |
| 57 | device_type = "i2c"; |
| 58 | compatible = "fsl-i2c"; |
| 59 | reg = <3000 100>; |
| 60 | interrupts = <1b 2>; |
| 61 | interrupt-parent = <40000>; |
| 62 | dfsrr; |
| 63 | }; |
| 64 | |
| 65 | mdio@24520 { |
| 66 | #address-cells = <1>; |
| 67 | #size-cells = <0>; |
| 68 | device_type = "mdio"; |
| 69 | compatible = "gianfar"; |
| 70 | reg = <24520 20>; |
| 71 | linux,phandle = <24520>; |
| 72 | ethernet-phy@0 { |
| 73 | linux,phandle = <2452000>; |
| 74 | interrupt-parent = <40000>; |
| 75 | interrupts = <35 0>; |
| 76 | reg = <0>; |
| 77 | device_type = "ethernet-phy"; |
| 78 | }; |
| 79 | ethernet-phy@1 { |
| 80 | linux,phandle = <2452001>; |
| 81 | interrupt-parent = <40000>; |
| 82 | interrupts = <35 0>; |
| 83 | reg = <1>; |
| 84 | device_type = "ethernet-phy"; |
| 85 | }; |
| 86 | }; |
| 87 | |
| 88 | ethernet@24000 { |
| 89 | #address-cells = <1>; |
| 90 | #size-cells = <0>; |
| 91 | device_type = "network"; |
| 92 | model = "TSEC"; |
| 93 | compatible = "gianfar"; |
| 94 | reg = <24000 1000>; |
| 95 | local-mac-address = [ 00 E0 0C 00 73 00 ]; |
| 96 | interrupts = <0d 2 0e 2 12 2>; |
| 97 | interrupt-parent = <40000>; |
| 98 | phy-handle = <2452000>; |
| 99 | }; |
| 100 | |
| 101 | ethernet@25000 { |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <0>; |
| 104 | device_type = "network"; |
| 105 | model = "TSEC"; |
| 106 | compatible = "gianfar"; |
| 107 | reg = <25000 1000>; |
| 108 | local-mac-address = [ 00 E0 0C 00 73 01 ]; |
| 109 | interrupts = <13 2 14 2 18 2>; |
| 110 | interrupt-parent = <40000>; |
| 111 | phy-handle = <2452001>; |
| 112 | }; |
| 113 | |
| 114 | serial@4500 { |
| 115 | device_type = "serial"; |
| 116 | compatible = "ns16550"; |
| 117 | reg = <4500 100>; // reg base, size |
| 118 | clock-frequency = <0>; // should we fill in in uboot? |
| 119 | interrupts = <1a 2>; |
| 120 | interrupt-parent = <40000>; |
| 121 | }; |
| 122 | |
| 123 | serial@4600 { |
| 124 | device_type = "serial"; |
| 125 | compatible = "ns16550"; |
| 126 | reg = <4600 100>; // reg base, size |
| 127 | clock-frequency = <0>; // should we fill in in uboot? |
| 128 | interrupts = <1a 2>; |
| 129 | interrupt-parent = <40000>; |
| 130 | }; |
| 131 | |
| 132 | pci@8000 { |
| 133 | linux,phandle = <8000>; |
| 134 | interrupt-map-mask = <1f800 0 0 7>; |
| 135 | interrupt-map = < |
| 136 | |
| 137 | /* IDSEL 0x10 */ |
| 138 | 08000 0 0 1 40000 30 1 |
| 139 | 08000 0 0 2 40000 31 1 |
| 140 | 08000 0 0 3 40000 32 1 |
| 141 | 08000 0 0 4 40000 33 1 |
| 142 | |
| 143 | /* IDSEL 0x11 */ |
| 144 | 08800 0 0 1 40000 30 1 |
| 145 | 08800 0 0 2 40000 31 1 |
| 146 | 08800 0 0 3 40000 32 1 |
| 147 | 08800 0 0 4 40000 33 1 |
| 148 | |
| 149 | /* IDSEL 0x12 (Slot 1) */ |
| 150 | 09000 0 0 1 40000 30 1 |
| 151 | 09000 0 0 2 40000 31 1 |
| 152 | 09000 0 0 3 40000 32 1 |
| 153 | 09000 0 0 4 40000 33 1 |
| 154 | |
| 155 | /* IDSEL 0x13 (Slot 2) */ |
| 156 | 09800 0 0 1 40000 31 1 |
| 157 | 09800 0 0 2 40000 32 1 |
| 158 | 09800 0 0 3 40000 33 1 |
| 159 | 09800 0 0 4 40000 30 1 |
| 160 | |
| 161 | /* IDSEL 0x14 (Slot 3) */ |
| 162 | 0a000 0 0 1 40000 32 1 |
| 163 | 0a000 0 0 2 40000 33 1 |
| 164 | 0a000 0 0 3 40000 30 1 |
| 165 | 0a000 0 0 4 40000 31 1 |
| 166 | |
| 167 | /* IDSEL 0x15 (Slot 4) */ |
| 168 | 0a800 0 0 1 40000 33 1 |
| 169 | 0a800 0 0 2 40000 30 1 |
| 170 | 0a800 0 0 3 40000 31 1 |
| 171 | 0a800 0 0 4 40000 32 1 |
| 172 | |
| 173 | /* Bus 1 (Tundra Bridge) */ |
| 174 | /* IDSEL 0x12 (ISA bridge) */ |
| 175 | 19000 0 0 1 40000 30 1 |
| 176 | 19000 0 0 2 40000 31 1 |
| 177 | 19000 0 0 3 40000 32 1 |
| 178 | 19000 0 0 4 40000 33 1>; |
| 179 | interrupt-parent = <40000>; |
| 180 | interrupts = <08 2>; |
| 181 | bus-range = <0 0>; |
| 182 | ranges = <02000000 0 80000000 80000000 0 20000000 |
| 183 | 01000000 0 00000000 e2000000 0 00100000>; |
| 184 | clock-frequency = <3f940aa>; |
| 185 | #interrupt-cells = <1>; |
| 186 | #size-cells = <2>; |
| 187 | #address-cells = <3>; |
| 188 | reg = <8000 1000>; |
| 189 | compatible = "85xx"; |
| 190 | device_type = "pci"; |
| 191 | |
| 192 | i8259@19000 { |
| 193 | clock-frequency = <0>; |
| 194 | interrupt-controller; |
| 195 | device_type = "interrupt-controller"; |
| 196 | reg = <19000 0 0 0 1>; |
| 197 | #address-cells = <0>; |
| 198 | #interrupt-cells = <2>; |
| 199 | built-in; |
| 200 | compatible = "chrp,iic"; |
| 201 | big-endian; |
| 202 | interrupts = <1>; |
| 203 | interrupt-parent = <8000>; |
| 204 | }; |
| 205 | }; |
| 206 | |
| 207 | pci@9000 { |
| 208 | linux,phandle = <9000>; |
| 209 | interrupt-map-mask = <f800 0 0 7>; |
| 210 | interrupt-map = < |
| 211 | |
| 212 | /* IDSEL 0x15 */ |
| 213 | a800 0 0 1 40000 3b 1 |
| 214 | a800 0 0 2 40000 3b 1 |
| 215 | a800 0 0 3 40000 3b 1 |
| 216 | a800 0 0 4 40000 3b 1>; |
| 217 | interrupt-parent = <40000>; |
| 218 | interrupts = <09 2>; |
| 219 | bus-range = <0 0>; |
| 220 | ranges = <02000000 0 a0000000 a0000000 0 20000000 |
| 221 | 01000000 0 00000000 e3000000 0 00100000>; |
| 222 | clock-frequency = <3f940aa>; |
| 223 | #interrupt-cells = <1>; |
| 224 | #size-cells = <2>; |
| 225 | #address-cells = <3>; |
| 226 | reg = <9000 1000>; |
| 227 | compatible = "85xx"; |
| 228 | device_type = "pci"; |
| 229 | }; |
| 230 | |
| 231 | pic@40000 { |
| 232 | linux,phandle = <40000>; |
| 233 | clock-frequency = <0>; |
| 234 | interrupt-controller; |
| 235 | #address-cells = <0>; |
| 236 | #interrupt-cells = <2>; |
| 237 | reg = <40000 40000>; |
| 238 | built-in; |
| 239 | compatible = "chrp,open-pic"; |
| 240 | device_type = "open-pic"; |
| 241 | big-endian; |
| 242 | }; |
| 243 | }; |
| 244 | }; |