blob: 94a71c91beb580b2f88f080cbbeeeeefa5bc0ba2 [file] [log] [blame]
Stephen Warrenc80efba2012-04-20 16:57:38 -06001/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
20 "gmc", "gmd", "gpu";
21 nvidia,function = "gmi";
22 };
23 atc {
24 nvidia,pins = "atc", "atd";
25 nvidia,function = "sdio4";
26 };
27 cdev1 {
28 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out";
30 };
31 cdev2 {
32 nvidia,pins = "cdev2";
33 nvidia,function = "osc";
34 };
35 crtp {
36 nvidia,pins = "crtp";
37 nvidia,function = "crt";
38 };
39 csus {
40 nvidia,pins = "csus";
41 nvidia,function = "vi_sensor_clk";
42 };
43 dap1 {
44 nvidia,pins = "dap1";
45 nvidia,function = "dap1";
46 };
47 dap2 {
48 nvidia,pins = "dap2";
49 nvidia,function = "dap2";
50 };
51 dap3 {
52 nvidia,pins = "dap3";
53 nvidia,function = "dap3";
54 };
55 dap4 {
56 nvidia,pins = "dap4";
57 nvidia,function = "dap4";
58 };
59 ddc {
60 nvidia,pins = "ddc";
61 nvidia,function = "i2c2";
62 };
63 dta {
64 nvidia,pins = "dta", "dtb", "dtc", "dtd";
65 nvidia,function = "vi";
66 };
67 dte {
68 nvidia,pins = "dte";
69 nvidia,function = "rsvd1";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gme {
76 nvidia,pins = "gme";
77 nvidia,function = "dap5";
78 };
79 gpu7 {
80 nvidia,pins = "gpu7";
81 nvidia,function = "rtck";
82 };
83 gpv {
84 nvidia,pins = "gpv";
85 nvidia,function = "pcie";
86 };
87 hdint {
88 nvidia,pins = "hdint", "pta";
89 nvidia,function = "hdmi";
90 };
91 i2cp {
92 nvidia,pins = "i2cp";
93 nvidia,function = "i2cp";
94 };
95 irrx {
96 nvidia,pins = "irrx", "irtx";
97 nvidia,function = "uartb";
98 };
99 kbca {
100 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
101 nvidia,function = "kbc";
102 };
103 kbcb {
104 nvidia,pins = "kbcb", "kbcd";
105 nvidia,function = "sdio2";
106 };
107 lcsn {
108 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
109 "spia", "spib", "spic";
110 nvidia,function = "spi3";
111 };
112 ld0 {
113 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
114 "ld5", "ld6", "ld7", "ld8", "ld9",
115 "ld10", "ld11", "ld12", "ld13", "ld14",
116 "ld15", "ld16", "ld17", "ldc", "ldi",
117 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
118 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
119 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "owr";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
137 "slxc", "slxd", "slxk";
138 nvidia,function = "sdio3";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 spdi {
145 nvidia,pins = "spdi", "spdo";
146 nvidia,function = "rsvd2";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spig", "spih";
150 nvidia,function = "spi2_alt";
151 };
152 spif {
153 nvidia,pins = "spif";
154 nvidia,function = "spi2";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab";
158 nvidia,function = "uarta";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 uda {
169 nvidia,pins = "uda";
170 nvidia,function = "spi1";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
174 "gmb", "gmc", "gmd", "irrx", "irtx",
175 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
176 "kbcf", "sdc", "sdd", "spie", "spig",
177 "spih", "uaa", "uab", "uad", "uca",
178 "ucb";
179 nvidia,pull = <2>;
180 nvidia,tristate = <0>;
181 };
182 conf_atd {
183 nvidia,pins = "atd", "ate", "cdev1", "csus",
184 "dap1", "dap2", "dap3", "dap4", "dte",
185 "dtf", "gpu", "gpu7", "gpv", "i2cp",
186 "rm", "sdio1", "slxa", "slxc", "slxd",
187 "slxk", "spdi", "spdo", "uac", "uda";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "spia", "spib";
193 nvidia,pull = <1>;
194 nvidia,tristate = <1>;
195 };
196 conf_ck32 {
197 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
198 "pmcb", "pmcc", "pmcd", "xm2c",
199 "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_crtp {
203 nvidia,pins = "crtp";
204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_dta {
208 nvidia,pins = "dta", "dtb", "dtc", "dtd",
209 "spid", "spif";
210 nvidia,pull = <1>;
211 nvidia,tristate = <0>;
212 };
213 conf_gme {
214 nvidia,pins = "gme", "owc", "pta", "spic";
215 nvidia,pull = <2>;
216 nvidia,tristate = <1>;
217 };
218 conf_ld17_0 {
219 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
220 "ld23_22";
221 nvidia,pull = <1>;
222 };
223 conf_ls {
224 nvidia,pins = "ls", "pmce";
225 nvidia,pull = <2>;
226 };
227 drive_dap1 {
228 nvidia,pins = "drive_dap1";
229 nvidia,high-speed-mode = <0>;
230 nvidia,schmitt = <1>;
231 nvidia,low-power-mode = <0>;
232 nvidia,pull-down-strength = <0>;
233 nvidia,pull-up-strength = <0>;
234 nvidia,slew-rate-rising = <0>;
235 nvidia,slew-rate-falling = <0>;
236 };
237 };
238 };
239
240 i2s@70002800 {
241 status = "okay";
242 };
243
244 serial@70006000 {
245 status = "okay";
246 clock-frequency = <216000000>;
247 };
248
249 i2c@7000d000 {
250 status = "okay";
251 clock-frequency = <100000>;
252
253 codec: codec@1a {
254 compatible = "wlf,wm8753";
255 reg = <0x1a>;
256 };
257
258 tca6416: gpio@20 {
259 compatible = "ti,tca6416";
260 reg = <0x20>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600264
265 max8907@3c {
266 compatible = "maxim,max8907";
267 reg = <0x3c>;
268 interrupts = <0 86 0x4>;
269
Stephen Warrenb37ed4a2012-09-11 13:13:05 -0600270 maxim,system-power-controller;
271
Stephen Warrene7765b32012-06-25 16:41:25 -0600272 mbatt-supply = <&usb0_vbus_reg>;
273 in-v1-supply = <&mbatt_reg>;
274 in-v2-supply = <&mbatt_reg>;
275 in-v3-supply = <&mbatt_reg>;
276 in1-supply = <&mbatt_reg>;
277 in2-supply = <&nvvdd_sv3_reg>;
278 in3-supply = <&mbatt_reg>;
279 in4-supply = <&mbatt_reg>;
280 in5-supply = <&mbatt_reg>;
281 in6-supply = <&mbatt_reg>;
282 in7-supply = <&mbatt_reg>;
283 in8-supply = <&mbatt_reg>;
284 in9-supply = <&mbatt_reg>;
285 in10-supply = <&mbatt_reg>;
286 in11-supply = <&mbatt_reg>;
287 in12-supply = <&mbatt_reg>;
288 in13-supply = <&mbatt_reg>;
289 in14-supply = <&mbatt_reg>;
290 in15-supply = <&mbatt_reg>;
291 in16-supply = <&mbatt_reg>;
292 in17-supply = <&nvvdd_sv3_reg>;
293 in18-supply = <&nvvdd_sv3_reg>;
294 in19-supply = <&mbatt_reg>;
295 in20-supply = <&mbatt_reg>;
296
297 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600298 mbatt_reg: mbatt {
Stephen Warrene7765b32012-06-25 16:41:25 -0600299 regulator-name = "vbat_pmu";
300 regulator-always-on;
301 };
302
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600303 sd1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600304 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
305 regulator-min-microvolt = <1000000>;
306 regulator-max-microvolt = <1000000>;
307 regulator-always-on;
308 };
309
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600310 sd2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600311 regulator-name = "nvvdd_sv2,vdd_core";
312 regulator-min-microvolt = <1200000>;
313 regulator-max-microvolt = <1200000>;
314 regulator-always-on;
315 };
316
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600317 nvvdd_sv3_reg: sd3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600318 regulator-name = "nvvdd_sv3";
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <1800000>;
321 regulator-always-on;
322 };
323
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600324 ldo1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600325 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
326 regulator-min-microvolt = <3300000>;
327 regulator-max-microvolt = <3300000>;
328 regulator-always-on;
329 };
330
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600331 ldo2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600332 regulator-name = "nvvdd_ldo2,avdd_pll*";
333 regulator-min-microvolt = <1100000>;
334 regulator-max-microvolt = <1100000>;
335 regulator-always-on;
336 };
337
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600338 ldo3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600339 regulator-name = "nvvdd_ldo3,vcom_1v8b";
340 regulator-min-microvolt = <1800000>;
341 regulator-max-microvolt = <1800000>;
342 regulator-always-on;
343 };
344
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600345 ldo4 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600346 regulator-name = "nvvdd_ldo4,avdd_usb*";
347 regulator-min-microvolt = <3300000>;
348 regulator-max-microvolt = <3300000>;
349 regulator-always-on;
350 };
351
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600352 ldo5 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600353 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
354 regulator-min-microvolt = <2800000>;
355 regulator-max-microvolt = <2800000>;
356 regulator-always-on;
357 };
358
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600359 ldo6 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600360 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600365 ldo7 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600366 regulator-name = "nvvdd_ldo7,avddio_audio";
367 regulator-min-microvolt = <2800000>;
368 regulator-max-microvolt = <2800000>;
369 regulator-always-on;
370 };
371
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600372 ldo8 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600373 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
374 regulator-min-microvolt = <3000000>;
375 regulator-max-microvolt = <3000000>;
376 };
377
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600378 ldo9 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600379 regulator-name = "nvvdd_ldo9,avdd_cam*";
380 regulator-min-microvolt = <2800000>;
381 regulator-max-microvolt = <2800000>;
382 };
383
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600384 ldo10 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600385 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
386 regulator-min-microvolt = <3000000>;
387 regulator-max-microvolt = <3000000>;
388 regulator-always-on;
389 };
390
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600391 ldo11 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600392 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
393 regulator-min-microvolt = <3300000>;
394 regulator-max-microvolt = <3300000>;
395 };
396
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600397 ldo12 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600398 regulator-name = "nvvdd_ldo12,vddio_sdio";
399 regulator-min-microvolt = <2800000>;
400 regulator-max-microvolt = <2800000>;
401 regulator-always-on;
402 };
403
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600404 ldo13 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600405 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
406 regulator-min-microvolt = <2800000>;
407 regulator-max-microvolt = <2800000>;
408 };
409
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600410 ldo14 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600411 regulator-name = "nvvdd_ldo14,avdd_vdac";
412 regulator-min-microvolt = <2800000>;
413 regulator-max-microvolt = <2800000>;
414 };
415
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600416 ldo15 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600417 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
418 regulator-min-microvolt = <3300000>;
419 regulator-max-microvolt = <3300000>;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 ldo16 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600423 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
424 regulator-min-microvolt = <1300000>;
425 regulator-max-microvolt = <1300000>;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 ldo17 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600429 regulator-name = "nvvdd_ldo17,vddio_mipi";
430 regulator-min-microvolt = <1200000>;
431 regulator-max-microvolt = <1200000>;
432 };
433
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600434 ldo18 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600435 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
436 regulator-min-microvolt = <1800000>;
437 regulator-max-microvolt = <1800000>;
438 };
439
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600440 ldo19 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600441 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
442 regulator-min-microvolt = <2800000>;
443 regulator-max-microvolt = <2800000>;
444 };
445
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600446 ldo20 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600447 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
448 regulator-min-microvolt = <1200000>;
449 regulator-max-microvolt = <1200000>;
450 regulator-always-on;
451 };
452
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600453 out5v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600454 regulator-name = "usb0_vbus_reg";
455 };
456
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600457 out33v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600458 regulator-name = "pmu_out3v3";
459 };
460
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600461 bbat {
Stephen Warrene7765b32012-06-25 16:41:25 -0600462 regulator-name = "pmu_bbat";
463 regulator-min-microvolt = <2400000>;
464 regulator-max-microvolt = <2400000>;
465 regulator-always-on;
466 };
467
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600468 sdby {
Stephen Warrene7765b32012-06-25 16:41:25 -0600469 regulator-name = "vdd_aon";
470 regulator-always-on;
471 };
472
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600473 vrtc {
Stephen Warrene7765b32012-06-25 16:41:25 -0600474 regulator-name = "vrtc,pmu_vccadc";
475 regulator-always-on;
476 };
477 };
478 };
479 };
480
481 pmc {
482 nvidia,invert-interrupt;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600483 };
484
485 usb@c5000000 {
486 status = "okay";
487 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
488 };
489
490 usb@c5008000 {
491 status = "okay";
492 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
493 };
494
495 sdhci@c8000400 {
496 status = "okay";
497 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
498 bus-width = <8>;
499 };
500
501 sdhci@c8000600 {
502 status = "okay";
503 bus-width = <8>;
504 };
505
Stephen Warrene7765b32012-06-25 16:41:25 -0600506 regulators {
507 compatible = "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 usb0_vbus_reg: regulator {
512 compatible = "regulator-fixed";
513 reg = <0>;
514 regulator-name = "usb0_vbus";
515 regulator-min-microvolt = <5000000>;
516 regulator-max-microvolt = <5000000>;
517 regulator-always-on;
518 };
519 };
520
Stephen Warrenc80efba2012-04-20 16:57:38 -0600521 sound {
522 compatible = "nvidia,tegra-audio-wm8753-whistler",
523 "nvidia,tegra-audio-wm8753";
524 nvidia,model = "NVIDIA Tegra Whistler";
525
526 nvidia,audio-routing =
527 "Headphone Jack", "LOUT1",
528 "Headphone Jack", "ROUT1",
529 "MIC2", "Mic Jack",
530 "MIC2N", "Mic Jack";
531
532 nvidia,i2s-controller = <&tegra_i2s1>;
533 nvidia,audio-codec = <&codec>;
534 };
535};